1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * PIC32 pinctrl driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Joshua Henderson, <joshua.henderson@microchip.com> 6*4882a593Smuzhiyun * Copyright (C) 2015 Microchip Technology Inc. All rights reserved. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun #ifndef PINCTRL_PINCTRL_PIC32_H 9*4882a593Smuzhiyun #define PINCTRL_PINCTRL_PIC32_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* PORT Registers */ 12*4882a593Smuzhiyun #define ANSEL_REG 0x00 13*4882a593Smuzhiyun #define TRIS_REG 0x10 14*4882a593Smuzhiyun #define PORT_REG 0x20 15*4882a593Smuzhiyun #define LAT_REG 0x30 16*4882a593Smuzhiyun #define ODCU_REG 0x40 17*4882a593Smuzhiyun #define CNPU_REG 0x50 18*4882a593Smuzhiyun #define CNPD_REG 0x60 19*4882a593Smuzhiyun #define CNCON_REG 0x70 20*4882a593Smuzhiyun #define CNEN_REG 0x80 21*4882a593Smuzhiyun #define CNSTAT_REG 0x90 22*4882a593Smuzhiyun #define CNNE_REG 0xA0 23*4882a593Smuzhiyun #define CNF_REG 0xB0 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Input PPS Registers */ 26*4882a593Smuzhiyun #define INT1R 0x04 27*4882a593Smuzhiyun #define INT2R 0x08 28*4882a593Smuzhiyun #define INT3R 0x0C 29*4882a593Smuzhiyun #define INT4R 0x10 30*4882a593Smuzhiyun #define T2CKR 0x18 31*4882a593Smuzhiyun #define T3CKR 0x1C 32*4882a593Smuzhiyun #define T4CKR 0x20 33*4882a593Smuzhiyun #define T5CKR 0x24 34*4882a593Smuzhiyun #define T6CKR 0x28 35*4882a593Smuzhiyun #define T7CKR 0x2C 36*4882a593Smuzhiyun #define T8CKR 0x30 37*4882a593Smuzhiyun #define T9CKR 0x34 38*4882a593Smuzhiyun #define IC1R 0x38 39*4882a593Smuzhiyun #define IC2R 0x3C 40*4882a593Smuzhiyun #define IC3R 0x40 41*4882a593Smuzhiyun #define IC4R 0x44 42*4882a593Smuzhiyun #define IC5R 0x48 43*4882a593Smuzhiyun #define IC6R 0x4C 44*4882a593Smuzhiyun #define IC7R 0x50 45*4882a593Smuzhiyun #define IC8R 0x54 46*4882a593Smuzhiyun #define IC9R 0x58 47*4882a593Smuzhiyun #define OCFAR 0x60 48*4882a593Smuzhiyun #define U1RXR 0x68 49*4882a593Smuzhiyun #define U1CTSR 0x6C 50*4882a593Smuzhiyun #define U2RXR 0x70 51*4882a593Smuzhiyun #define U2CTSR 0x74 52*4882a593Smuzhiyun #define U3RXR 0x78 53*4882a593Smuzhiyun #define U3CTSR 0x7C 54*4882a593Smuzhiyun #define U4RXR 0x80 55*4882a593Smuzhiyun #define U4CTSR 0x84 56*4882a593Smuzhiyun #define U5RXR 0x88 57*4882a593Smuzhiyun #define U5CTSR 0x8C 58*4882a593Smuzhiyun #define U6RXR 0x90 59*4882a593Smuzhiyun #define U6CTSR 0x94 60*4882a593Smuzhiyun #define SDI1R 0x9C 61*4882a593Smuzhiyun #define SS1INR 0xA0 62*4882a593Smuzhiyun #define SDI2R 0xA8 63*4882a593Smuzhiyun #define SS2INR 0xAC 64*4882a593Smuzhiyun #define SDI3R 0xB4 65*4882a593Smuzhiyun #define SS3INR 0xB8 66*4882a593Smuzhiyun #define SDI4R 0xC0 67*4882a593Smuzhiyun #define SS4INR 0xC4 68*4882a593Smuzhiyun #define SDI5R 0xCC 69*4882a593Smuzhiyun #define SS5INR 0xD0 70*4882a593Smuzhiyun #define SDI6R 0xD8 71*4882a593Smuzhiyun #define SS6INR 0xDC 72*4882a593Smuzhiyun #define C1RXR 0xE0 73*4882a593Smuzhiyun #define C2RXR 0xE4 74*4882a593Smuzhiyun #define REFCLKI1R 0xE8 75*4882a593Smuzhiyun #define REFCLKI3R 0xF0 76*4882a593Smuzhiyun #define REFCLKI4R 0xF4 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /* Output PPS Registers */ 79*4882a593Smuzhiyun #define RPA14R 0x138 80*4882a593Smuzhiyun #define RPA15R 0x13C 81*4882a593Smuzhiyun #define RPB0R 0x140 82*4882a593Smuzhiyun #define RPB1R 0x144 83*4882a593Smuzhiyun #define RPB2R 0x148 84*4882a593Smuzhiyun #define RPB3R 0x14C 85*4882a593Smuzhiyun #define RPB5R 0x154 86*4882a593Smuzhiyun #define RPB6R 0x158 87*4882a593Smuzhiyun #define RPB7R 0x15C 88*4882a593Smuzhiyun #define RPB8R 0x160 89*4882a593Smuzhiyun #define RPB9R 0x164 90*4882a593Smuzhiyun #define RPB10R 0x168 91*4882a593Smuzhiyun #define RPB14R 0x178 92*4882a593Smuzhiyun #define RPB15R 0x17C 93*4882a593Smuzhiyun #define RPC1R 0x184 94*4882a593Smuzhiyun #define RPC2R 0x188 95*4882a593Smuzhiyun #define RPC3R 0x18C 96*4882a593Smuzhiyun #define RPC4R 0x190 97*4882a593Smuzhiyun #define RPC13R 0x1B4 98*4882a593Smuzhiyun #define RPC14R 0x1B8 99*4882a593Smuzhiyun #define RPD0R 0x1C0 100*4882a593Smuzhiyun #define RPD1R 0x1C4 101*4882a593Smuzhiyun #define RPD2R 0x1C8 102*4882a593Smuzhiyun #define RPD3R 0x1CC 103*4882a593Smuzhiyun #define RPD4R 0x1D0 104*4882a593Smuzhiyun #define RPD5R 0x1D4 105*4882a593Smuzhiyun #define RPD6R 0x1D8 106*4882a593Smuzhiyun #define RPD7R 0x1DC 107*4882a593Smuzhiyun #define RPD9R 0x1E4 108*4882a593Smuzhiyun #define RPD10R 0x1E8 109*4882a593Smuzhiyun #define RPD11R 0x1EC 110*4882a593Smuzhiyun #define RPD12R 0x1F0 111*4882a593Smuzhiyun #define RPD14R 0x1F8 112*4882a593Smuzhiyun #define RPD15R 0x1FC 113*4882a593Smuzhiyun #define RPE3R 0x20C 114*4882a593Smuzhiyun #define RPE5R 0x214 115*4882a593Smuzhiyun #define RPE8R 0x220 116*4882a593Smuzhiyun #define RPE9R 0x224 117*4882a593Smuzhiyun #define RPF0R 0x240 118*4882a593Smuzhiyun #define RPF1R 0x244 119*4882a593Smuzhiyun #define RPF2R 0x248 120*4882a593Smuzhiyun #define RPF3R 0x24C 121*4882a593Smuzhiyun #define RPF4R 0x250 122*4882a593Smuzhiyun #define RPF5R 0x254 123*4882a593Smuzhiyun #define RPF8R 0x260 124*4882a593Smuzhiyun #define RPF12R 0x270 125*4882a593Smuzhiyun #define RPF13R 0x274 126*4882a593Smuzhiyun #define RPG0R 0x280 127*4882a593Smuzhiyun #define RPG1R 0x284 128*4882a593Smuzhiyun #define RPG6R 0x298 129*4882a593Smuzhiyun #define RPG7R 0x29C 130*4882a593Smuzhiyun #define RPG8R 0x2A0 131*4882a593Smuzhiyun #define RPG9R 0x2A4 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #endif /* PINCTRL_PINCTRL_PIC32_H */ 134