1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright(c) 2019 Intel Corporation. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __PINCTRL_EQUILIBRIUM_H 7*4882a593Smuzhiyun #define __PINCTRL_EQUILIBRIUM_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun /* PINPAD register offset */ 10*4882a593Smuzhiyun #define REG_PMX_BASE 0x0 /* Port Multiplexer Control Register */ 11*4882a593Smuzhiyun #define REG_PUEN 0x80 /* PULL UP Enable Register */ 12*4882a593Smuzhiyun #define REG_PDEN 0x84 /* PULL DOWN Enable Register */ 13*4882a593Smuzhiyun #define REG_SRC 0x88 /* Slew Rate Control Register */ 14*4882a593Smuzhiyun #define REG_DCC0 0x8C /* Drive Current Control Register 0 */ 15*4882a593Smuzhiyun #define REG_DCC1 0x90 /* Drive Current Control Register 1 */ 16*4882a593Smuzhiyun #define REG_OD 0x94 /* Open Drain Enable Register */ 17*4882a593Smuzhiyun #define REG_AVAIL 0x98 /* Pad Control Availability Register */ 18*4882a593Smuzhiyun #define DRV_CUR_PINS 16 /* Drive Current pin number per register */ 19*4882a593Smuzhiyun #define REG_DRCC(x) (REG_DCC0 + (x) * 4) /* Driver current macro */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* GPIO register offset */ 22*4882a593Smuzhiyun #define GPIO_OUT 0x0 /* Data Output Register */ 23*4882a593Smuzhiyun #define GPIO_IN 0x4 /* Data Input Register */ 24*4882a593Smuzhiyun #define GPIO_DIR 0x8 /* Direction Register */ 25*4882a593Smuzhiyun #define GPIO_EXINTCR0 0x18 /* External Interrupt Control Register 0 */ 26*4882a593Smuzhiyun #define GPIO_EXINTCR1 0x1C /* External Interrupt Control Register 1 */ 27*4882a593Smuzhiyun #define GPIO_IRNCR 0x20 /* IRN Capture Register */ 28*4882a593Smuzhiyun #define GPIO_IRNICR 0x24 /* IRN Interrupt Control Register */ 29*4882a593Smuzhiyun #define GPIO_IRNEN 0x28 /* IRN Interrupt Enable Register */ 30*4882a593Smuzhiyun #define GPIO_IRNCFG 0x2C /* IRN Interrupt Configuration Register */ 31*4882a593Smuzhiyun #define GPIO_IRNRNSET 0x30 /* IRN Interrupt Enable Set Register */ 32*4882a593Smuzhiyun #define GPIO_IRNENCLR 0x34 /* IRN Interrupt Enable Clear Register */ 33*4882a593Smuzhiyun #define GPIO_OUTSET 0x40 /* Output Set Register */ 34*4882a593Smuzhiyun #define GPIO_OUTCLR 0x44 /* Output Clear Register */ 35*4882a593Smuzhiyun #define GPIO_DIRSET 0x48 /* Direction Set Register */ 36*4882a593Smuzhiyun #define GPIO_DIRCLR 0x4C /* Direction Clear Register */ 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* parse given pin's driver current value */ 39*4882a593Smuzhiyun #define PARSE_DRV_CURRENT(val, pin) (((val) >> ((pin) * 2)) & 0x3) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define GPIO_EDGE_TRIG 0 42*4882a593Smuzhiyun #define GPIO_LEVEL_TRIG 1 43*4882a593Smuzhiyun #define GPIO_SINGLE_EDGE 0 44*4882a593Smuzhiyun #define GPIO_BOTH_EDGE 1 45*4882a593Smuzhiyun #define GPIO_POSITIVE_TRIG 0 46*4882a593Smuzhiyun #define GPIO_NEGATIVE_TRIG 1 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define EQBR_GPIO_MODE 0 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun typedef enum { 51*4882a593Smuzhiyun OP_COUNT_NR_FUNCS, 52*4882a593Smuzhiyun OP_ADD_FUNCS, 53*4882a593Smuzhiyun OP_COUNT_NR_FUNC_GRPS, 54*4882a593Smuzhiyun OP_ADD_FUNC_GRPS, 55*4882a593Smuzhiyun OP_NONE, 56*4882a593Smuzhiyun } funcs_util_ops; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /** 59*4882a593Smuzhiyun * struct gpio_irq_type: gpio irq configuration 60*4882a593Smuzhiyun * @trig_type: level trigger or edge trigger 61*4882a593Smuzhiyun * @edge_type: sigle edge or both edge 62*4882a593Smuzhiyun * @logic_type: positive trigger or negative trigger 63*4882a593Smuzhiyun */ 64*4882a593Smuzhiyun struct gpio_irq_type { 65*4882a593Smuzhiyun unsigned int trig_type; 66*4882a593Smuzhiyun unsigned int edge_type; 67*4882a593Smuzhiyun unsigned int logic_type; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /** 71*4882a593Smuzhiyun * struct eqbr_pmx_func: represent a pin function. 72*4882a593Smuzhiyun * @name: name of the pin function, used to lookup the function. 73*4882a593Smuzhiyun * @groups: one or more names of pin groups that provide this function. 74*4882a593Smuzhiyun * @nr_groups: number of groups included in @groups. 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun struct eqbr_pmx_func { 77*4882a593Smuzhiyun const char *name; 78*4882a593Smuzhiyun const char **groups; 79*4882a593Smuzhiyun unsigned int nr_groups; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /** 83*4882a593Smuzhiyun * struct eqbr_pin_bank: represent a pin bank. 84*4882a593Smuzhiyun * @membase: base address of the pin bank register. 85*4882a593Smuzhiyun * @id: bank id, to idenify the unique bank. 86*4882a593Smuzhiyun * @pin_base: starting pin number of the pin bank. 87*4882a593Smuzhiyun * @nr_pins: number of the pins of the pin bank. 88*4882a593Smuzhiyun * @aval_pinmap: available pin bitmap of the pin bank. 89*4882a593Smuzhiyun */ 90*4882a593Smuzhiyun struct eqbr_pin_bank { 91*4882a593Smuzhiyun void __iomem *membase; 92*4882a593Smuzhiyun unsigned int id; 93*4882a593Smuzhiyun unsigned int pin_base; 94*4882a593Smuzhiyun unsigned int nr_pins; 95*4882a593Smuzhiyun u32 aval_pinmap; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /** 99*4882a593Smuzhiyun * struct eqbr_gpio_ctrl: represent a gpio controller. 100*4882a593Smuzhiyun * @node: device node of gpio controller. 101*4882a593Smuzhiyun * @bank: pointer to corresponding pin bank. 102*4882a593Smuzhiyun * @membase: base address of the gpio controller. 103*4882a593Smuzhiyun * @chip: gpio chip. 104*4882a593Smuzhiyun * @ic: irq chip. 105*4882a593Smuzhiyun * @name: gpio chip name. 106*4882a593Smuzhiyun * @virq: irq number of the gpio chip to parent's irq domain. 107*4882a593Smuzhiyun * @lock: spin lock to protect gpio register write. 108*4882a593Smuzhiyun */ 109*4882a593Smuzhiyun struct eqbr_gpio_ctrl { 110*4882a593Smuzhiyun struct device_node *node; 111*4882a593Smuzhiyun struct eqbr_pin_bank *bank; 112*4882a593Smuzhiyun void __iomem *membase; 113*4882a593Smuzhiyun struct gpio_chip chip; 114*4882a593Smuzhiyun struct irq_chip ic; 115*4882a593Smuzhiyun const char *name; 116*4882a593Smuzhiyun unsigned int virq; 117*4882a593Smuzhiyun raw_spinlock_t lock; /* protect gpio register */ 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun /** 121*4882a593Smuzhiyun * struct eqbr_pinctrl_drv_data: 122*4882a593Smuzhiyun * @dev: device instance representing the controller. 123*4882a593Smuzhiyun * @pctl_desc: pin controller descriptor. 124*4882a593Smuzhiyun * @pctl_dev: pin control class device 125*4882a593Smuzhiyun * @membase: base address of pin controller 126*4882a593Smuzhiyun * @pin_banks: list of pin banks of the driver. 127*4882a593Smuzhiyun * @nr_banks: number of pin banks. 128*4882a593Smuzhiyun * @gpio_ctrls: list of gpio controllers. 129*4882a593Smuzhiyun * @nr_gpio_ctrls: number of gpio controllers. 130*4882a593Smuzhiyun * @lock: protect pinctrl register write 131*4882a593Smuzhiyun */ 132*4882a593Smuzhiyun struct eqbr_pinctrl_drv_data { 133*4882a593Smuzhiyun struct device *dev; 134*4882a593Smuzhiyun struct pinctrl_desc pctl_desc; 135*4882a593Smuzhiyun struct pinctrl_dev *pctl_dev; 136*4882a593Smuzhiyun void __iomem *membase; 137*4882a593Smuzhiyun struct eqbr_pin_bank *pin_banks; 138*4882a593Smuzhiyun unsigned int nr_banks; 139*4882a593Smuzhiyun struct eqbr_gpio_ctrl *gpio_ctrls; 140*4882a593Smuzhiyun unsigned int nr_gpio_ctrls; 141*4882a593Smuzhiyun raw_spinlock_t lock; /* protect pinpad register */ 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #endif /* __PINCTRL_EQUILIBRIUM_H */ 145