1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * AXP20x pinctrl and GPIO driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
6*4882a593Smuzhiyun * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/bitops.h>
10*4882a593Smuzhiyun #include <linux/device.h>
11*4882a593Smuzhiyun #include <linux/gpio/driver.h>
12*4882a593Smuzhiyun #include <linux/init.h>
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/kernel.h>
15*4882a593Smuzhiyun #include <linux/mfd/axp20x.h>
16*4882a593Smuzhiyun #include <linux/module.h>
17*4882a593Smuzhiyun #include <linux/of.h>
18*4882a593Smuzhiyun #include <linux/of_device.h>
19*4882a593Smuzhiyun #include <linux/pinctrl/pinconf-generic.h>
20*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
21*4882a593Smuzhiyun #include <linux/pinctrl/pinmux.h>
22*4882a593Smuzhiyun #include <linux/platform_device.h>
23*4882a593Smuzhiyun #include <linux/regmap.h>
24*4882a593Smuzhiyun #include <linux/slab.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define AXP20X_GPIO_FUNCTIONS 0x7
27*4882a593Smuzhiyun #define AXP20X_GPIO_FUNCTION_OUT_LOW 0
28*4882a593Smuzhiyun #define AXP20X_GPIO_FUNCTION_OUT_HIGH 1
29*4882a593Smuzhiyun #define AXP20X_GPIO_FUNCTION_INPUT 2
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define AXP20X_FUNC_GPIO_OUT 0
32*4882a593Smuzhiyun #define AXP20X_FUNC_GPIO_IN 1
33*4882a593Smuzhiyun #define AXP20X_FUNC_LDO 2
34*4882a593Smuzhiyun #define AXP20X_FUNC_ADC 3
35*4882a593Smuzhiyun #define AXP20X_FUNCS_NB 4
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #define AXP20X_MUX_GPIO_OUT 0
38*4882a593Smuzhiyun #define AXP20X_MUX_GPIO_IN BIT(1)
39*4882a593Smuzhiyun #define AXP20X_MUX_ADC BIT(2)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define AXP813_MUX_ADC (BIT(2) | BIT(0))
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun struct axp20x_pctrl_desc {
44*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins;
45*4882a593Smuzhiyun unsigned int npins;
46*4882a593Smuzhiyun /* Stores the pins supporting LDO function. Bit offset is pin number. */
47*4882a593Smuzhiyun u8 ldo_mask;
48*4882a593Smuzhiyun /* Stores the pins supporting ADC function. Bit offset is pin number. */
49*4882a593Smuzhiyun u8 adc_mask;
50*4882a593Smuzhiyun u8 gpio_status_offset;
51*4882a593Smuzhiyun u8 adc_mux;
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun struct axp20x_pinctrl_function {
55*4882a593Smuzhiyun const char *name;
56*4882a593Smuzhiyun unsigned int muxval;
57*4882a593Smuzhiyun const char **groups;
58*4882a593Smuzhiyun unsigned int ngroups;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun struct axp20x_pctl {
62*4882a593Smuzhiyun struct gpio_chip chip;
63*4882a593Smuzhiyun struct regmap *regmap;
64*4882a593Smuzhiyun struct pinctrl_dev *pctl_dev;
65*4882a593Smuzhiyun struct device *dev;
66*4882a593Smuzhiyun const struct axp20x_pctrl_desc *desc;
67*4882a593Smuzhiyun struct axp20x_pinctrl_function funcs[AXP20X_FUNCS_NB];
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static const struct pinctrl_pin_desc axp209_pins[] = {
71*4882a593Smuzhiyun PINCTRL_PIN(0, "GPIO0"),
72*4882a593Smuzhiyun PINCTRL_PIN(1, "GPIO1"),
73*4882a593Smuzhiyun PINCTRL_PIN(2, "GPIO2"),
74*4882a593Smuzhiyun };
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static const struct pinctrl_pin_desc axp813_pins[] = {
77*4882a593Smuzhiyun PINCTRL_PIN(0, "GPIO0"),
78*4882a593Smuzhiyun PINCTRL_PIN(1, "GPIO1"),
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct axp20x_pctrl_desc axp20x_data = {
82*4882a593Smuzhiyun .pins = axp209_pins,
83*4882a593Smuzhiyun .npins = ARRAY_SIZE(axp209_pins),
84*4882a593Smuzhiyun .ldo_mask = BIT(0) | BIT(1),
85*4882a593Smuzhiyun .adc_mask = BIT(0) | BIT(1),
86*4882a593Smuzhiyun .gpio_status_offset = 4,
87*4882a593Smuzhiyun .adc_mux = AXP20X_MUX_ADC,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun static const struct axp20x_pctrl_desc axp813_data = {
91*4882a593Smuzhiyun .pins = axp813_pins,
92*4882a593Smuzhiyun .npins = ARRAY_SIZE(axp813_pins),
93*4882a593Smuzhiyun .ldo_mask = BIT(0) | BIT(1),
94*4882a593Smuzhiyun .adc_mask = BIT(0),
95*4882a593Smuzhiyun .gpio_status_offset = 0,
96*4882a593Smuzhiyun .adc_mux = AXP813_MUX_ADC,
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
axp20x_gpio_get_reg(unsigned int offset)99*4882a593Smuzhiyun static int axp20x_gpio_get_reg(unsigned int offset)
100*4882a593Smuzhiyun {
101*4882a593Smuzhiyun switch (offset) {
102*4882a593Smuzhiyun case 0:
103*4882a593Smuzhiyun return AXP20X_GPIO0_CTRL;
104*4882a593Smuzhiyun case 1:
105*4882a593Smuzhiyun return AXP20X_GPIO1_CTRL;
106*4882a593Smuzhiyun case 2:
107*4882a593Smuzhiyun return AXP20X_GPIO2_CTRL;
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun return -EINVAL;
111*4882a593Smuzhiyun }
112*4882a593Smuzhiyun
axp20x_gpio_input(struct gpio_chip * chip,unsigned int offset)113*4882a593Smuzhiyun static int axp20x_gpio_input(struct gpio_chip *chip, unsigned int offset)
114*4882a593Smuzhiyun {
115*4882a593Smuzhiyun return pinctrl_gpio_direction_input(chip->base + offset);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
axp20x_gpio_get(struct gpio_chip * chip,unsigned int offset)118*4882a593Smuzhiyun static int axp20x_gpio_get(struct gpio_chip *chip, unsigned int offset)
119*4882a593Smuzhiyun {
120*4882a593Smuzhiyun struct axp20x_pctl *pctl = gpiochip_get_data(chip);
121*4882a593Smuzhiyun unsigned int val;
122*4882a593Smuzhiyun int ret;
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun ret = regmap_read(pctl->regmap, AXP20X_GPIO20_SS, &val);
125*4882a593Smuzhiyun if (ret)
126*4882a593Smuzhiyun return ret;
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun return !!(val & BIT(offset + pctl->desc->gpio_status_offset));
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
axp20x_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)131*4882a593Smuzhiyun static int axp20x_gpio_get_direction(struct gpio_chip *chip,
132*4882a593Smuzhiyun unsigned int offset)
133*4882a593Smuzhiyun {
134*4882a593Smuzhiyun struct axp20x_pctl *pctl = gpiochip_get_data(chip);
135*4882a593Smuzhiyun unsigned int val;
136*4882a593Smuzhiyun int reg, ret;
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun reg = axp20x_gpio_get_reg(offset);
139*4882a593Smuzhiyun if (reg < 0)
140*4882a593Smuzhiyun return reg;
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun ret = regmap_read(pctl->regmap, reg, &val);
143*4882a593Smuzhiyun if (ret)
144*4882a593Smuzhiyun return ret;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun /*
147*4882a593Smuzhiyun * This shouldn't really happen if the pin is in use already,
148*4882a593Smuzhiyun * or if it's not in use yet, it doesn't matter since we're
149*4882a593Smuzhiyun * going to change the value soon anyway. Default to output.
150*4882a593Smuzhiyun */
151*4882a593Smuzhiyun if ((val & AXP20X_GPIO_FUNCTIONS) > 2)
152*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_OUT;
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun /*
155*4882a593Smuzhiyun * The GPIO directions are the three lowest values.
156*4882a593Smuzhiyun * 2 is input, 0 and 1 are output
157*4882a593Smuzhiyun */
158*4882a593Smuzhiyun if (val & 2)
159*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_IN;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun return GPIO_LINE_DIRECTION_OUT;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun
axp20x_gpio_output(struct gpio_chip * chip,unsigned int offset,int value)164*4882a593Smuzhiyun static int axp20x_gpio_output(struct gpio_chip *chip, unsigned int offset,
165*4882a593Smuzhiyun int value)
166*4882a593Smuzhiyun {
167*4882a593Smuzhiyun chip->set(chip, offset, value);
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun return 0;
170*4882a593Smuzhiyun }
171*4882a593Smuzhiyun
axp20x_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)172*4882a593Smuzhiyun static void axp20x_gpio_set(struct gpio_chip *chip, unsigned int offset,
173*4882a593Smuzhiyun int value)
174*4882a593Smuzhiyun {
175*4882a593Smuzhiyun struct axp20x_pctl *pctl = gpiochip_get_data(chip);
176*4882a593Smuzhiyun int reg;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun reg = axp20x_gpio_get_reg(offset);
179*4882a593Smuzhiyun if (reg < 0)
180*4882a593Smuzhiyun return;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun regmap_update_bits(pctl->regmap, reg,
183*4882a593Smuzhiyun AXP20X_GPIO_FUNCTIONS,
184*4882a593Smuzhiyun value ? AXP20X_GPIO_FUNCTION_OUT_HIGH :
185*4882a593Smuzhiyun AXP20X_GPIO_FUNCTION_OUT_LOW);
186*4882a593Smuzhiyun }
187*4882a593Smuzhiyun
axp20x_pmx_set(struct pinctrl_dev * pctldev,unsigned int offset,u8 config)188*4882a593Smuzhiyun static int axp20x_pmx_set(struct pinctrl_dev *pctldev, unsigned int offset,
189*4882a593Smuzhiyun u8 config)
190*4882a593Smuzhiyun {
191*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
192*4882a593Smuzhiyun int reg;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun reg = axp20x_gpio_get_reg(offset);
195*4882a593Smuzhiyun if (reg < 0)
196*4882a593Smuzhiyun return reg;
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun return regmap_update_bits(pctl->regmap, reg, AXP20X_GPIO_FUNCTIONS,
199*4882a593Smuzhiyun config);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
axp20x_pmx_func_cnt(struct pinctrl_dev * pctldev)202*4882a593Smuzhiyun static int axp20x_pmx_func_cnt(struct pinctrl_dev *pctldev)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return ARRAY_SIZE(pctl->funcs);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
axp20x_pmx_func_name(struct pinctrl_dev * pctldev,unsigned int selector)209*4882a593Smuzhiyun static const char *axp20x_pmx_func_name(struct pinctrl_dev *pctldev,
210*4882a593Smuzhiyun unsigned int selector)
211*4882a593Smuzhiyun {
212*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun return pctl->funcs[selector].name;
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
axp20x_pmx_func_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * num_groups)217*4882a593Smuzhiyun static int axp20x_pmx_func_groups(struct pinctrl_dev *pctldev,
218*4882a593Smuzhiyun unsigned int selector,
219*4882a593Smuzhiyun const char * const **groups,
220*4882a593Smuzhiyun unsigned int *num_groups)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun *groups = pctl->funcs[selector].groups;
225*4882a593Smuzhiyun *num_groups = pctl->funcs[selector].ngroups;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun return 0;
228*4882a593Smuzhiyun }
229*4882a593Smuzhiyun
axp20x_pmx_set_mux(struct pinctrl_dev * pctldev,unsigned int function,unsigned int group)230*4882a593Smuzhiyun static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
231*4882a593Smuzhiyun unsigned int function, unsigned int group)
232*4882a593Smuzhiyun {
233*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
234*4882a593Smuzhiyun unsigned int mask;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* Every pin supports GPIO_OUT and GPIO_IN functions */
237*4882a593Smuzhiyun if (function <= AXP20X_FUNC_GPIO_IN)
238*4882a593Smuzhiyun return axp20x_pmx_set(pctldev, group,
239*4882a593Smuzhiyun pctl->funcs[function].muxval);
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun if (function == AXP20X_FUNC_LDO)
242*4882a593Smuzhiyun mask = pctl->desc->ldo_mask;
243*4882a593Smuzhiyun else
244*4882a593Smuzhiyun mask = pctl->desc->adc_mask;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (!(BIT(group) & mask))
247*4882a593Smuzhiyun return -EINVAL;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun /*
250*4882a593Smuzhiyun * We let the regulator framework handle the LDO muxing as muxing bits
251*4882a593Smuzhiyun * are basically also regulators on/off bits. It's better not to enforce
252*4882a593Smuzhiyun * any state of the regulator when selecting LDO mux so that we don't
253*4882a593Smuzhiyun * interfere with the regulator driver.
254*4882a593Smuzhiyun */
255*4882a593Smuzhiyun if (function == AXP20X_FUNC_LDO)
256*4882a593Smuzhiyun return 0;
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun return axp20x_pmx_set(pctldev, group, pctl->funcs[function].muxval);
259*4882a593Smuzhiyun }
260*4882a593Smuzhiyun
axp20x_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)261*4882a593Smuzhiyun static int axp20x_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
262*4882a593Smuzhiyun struct pinctrl_gpio_range *range,
263*4882a593Smuzhiyun unsigned int offset, bool input)
264*4882a593Smuzhiyun {
265*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun if (input)
268*4882a593Smuzhiyun return axp20x_pmx_set(pctldev, offset,
269*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval);
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun return axp20x_pmx_set(pctldev, offset,
272*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval);
273*4882a593Smuzhiyun }
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun static const struct pinmux_ops axp20x_pmx_ops = {
276*4882a593Smuzhiyun .get_functions_count = axp20x_pmx_func_cnt,
277*4882a593Smuzhiyun .get_function_name = axp20x_pmx_func_name,
278*4882a593Smuzhiyun .get_function_groups = axp20x_pmx_func_groups,
279*4882a593Smuzhiyun .set_mux = axp20x_pmx_set_mux,
280*4882a593Smuzhiyun .gpio_set_direction = axp20x_pmx_gpio_set_direction,
281*4882a593Smuzhiyun .strict = true,
282*4882a593Smuzhiyun };
283*4882a593Smuzhiyun
axp20x_groups_cnt(struct pinctrl_dev * pctldev)284*4882a593Smuzhiyun static int axp20x_groups_cnt(struct pinctrl_dev *pctldev)
285*4882a593Smuzhiyun {
286*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
287*4882a593Smuzhiyun
288*4882a593Smuzhiyun return pctl->desc->npins;
289*4882a593Smuzhiyun }
290*4882a593Smuzhiyun
axp20x_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)291*4882a593Smuzhiyun static int axp20x_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
292*4882a593Smuzhiyun const unsigned int **pins, unsigned int *num_pins)
293*4882a593Smuzhiyun {
294*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
295*4882a593Smuzhiyun
296*4882a593Smuzhiyun *pins = (unsigned int *)&pctl->desc->pins[selector];
297*4882a593Smuzhiyun *num_pins = 1;
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun return 0;
300*4882a593Smuzhiyun }
301*4882a593Smuzhiyun
axp20x_group_name(struct pinctrl_dev * pctldev,unsigned int selector)302*4882a593Smuzhiyun static const char *axp20x_group_name(struct pinctrl_dev *pctldev,
303*4882a593Smuzhiyun unsigned int selector)
304*4882a593Smuzhiyun {
305*4882a593Smuzhiyun struct axp20x_pctl *pctl = pinctrl_dev_get_drvdata(pctldev);
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun return pctl->desc->pins[selector].name;
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun static const struct pinctrl_ops axp20x_pctrl_ops = {
311*4882a593Smuzhiyun .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
312*4882a593Smuzhiyun .dt_free_map = pinconf_generic_dt_free_map,
313*4882a593Smuzhiyun .get_groups_count = axp20x_groups_cnt,
314*4882a593Smuzhiyun .get_group_name = axp20x_group_name,
315*4882a593Smuzhiyun .get_group_pins = axp20x_group_pins,
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun
axp20x_funcs_groups_from_mask(struct device * dev,unsigned int mask,unsigned int mask_len,struct axp20x_pinctrl_function * func,const struct pinctrl_pin_desc * pins)318*4882a593Smuzhiyun static int axp20x_funcs_groups_from_mask(struct device *dev, unsigned int mask,
319*4882a593Smuzhiyun unsigned int mask_len,
320*4882a593Smuzhiyun struct axp20x_pinctrl_function *func,
321*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun unsigned long int mask_cpy = mask;
324*4882a593Smuzhiyun const char **group;
325*4882a593Smuzhiyun unsigned int ngroups = hweight8(mask);
326*4882a593Smuzhiyun int bit;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun func->ngroups = ngroups;
329*4882a593Smuzhiyun if (func->ngroups > 0) {
330*4882a593Smuzhiyun func->groups = devm_kcalloc(dev,
331*4882a593Smuzhiyun ngroups, sizeof(const char *),
332*4882a593Smuzhiyun GFP_KERNEL);
333*4882a593Smuzhiyun if (!func->groups)
334*4882a593Smuzhiyun return -ENOMEM;
335*4882a593Smuzhiyun group = func->groups;
336*4882a593Smuzhiyun for_each_set_bit(bit, &mask_cpy, mask_len) {
337*4882a593Smuzhiyun *group = pins[bit].name;
338*4882a593Smuzhiyun group++;
339*4882a593Smuzhiyun }
340*4882a593Smuzhiyun }
341*4882a593Smuzhiyun
342*4882a593Smuzhiyun return 0;
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
axp20x_build_funcs_groups(struct platform_device * pdev)345*4882a593Smuzhiyun static int axp20x_build_funcs_groups(struct platform_device *pdev)
346*4882a593Smuzhiyun {
347*4882a593Smuzhiyun struct axp20x_pctl *pctl = platform_get_drvdata(pdev);
348*4882a593Smuzhiyun int i, ret, pin, npins = pctl->desc->npins;
349*4882a593Smuzhiyun
350*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_GPIO_OUT].name = "gpio_out";
351*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_GPIO_OUT].muxval = AXP20X_MUX_GPIO_OUT;
352*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_GPIO_IN].name = "gpio_in";
353*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_GPIO_IN].muxval = AXP20X_MUX_GPIO_IN;
354*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_LDO].name = "ldo";
355*4882a593Smuzhiyun /*
356*4882a593Smuzhiyun * Muxval for LDO is useless as we won't use it.
357*4882a593Smuzhiyun * See comment in axp20x_pmx_set_mux.
358*4882a593Smuzhiyun */
359*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_ADC].name = "adc";
360*4882a593Smuzhiyun pctl->funcs[AXP20X_FUNC_ADC].muxval = pctl->desc->adc_mux;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun /* Every pin supports GPIO_OUT and GPIO_IN functions */
363*4882a593Smuzhiyun for (i = 0; i <= AXP20X_FUNC_GPIO_IN; i++) {
364*4882a593Smuzhiyun pctl->funcs[i].ngroups = npins;
365*4882a593Smuzhiyun pctl->funcs[i].groups = devm_kcalloc(&pdev->dev,
366*4882a593Smuzhiyun npins, sizeof(char *),
367*4882a593Smuzhiyun GFP_KERNEL);
368*4882a593Smuzhiyun if (!pctl->funcs[i].groups)
369*4882a593Smuzhiyun return -ENOMEM;
370*4882a593Smuzhiyun for (pin = 0; pin < npins; pin++)
371*4882a593Smuzhiyun pctl->funcs[i].groups[pin] = pctl->desc->pins[pin].name;
372*4882a593Smuzhiyun }
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->ldo_mask,
375*4882a593Smuzhiyun npins, &pctl->funcs[AXP20X_FUNC_LDO],
376*4882a593Smuzhiyun pctl->desc->pins);
377*4882a593Smuzhiyun if (ret)
378*4882a593Smuzhiyun return ret;
379*4882a593Smuzhiyun
380*4882a593Smuzhiyun ret = axp20x_funcs_groups_from_mask(&pdev->dev, pctl->desc->adc_mask,
381*4882a593Smuzhiyun npins, &pctl->funcs[AXP20X_FUNC_ADC],
382*4882a593Smuzhiyun pctl->desc->pins);
383*4882a593Smuzhiyun if (ret)
384*4882a593Smuzhiyun return ret;
385*4882a593Smuzhiyun
386*4882a593Smuzhiyun return 0;
387*4882a593Smuzhiyun }
388*4882a593Smuzhiyun
389*4882a593Smuzhiyun static const struct of_device_id axp20x_pctl_match[] = {
390*4882a593Smuzhiyun { .compatible = "x-powers,axp209-gpio", .data = &axp20x_data, },
391*4882a593Smuzhiyun { .compatible = "x-powers,axp813-gpio", .data = &axp813_data, },
392*4882a593Smuzhiyun { }
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, axp20x_pctl_match);
395*4882a593Smuzhiyun
axp20x_pctl_probe(struct platform_device * pdev)396*4882a593Smuzhiyun static int axp20x_pctl_probe(struct platform_device *pdev)
397*4882a593Smuzhiyun {
398*4882a593Smuzhiyun struct axp20x_dev *axp20x = dev_get_drvdata(pdev->dev.parent);
399*4882a593Smuzhiyun struct axp20x_pctl *pctl;
400*4882a593Smuzhiyun struct device *dev = &pdev->dev;
401*4882a593Smuzhiyun struct pinctrl_desc *pctrl_desc;
402*4882a593Smuzhiyun int ret;
403*4882a593Smuzhiyun
404*4882a593Smuzhiyun if (!of_device_is_available(pdev->dev.of_node))
405*4882a593Smuzhiyun return -ENODEV;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun if (!axp20x) {
408*4882a593Smuzhiyun dev_err(&pdev->dev, "Parent drvdata not set\n");
409*4882a593Smuzhiyun return -EINVAL;
410*4882a593Smuzhiyun }
411*4882a593Smuzhiyun
412*4882a593Smuzhiyun pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
413*4882a593Smuzhiyun if (!pctl)
414*4882a593Smuzhiyun return -ENOMEM;
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun pctl->chip.base = -1;
417*4882a593Smuzhiyun pctl->chip.can_sleep = true;
418*4882a593Smuzhiyun pctl->chip.request = gpiochip_generic_request;
419*4882a593Smuzhiyun pctl->chip.free = gpiochip_generic_free;
420*4882a593Smuzhiyun pctl->chip.parent = &pdev->dev;
421*4882a593Smuzhiyun pctl->chip.label = dev_name(&pdev->dev);
422*4882a593Smuzhiyun pctl->chip.owner = THIS_MODULE;
423*4882a593Smuzhiyun pctl->chip.get = axp20x_gpio_get;
424*4882a593Smuzhiyun pctl->chip.get_direction = axp20x_gpio_get_direction;
425*4882a593Smuzhiyun pctl->chip.set = axp20x_gpio_set;
426*4882a593Smuzhiyun pctl->chip.direction_input = axp20x_gpio_input;
427*4882a593Smuzhiyun pctl->chip.direction_output = axp20x_gpio_output;
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun pctl->desc = of_device_get_match_data(dev);
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun pctl->chip.ngpio = pctl->desc->npins;
432*4882a593Smuzhiyun
433*4882a593Smuzhiyun pctl->regmap = axp20x->regmap;
434*4882a593Smuzhiyun pctl->dev = &pdev->dev;
435*4882a593Smuzhiyun
436*4882a593Smuzhiyun platform_set_drvdata(pdev, pctl);
437*4882a593Smuzhiyun
438*4882a593Smuzhiyun ret = axp20x_build_funcs_groups(pdev);
439*4882a593Smuzhiyun if (ret) {
440*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to build groups\n");
441*4882a593Smuzhiyun return ret;
442*4882a593Smuzhiyun }
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun pctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*pctrl_desc), GFP_KERNEL);
445*4882a593Smuzhiyun if (!pctrl_desc)
446*4882a593Smuzhiyun return -ENOMEM;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun pctrl_desc->name = dev_name(&pdev->dev);
449*4882a593Smuzhiyun pctrl_desc->owner = THIS_MODULE;
450*4882a593Smuzhiyun pctrl_desc->pins = pctl->desc->pins;
451*4882a593Smuzhiyun pctrl_desc->npins = pctl->desc->npins;
452*4882a593Smuzhiyun pctrl_desc->pctlops = &axp20x_pctrl_ops;
453*4882a593Smuzhiyun pctrl_desc->pmxops = &axp20x_pmx_ops;
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, pctrl_desc, pctl);
456*4882a593Smuzhiyun if (IS_ERR(pctl->pctl_dev)) {
457*4882a593Smuzhiyun dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
458*4882a593Smuzhiyun return PTR_ERR(pctl->pctl_dev);
459*4882a593Smuzhiyun }
460*4882a593Smuzhiyun
461*4882a593Smuzhiyun ret = devm_gpiochip_add_data(&pdev->dev, &pctl->chip, pctl);
462*4882a593Smuzhiyun if (ret) {
463*4882a593Smuzhiyun dev_err(&pdev->dev, "Failed to register GPIO chip\n");
464*4882a593Smuzhiyun return ret;
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
467*4882a593Smuzhiyun ret = gpiochip_add_pin_range(&pctl->chip, dev_name(&pdev->dev),
468*4882a593Smuzhiyun pctl->desc->pins->number,
469*4882a593Smuzhiyun pctl->desc->pins->number,
470*4882a593Smuzhiyun pctl->desc->npins);
471*4882a593Smuzhiyun if (ret) {
472*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to add pin range\n");
473*4882a593Smuzhiyun return ret;
474*4882a593Smuzhiyun }
475*4882a593Smuzhiyun
476*4882a593Smuzhiyun dev_info(&pdev->dev, "AXP209 pinctrl and GPIO driver loaded\n");
477*4882a593Smuzhiyun
478*4882a593Smuzhiyun return 0;
479*4882a593Smuzhiyun }
480*4882a593Smuzhiyun
481*4882a593Smuzhiyun static struct platform_driver axp20x_pctl_driver = {
482*4882a593Smuzhiyun .probe = axp20x_pctl_probe,
483*4882a593Smuzhiyun .driver = {
484*4882a593Smuzhiyun .name = "axp20x-gpio",
485*4882a593Smuzhiyun .of_match_table = axp20x_pctl_match,
486*4882a593Smuzhiyun },
487*4882a593Smuzhiyun };
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun module_platform_driver(axp20x_pctl_driver);
490*4882a593Smuzhiyun
491*4882a593Smuzhiyun MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
492*4882a593Smuzhiyun MODULE_AUTHOR("Quentin Schulz <quentin.schulz@free-electrons.com>");
493*4882a593Smuzhiyun MODULE_DESCRIPTION("AXP20x PMIC pinctrl and GPIO driver");
494*4882a593Smuzhiyun MODULE_LICENSE("GPL");
495