1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef PINCTRL_PINCTRL_NOMADIK_H
3*4882a593Smuzhiyun #define PINCTRL_PINCTRL_NOMADIK_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /* Package definitions */
6*4882a593Smuzhiyun #define PINCTRL_NMK_STN8815 0
7*4882a593Smuzhiyun #define PINCTRL_NMK_DB8500 1
8*4882a593Smuzhiyun #define PINCTRL_NMK_DB8540 2
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /* Alternate functions: function C is set in hw by setting both A and B */
11*4882a593Smuzhiyun #define NMK_GPIO_ALT_GPIO 0
12*4882a593Smuzhiyun #define NMK_GPIO_ALT_A 1
13*4882a593Smuzhiyun #define NMK_GPIO_ALT_B 2
14*4882a593Smuzhiyun #define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define NMK_GPIO_ALT_CX_SHIFT 2
17*4882a593Smuzhiyun #define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
18*4882a593Smuzhiyun #define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
19*4882a593Smuzhiyun #define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
20*4882a593Smuzhiyun #define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define PRCM_GPIOCR_ALTCX(pin_num,\
23*4882a593Smuzhiyun altc1_used, altc1_ri, altc1_cb,\
24*4882a593Smuzhiyun altc2_used, altc2_ri, altc2_cb,\
25*4882a593Smuzhiyun altc3_used, altc3_ri, altc3_cb,\
26*4882a593Smuzhiyun altc4_used, altc4_ri, altc4_cb)\
27*4882a593Smuzhiyun {\
28*4882a593Smuzhiyun .pin = pin_num,\
29*4882a593Smuzhiyun .altcx[PRCM_IDX_GPIOCR_ALTC1] = {\
30*4882a593Smuzhiyun .used = altc1_used,\
31*4882a593Smuzhiyun .reg_index = altc1_ri,\
32*4882a593Smuzhiyun .control_bit = altc1_cb\
33*4882a593Smuzhiyun },\
34*4882a593Smuzhiyun .altcx[PRCM_IDX_GPIOCR_ALTC2] = {\
35*4882a593Smuzhiyun .used = altc2_used,\
36*4882a593Smuzhiyun .reg_index = altc2_ri,\
37*4882a593Smuzhiyun .control_bit = altc2_cb\
38*4882a593Smuzhiyun },\
39*4882a593Smuzhiyun .altcx[PRCM_IDX_GPIOCR_ALTC3] = {\
40*4882a593Smuzhiyun .used = altc3_used,\
41*4882a593Smuzhiyun .reg_index = altc3_ri,\
42*4882a593Smuzhiyun .control_bit = altc3_cb\
43*4882a593Smuzhiyun },\
44*4882a593Smuzhiyun .altcx[PRCM_IDX_GPIOCR_ALTC4] = {\
45*4882a593Smuzhiyun .used = altc4_used,\
46*4882a593Smuzhiyun .reg_index = altc4_ri,\
47*4882a593Smuzhiyun .control_bit = altc4_cb\
48*4882a593Smuzhiyun },\
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun /**
52*4882a593Smuzhiyun * enum prcm_gpiocr_reg_index
53*4882a593Smuzhiyun * Used to reference an PRCM GPIOCR register address.
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun enum prcm_gpiocr_reg_index {
56*4882a593Smuzhiyun PRCM_IDX_GPIOCR1,
57*4882a593Smuzhiyun PRCM_IDX_GPIOCR2,
58*4882a593Smuzhiyun PRCM_IDX_GPIOCR3
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun /**
61*4882a593Smuzhiyun * enum prcm_gpiocr_altcx_index
62*4882a593Smuzhiyun * Used to reference an Other alternate-C function.
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun enum prcm_gpiocr_altcx_index {
65*4882a593Smuzhiyun PRCM_IDX_GPIOCR_ALTC1,
66*4882a593Smuzhiyun PRCM_IDX_GPIOCR_ALTC2,
67*4882a593Smuzhiyun PRCM_IDX_GPIOCR_ALTC3,
68*4882a593Smuzhiyun PRCM_IDX_GPIOCR_ALTC4,
69*4882a593Smuzhiyun PRCM_IDX_GPIOCR_ALTC_MAX,
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun /**
73*4882a593Smuzhiyun * struct prcm_gpio_altcx - Other alternate-C function
74*4882a593Smuzhiyun * @used: other alternate-C function availability
75*4882a593Smuzhiyun * @reg_index: PRCM GPIOCR register index used to control the function
76*4882a593Smuzhiyun * @control_bit: PRCM GPIOCR bit used to control the function
77*4882a593Smuzhiyun */
78*4882a593Smuzhiyun struct prcm_gpiocr_altcx {
79*4882a593Smuzhiyun bool used:1;
80*4882a593Smuzhiyun u8 reg_index:2;
81*4882a593Smuzhiyun u8 control_bit:5;
82*4882a593Smuzhiyun } __packed;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /**
85*4882a593Smuzhiyun * struct prcm_gpio_altcx_pin_desc - Other alternate-C pin
86*4882a593Smuzhiyun * @pin: The pin number
87*4882a593Smuzhiyun * @altcx: array of other alternate-C[1-4] functions
88*4882a593Smuzhiyun */
89*4882a593Smuzhiyun struct prcm_gpiocr_altcx_pin_desc {
90*4882a593Smuzhiyun unsigned short pin;
91*4882a593Smuzhiyun struct prcm_gpiocr_altcx altcx[PRCM_IDX_GPIOCR_ALTC_MAX];
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun /**
95*4882a593Smuzhiyun * struct nmk_function - Nomadik pinctrl mux function
96*4882a593Smuzhiyun * @name: The name of the function, exported to pinctrl core.
97*4882a593Smuzhiyun * @groups: An array of pin groups that may select this function.
98*4882a593Smuzhiyun * @ngroups: The number of entries in @groups.
99*4882a593Smuzhiyun */
100*4882a593Smuzhiyun struct nmk_function {
101*4882a593Smuzhiyun const char *name;
102*4882a593Smuzhiyun const char * const *groups;
103*4882a593Smuzhiyun unsigned ngroups;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun /**
107*4882a593Smuzhiyun * struct nmk_pingroup - describes a Nomadik pin group
108*4882a593Smuzhiyun * @name: the name of this specific pin group
109*4882a593Smuzhiyun * @pins: an array of discrete physical pins used in this group, taken
110*4882a593Smuzhiyun * from the driver-local pin enumeration space
111*4882a593Smuzhiyun * @num_pins: the number of pins in this group array, i.e. the number of
112*4882a593Smuzhiyun * elements in .pins so we can iterate over that array
113*4882a593Smuzhiyun * @altsetting: the altsetting to apply to all pins in this group to
114*4882a593Smuzhiyun * configure them to be used by a function
115*4882a593Smuzhiyun */
116*4882a593Smuzhiyun struct nmk_pingroup {
117*4882a593Smuzhiyun const char *name;
118*4882a593Smuzhiyun const unsigned int *pins;
119*4882a593Smuzhiyun const unsigned npins;
120*4882a593Smuzhiyun int altsetting;
121*4882a593Smuzhiyun };
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun /**
124*4882a593Smuzhiyun * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration
125*4882a593Smuzhiyun * @pins: An array describing all pins the pin controller affects.
126*4882a593Smuzhiyun * All pins which are also GPIOs must be listed first within the
127*4882a593Smuzhiyun * array, and be numbered identically to the GPIO controller's
128*4882a593Smuzhiyun * numbering.
129*4882a593Smuzhiyun * @npins: The number of entries in @pins.
130*4882a593Smuzhiyun * @functions: The functions supported on this SoC.
131*4882a593Smuzhiyun * @nfunction: The number of entries in @functions.
132*4882a593Smuzhiyun * @groups: An array describing all pin groups the pin SoC supports.
133*4882a593Smuzhiyun * @ngroups: The number of entries in @groups.
134*4882a593Smuzhiyun * @altcx_pins: The pins that support Other alternate-C function on this SoC
135*4882a593Smuzhiyun * @npins_altcx: The number of Other alternate-C pins
136*4882a593Smuzhiyun * @prcm_gpiocr_registers: The array of PRCM GPIOCR registers on this SoC
137*4882a593Smuzhiyun */
138*4882a593Smuzhiyun struct nmk_pinctrl_soc_data {
139*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins;
140*4882a593Smuzhiyun unsigned npins;
141*4882a593Smuzhiyun const struct nmk_function *functions;
142*4882a593Smuzhiyun unsigned nfunctions;
143*4882a593Smuzhiyun const struct nmk_pingroup *groups;
144*4882a593Smuzhiyun unsigned ngroups;
145*4882a593Smuzhiyun const struct prcm_gpiocr_altcx_pin_desc *altcx_pins;
146*4882a593Smuzhiyun unsigned npins_altcx;
147*4882a593Smuzhiyun const u16 *prcm_gpiocr_registers;
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun #ifdef CONFIG_PINCTRL_STN8815
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc);
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun #else
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun static inline void
nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data ** soc)157*4882a593Smuzhiyun nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun }
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun #endif
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun #ifdef CONFIG_PINCTRL_DB8500
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun #else
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun static inline void
nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data ** soc)170*4882a593Smuzhiyun nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
174*4882a593Smuzhiyun #endif
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun #ifdef CONFIG_PINCTRL_DB8540
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun #else
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun static inline void
nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data ** soc)183*4882a593Smuzhiyun nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
184*4882a593Smuzhiyun {
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun #endif
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun #endif /* PINCTRL_PINCTRL_NOMADIK_H */
190