1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef PINCTRL_PINCTRL_ABx500_H
3*4882a593Smuzhiyun #define PINCTRL_PINCTRL_ABx500_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /* Package definitions */
6*4882a593Smuzhiyun #define PINCTRL_AB8500 0
7*4882a593Smuzhiyun #define PINCTRL_AB8505 1
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /* pins alternate function */
10*4882a593Smuzhiyun enum abx500_pin_func {
11*4882a593Smuzhiyun ABX500_DEFAULT,
12*4882a593Smuzhiyun ABX500_ALT_A,
13*4882a593Smuzhiyun ABX500_ALT_B,
14*4882a593Smuzhiyun ABX500_ALT_C,
15*4882a593Smuzhiyun };
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun enum abx500_gpio_pull_updown {
18*4882a593Smuzhiyun ABX500_GPIO_PULL_DOWN = 0x0,
19*4882a593Smuzhiyun ABX500_GPIO_PULL_NONE = 0x1,
20*4882a593Smuzhiyun ABX500_GPIO_PULL_UP = 0x3,
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun enum abx500_gpio_vinsel {
24*4882a593Smuzhiyun ABX500_GPIO_VINSEL_VBAT = 0x0,
25*4882a593Smuzhiyun ABX500_GPIO_VINSEL_VIN_1V8 = 0x1,
26*4882a593Smuzhiyun ABX500_GPIO_VINSEL_VDD_BIF = 0x2,
27*4882a593Smuzhiyun };
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /**
30*4882a593Smuzhiyun * struct abx500_function - ABx500 pinctrl mux function
31*4882a593Smuzhiyun * @name: The name of the function, exported to pinctrl core.
32*4882a593Smuzhiyun * @groups: An array of pin groups that may select this function.
33*4882a593Smuzhiyun * @ngroups: The number of entries in @groups.
34*4882a593Smuzhiyun */
35*4882a593Smuzhiyun struct abx500_function {
36*4882a593Smuzhiyun const char *name;
37*4882a593Smuzhiyun const char * const *groups;
38*4882a593Smuzhiyun unsigned ngroups;
39*4882a593Smuzhiyun };
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /**
42*4882a593Smuzhiyun * struct abx500_pingroup - describes a ABx500 pin group
43*4882a593Smuzhiyun * @name: the name of this specific pin group
44*4882a593Smuzhiyun * @pins: an array of discrete physical pins used in this group, taken
45*4882a593Smuzhiyun * from the driver-local pin enumeration space
46*4882a593Smuzhiyun * @num_pins: the number of pins in this group array, i.e. the number of
47*4882a593Smuzhiyun * elements in .pins so we can iterate over that array
48*4882a593Smuzhiyun * @altsetting: the altsetting to apply to all pins in this group to
49*4882a593Smuzhiyun * configure them to be used by a function
50*4882a593Smuzhiyun */
51*4882a593Smuzhiyun struct abx500_pingroup {
52*4882a593Smuzhiyun const char *name;
53*4882a593Smuzhiyun const unsigned int *pins;
54*4882a593Smuzhiyun const unsigned npins;
55*4882a593Smuzhiyun int altsetting;
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun #define ALTERNATE_FUNCTIONS(pin, sel_bit, alt1, alt2, alta, altb, altc) \
59*4882a593Smuzhiyun { \
60*4882a593Smuzhiyun .pin_number = pin, \
61*4882a593Smuzhiyun .gpiosel_bit = sel_bit, \
62*4882a593Smuzhiyun .alt_bit1 = alt1, \
63*4882a593Smuzhiyun .alt_bit2 = alt2, \
64*4882a593Smuzhiyun .alta_val = alta, \
65*4882a593Smuzhiyun .altb_val = altb, \
66*4882a593Smuzhiyun .altc_val = altc, \
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define UNUSED -1
70*4882a593Smuzhiyun /**
71*4882a593Smuzhiyun * struct alternate_functions
72*4882a593Smuzhiyun * @pin_number: The pin number
73*4882a593Smuzhiyun * @gpiosel_bit: Control bit in GPIOSEL register,
74*4882a593Smuzhiyun * @alt_bit1: First AlternateFunction bit used to select the
75*4882a593Smuzhiyun * alternate function
76*4882a593Smuzhiyun * @alt_bit2: Second AlternateFunction bit used to select the
77*4882a593Smuzhiyun * alternate function
78*4882a593Smuzhiyun *
79*4882a593Smuzhiyun * these 3 following fields are necessary due to none
80*4882a593Smuzhiyun * coherency on how to select the altA, altB and altC
81*4882a593Smuzhiyun * function between the ABx500 SOC family when using
82*4882a593Smuzhiyun * alternatfunc register.
83*4882a593Smuzhiyun * @alta_val: value to write in alternatfunc to select altA function
84*4882a593Smuzhiyun * @altb_val: value to write in alternatfunc to select altB function
85*4882a593Smuzhiyun * @altc_val: value to write in alternatfunc to select altC function
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun struct alternate_functions {
88*4882a593Smuzhiyun unsigned pin_number;
89*4882a593Smuzhiyun s8 gpiosel_bit;
90*4882a593Smuzhiyun s8 alt_bit1;
91*4882a593Smuzhiyun s8 alt_bit2;
92*4882a593Smuzhiyun u8 alta_val;
93*4882a593Smuzhiyun u8 altb_val;
94*4882a593Smuzhiyun u8 altc_val;
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun #define GPIO_IRQ_CLUSTER(a, b, c) \
98*4882a593Smuzhiyun { \
99*4882a593Smuzhiyun .start = a, \
100*4882a593Smuzhiyun .end = b, \
101*4882a593Smuzhiyun .to_irq = c, \
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /**
105*4882a593Smuzhiyun * struct abx500_gpio_irq_cluster - indicates GPIOs which are interrupt
106*4882a593Smuzhiyun * capable
107*4882a593Smuzhiyun * @start: The pin number of the first pin interrupt capable
108*4882a593Smuzhiyun * @end: The pin number of the last pin interrupt capable
109*4882a593Smuzhiyun * @to_irq: The ABx500 GPIO's associated IRQs are clustered
110*4882a593Smuzhiyun * together throughout the interrupt numbers at irregular
111*4882a593Smuzhiyun * intervals. To solve this quandary, we will place the
112*4882a593Smuzhiyun * read-in values into the cluster information table
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun struct abx500_gpio_irq_cluster {
116*4882a593Smuzhiyun int start;
117*4882a593Smuzhiyun int end;
118*4882a593Smuzhiyun int to_irq;
119*4882a593Smuzhiyun };
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun /**
122*4882a593Smuzhiyun * struct abx500_pinrange - map pin numbers to GPIO offsets
123*4882a593Smuzhiyun * @offset: offset into the GPIO local numberspace, incidentally
124*4882a593Smuzhiyun * identical to the offset into the local pin numberspace
125*4882a593Smuzhiyun * @npins: number of pins to map from both offsets
126*4882a593Smuzhiyun * @altfunc: altfunc setting to be used to enable GPIO on a pin in
127*4882a593Smuzhiyun * this range (may vary)
128*4882a593Smuzhiyun */
129*4882a593Smuzhiyun struct abx500_pinrange {
130*4882a593Smuzhiyun unsigned int offset;
131*4882a593Smuzhiyun unsigned int npins;
132*4882a593Smuzhiyun int altfunc;
133*4882a593Smuzhiyun };
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun #define ABX500_PINRANGE(a, b, c) { .offset = a, .npins = b, .altfunc = c }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /**
138*4882a593Smuzhiyun * struct abx500_pinctrl_soc_data - ABx500 pin controller per-SoC configuration
139*4882a593Smuzhiyun * @gpio_ranges: An array of GPIO ranges for this SoC
140*4882a593Smuzhiyun * @gpio_num_ranges: The number of GPIO ranges for this SoC
141*4882a593Smuzhiyun * @pins: An array describing all pins the pin controller affects.
142*4882a593Smuzhiyun * All pins which are also GPIOs must be listed first within the
143*4882a593Smuzhiyun * array, and be numbered identically to the GPIO controller's
144*4882a593Smuzhiyun * numbering.
145*4882a593Smuzhiyun * @npins: The number of entries in @pins.
146*4882a593Smuzhiyun * @functions: The functions supported on this SoC.
147*4882a593Smuzhiyun * @nfunction: The number of entries in @functions.
148*4882a593Smuzhiyun * @groups: An array describing all pin groups the pin SoC supports.
149*4882a593Smuzhiyun * @ngroups: The number of entries in @groups.
150*4882a593Smuzhiyun * @alternate_functions: array describing pins which supports alternate and
151*4882a593Smuzhiyun * how to set it.
152*4882a593Smuzhiyun * @gpio_irq_cluster: An array of GPIO interrupt capable for this SoC
153*4882a593Smuzhiyun * @ngpio_irq_cluster: The number of GPIO inetrrupt capable for this SoC
154*4882a593Smuzhiyun * @irq_gpio_rising_offset: Interrupt offset used as base to compute specific
155*4882a593Smuzhiyun * setting strategy of the rising interrupt line
156*4882a593Smuzhiyun * @irq_gpio_falling_offset: Interrupt offset used as base to compute specific
157*4882a593Smuzhiyun * setting strategy of the falling interrupt line
158*4882a593Smuzhiyun * @irq_gpio_factor: Factor used to compute specific setting strategy of
159*4882a593Smuzhiyun * the interrupt line
160*4882a593Smuzhiyun */
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun struct abx500_pinctrl_soc_data {
163*4882a593Smuzhiyun const struct abx500_pinrange *gpio_ranges;
164*4882a593Smuzhiyun unsigned gpio_num_ranges;
165*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins;
166*4882a593Smuzhiyun unsigned npins;
167*4882a593Smuzhiyun const struct abx500_function *functions;
168*4882a593Smuzhiyun unsigned nfunctions;
169*4882a593Smuzhiyun const struct abx500_pingroup *groups;
170*4882a593Smuzhiyun unsigned ngroups;
171*4882a593Smuzhiyun struct alternate_functions *alternate_functions;
172*4882a593Smuzhiyun struct abx500_gpio_irq_cluster *gpio_irq_cluster;
173*4882a593Smuzhiyun unsigned ngpio_irq_cluster;
174*4882a593Smuzhiyun int irq_gpio_rising_offset;
175*4882a593Smuzhiyun int irq_gpio_falling_offset;
176*4882a593Smuzhiyun int irq_gpio_factor;
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun #ifdef CONFIG_PINCTRL_AB8500
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun void abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc);
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun #else
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun static inline void
abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data ** soc)186*4882a593Smuzhiyun abx500_pinctrl_ab8500_init(struct abx500_pinctrl_soc_data **soc)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun }
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun #endif
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun #ifdef CONFIG_PINCTRL_AB8505
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun void abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc);
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun #else
197*4882a593Smuzhiyun
198*4882a593Smuzhiyun static inline void
abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data ** soc)199*4882a593Smuzhiyun abx500_pinctrl_ab8505_init(struct abx500_pinctrl_soc_data **soc)
200*4882a593Smuzhiyun {
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun #endif
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun #endif /* PINCTRL_PINCTRL_ABx500_H */
206