1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Pin controller and GPIO driver for Amlogic Meson8 and Meson8m2. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <dt-bindings/gpio/meson8-gpio.h> 9*4882a593Smuzhiyun #include "pinctrl-meson.h" 10*4882a593Smuzhiyun #include "pinctrl-meson8-pmx.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun static const struct pinctrl_pin_desc meson8_cbus_pins[] = { 13*4882a593Smuzhiyun MESON_PIN(GPIOX_0), 14*4882a593Smuzhiyun MESON_PIN(GPIOX_1), 15*4882a593Smuzhiyun MESON_PIN(GPIOX_2), 16*4882a593Smuzhiyun MESON_PIN(GPIOX_3), 17*4882a593Smuzhiyun MESON_PIN(GPIOX_4), 18*4882a593Smuzhiyun MESON_PIN(GPIOX_5), 19*4882a593Smuzhiyun MESON_PIN(GPIOX_6), 20*4882a593Smuzhiyun MESON_PIN(GPIOX_7), 21*4882a593Smuzhiyun MESON_PIN(GPIOX_8), 22*4882a593Smuzhiyun MESON_PIN(GPIOX_9), 23*4882a593Smuzhiyun MESON_PIN(GPIOX_10), 24*4882a593Smuzhiyun MESON_PIN(GPIOX_11), 25*4882a593Smuzhiyun MESON_PIN(GPIOX_12), 26*4882a593Smuzhiyun MESON_PIN(GPIOX_13), 27*4882a593Smuzhiyun MESON_PIN(GPIOX_14), 28*4882a593Smuzhiyun MESON_PIN(GPIOX_15), 29*4882a593Smuzhiyun MESON_PIN(GPIOX_16), 30*4882a593Smuzhiyun MESON_PIN(GPIOX_17), 31*4882a593Smuzhiyun MESON_PIN(GPIOX_18), 32*4882a593Smuzhiyun MESON_PIN(GPIOX_19), 33*4882a593Smuzhiyun MESON_PIN(GPIOX_20), 34*4882a593Smuzhiyun MESON_PIN(GPIOX_21), 35*4882a593Smuzhiyun MESON_PIN(GPIOY_0), 36*4882a593Smuzhiyun MESON_PIN(GPIOY_1), 37*4882a593Smuzhiyun MESON_PIN(GPIOY_2), 38*4882a593Smuzhiyun MESON_PIN(GPIOY_3), 39*4882a593Smuzhiyun MESON_PIN(GPIOY_4), 40*4882a593Smuzhiyun MESON_PIN(GPIOY_5), 41*4882a593Smuzhiyun MESON_PIN(GPIOY_6), 42*4882a593Smuzhiyun MESON_PIN(GPIOY_7), 43*4882a593Smuzhiyun MESON_PIN(GPIOY_8), 44*4882a593Smuzhiyun MESON_PIN(GPIOY_9), 45*4882a593Smuzhiyun MESON_PIN(GPIOY_10), 46*4882a593Smuzhiyun MESON_PIN(GPIOY_11), 47*4882a593Smuzhiyun MESON_PIN(GPIOY_12), 48*4882a593Smuzhiyun MESON_PIN(GPIOY_13), 49*4882a593Smuzhiyun MESON_PIN(GPIOY_14), 50*4882a593Smuzhiyun MESON_PIN(GPIOY_15), 51*4882a593Smuzhiyun MESON_PIN(GPIOY_16), 52*4882a593Smuzhiyun MESON_PIN(GPIODV_0), 53*4882a593Smuzhiyun MESON_PIN(GPIODV_1), 54*4882a593Smuzhiyun MESON_PIN(GPIODV_2), 55*4882a593Smuzhiyun MESON_PIN(GPIODV_3), 56*4882a593Smuzhiyun MESON_PIN(GPIODV_4), 57*4882a593Smuzhiyun MESON_PIN(GPIODV_5), 58*4882a593Smuzhiyun MESON_PIN(GPIODV_6), 59*4882a593Smuzhiyun MESON_PIN(GPIODV_7), 60*4882a593Smuzhiyun MESON_PIN(GPIODV_8), 61*4882a593Smuzhiyun MESON_PIN(GPIODV_9), 62*4882a593Smuzhiyun MESON_PIN(GPIODV_10), 63*4882a593Smuzhiyun MESON_PIN(GPIODV_11), 64*4882a593Smuzhiyun MESON_PIN(GPIODV_12), 65*4882a593Smuzhiyun MESON_PIN(GPIODV_13), 66*4882a593Smuzhiyun MESON_PIN(GPIODV_14), 67*4882a593Smuzhiyun MESON_PIN(GPIODV_15), 68*4882a593Smuzhiyun MESON_PIN(GPIODV_16), 69*4882a593Smuzhiyun MESON_PIN(GPIODV_17), 70*4882a593Smuzhiyun MESON_PIN(GPIODV_18), 71*4882a593Smuzhiyun MESON_PIN(GPIODV_19), 72*4882a593Smuzhiyun MESON_PIN(GPIODV_20), 73*4882a593Smuzhiyun MESON_PIN(GPIODV_21), 74*4882a593Smuzhiyun MESON_PIN(GPIODV_22), 75*4882a593Smuzhiyun MESON_PIN(GPIODV_23), 76*4882a593Smuzhiyun MESON_PIN(GPIODV_24), 77*4882a593Smuzhiyun MESON_PIN(GPIODV_25), 78*4882a593Smuzhiyun MESON_PIN(GPIODV_26), 79*4882a593Smuzhiyun MESON_PIN(GPIODV_27), 80*4882a593Smuzhiyun MESON_PIN(GPIODV_28), 81*4882a593Smuzhiyun MESON_PIN(GPIODV_29), 82*4882a593Smuzhiyun MESON_PIN(GPIOH_0), 83*4882a593Smuzhiyun MESON_PIN(GPIOH_1), 84*4882a593Smuzhiyun MESON_PIN(GPIOH_2), 85*4882a593Smuzhiyun MESON_PIN(GPIOH_3), 86*4882a593Smuzhiyun MESON_PIN(GPIOH_4), 87*4882a593Smuzhiyun MESON_PIN(GPIOH_5), 88*4882a593Smuzhiyun MESON_PIN(GPIOH_6), 89*4882a593Smuzhiyun MESON_PIN(GPIOH_7), 90*4882a593Smuzhiyun MESON_PIN(GPIOH_8), 91*4882a593Smuzhiyun MESON_PIN(GPIOH_9), 92*4882a593Smuzhiyun MESON_PIN(GPIOZ_0), 93*4882a593Smuzhiyun MESON_PIN(GPIOZ_1), 94*4882a593Smuzhiyun MESON_PIN(GPIOZ_2), 95*4882a593Smuzhiyun MESON_PIN(GPIOZ_3), 96*4882a593Smuzhiyun MESON_PIN(GPIOZ_4), 97*4882a593Smuzhiyun MESON_PIN(GPIOZ_5), 98*4882a593Smuzhiyun MESON_PIN(GPIOZ_6), 99*4882a593Smuzhiyun MESON_PIN(GPIOZ_7), 100*4882a593Smuzhiyun MESON_PIN(GPIOZ_8), 101*4882a593Smuzhiyun MESON_PIN(GPIOZ_9), 102*4882a593Smuzhiyun MESON_PIN(GPIOZ_10), 103*4882a593Smuzhiyun MESON_PIN(GPIOZ_11), 104*4882a593Smuzhiyun MESON_PIN(GPIOZ_12), 105*4882a593Smuzhiyun MESON_PIN(GPIOZ_13), 106*4882a593Smuzhiyun MESON_PIN(GPIOZ_14), 107*4882a593Smuzhiyun MESON_PIN(CARD_0), 108*4882a593Smuzhiyun MESON_PIN(CARD_1), 109*4882a593Smuzhiyun MESON_PIN(CARD_2), 110*4882a593Smuzhiyun MESON_PIN(CARD_3), 111*4882a593Smuzhiyun MESON_PIN(CARD_4), 112*4882a593Smuzhiyun MESON_PIN(CARD_5), 113*4882a593Smuzhiyun MESON_PIN(CARD_6), 114*4882a593Smuzhiyun MESON_PIN(BOOT_0), 115*4882a593Smuzhiyun MESON_PIN(BOOT_1), 116*4882a593Smuzhiyun MESON_PIN(BOOT_2), 117*4882a593Smuzhiyun MESON_PIN(BOOT_3), 118*4882a593Smuzhiyun MESON_PIN(BOOT_4), 119*4882a593Smuzhiyun MESON_PIN(BOOT_5), 120*4882a593Smuzhiyun MESON_PIN(BOOT_6), 121*4882a593Smuzhiyun MESON_PIN(BOOT_7), 122*4882a593Smuzhiyun MESON_PIN(BOOT_8), 123*4882a593Smuzhiyun MESON_PIN(BOOT_9), 124*4882a593Smuzhiyun MESON_PIN(BOOT_10), 125*4882a593Smuzhiyun MESON_PIN(BOOT_11), 126*4882a593Smuzhiyun MESON_PIN(BOOT_12), 127*4882a593Smuzhiyun MESON_PIN(BOOT_13), 128*4882a593Smuzhiyun MESON_PIN(BOOT_14), 129*4882a593Smuzhiyun MESON_PIN(BOOT_15), 130*4882a593Smuzhiyun MESON_PIN(BOOT_16), 131*4882a593Smuzhiyun MESON_PIN(BOOT_17), 132*4882a593Smuzhiyun MESON_PIN(BOOT_18), 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun static const struct pinctrl_pin_desc meson8_aobus_pins[] = { 136*4882a593Smuzhiyun MESON_PIN(GPIOAO_0), 137*4882a593Smuzhiyun MESON_PIN(GPIOAO_1), 138*4882a593Smuzhiyun MESON_PIN(GPIOAO_2), 139*4882a593Smuzhiyun MESON_PIN(GPIOAO_3), 140*4882a593Smuzhiyun MESON_PIN(GPIOAO_4), 141*4882a593Smuzhiyun MESON_PIN(GPIOAO_5), 142*4882a593Smuzhiyun MESON_PIN(GPIOAO_6), 143*4882a593Smuzhiyun MESON_PIN(GPIOAO_7), 144*4882a593Smuzhiyun MESON_PIN(GPIOAO_8), 145*4882a593Smuzhiyun MESON_PIN(GPIOAO_9), 146*4882a593Smuzhiyun MESON_PIN(GPIOAO_10), 147*4882a593Smuzhiyun MESON_PIN(GPIOAO_11), 148*4882a593Smuzhiyun MESON_PIN(GPIOAO_12), 149*4882a593Smuzhiyun MESON_PIN(GPIOAO_13), 150*4882a593Smuzhiyun MESON_PIN(GPIO_BSD_EN), 151*4882a593Smuzhiyun MESON_PIN(GPIO_TEST_N), 152*4882a593Smuzhiyun }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun /* bank X */ 155*4882a593Smuzhiyun static const unsigned int sd_d0_a_pins[] = { GPIOX_0 }; 156*4882a593Smuzhiyun static const unsigned int sd_d1_a_pins[] = { GPIOX_1 }; 157*4882a593Smuzhiyun static const unsigned int sd_d2_a_pins[] = { GPIOX_2 }; 158*4882a593Smuzhiyun static const unsigned int sd_d3_a_pins[] = { GPIOX_3 }; 159*4882a593Smuzhiyun static const unsigned int sd_clk_a_pins[] = { GPIOX_8 }; 160*4882a593Smuzhiyun static const unsigned int sd_cmd_a_pins[] = { GPIOX_9 }; 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun static const unsigned int sdxc_d0_a_pins[] = { GPIOX_0 }; 163*4882a593Smuzhiyun static const unsigned int sdxc_d13_a_pins[] = { GPIOX_1, GPIOX_2, GPIOX_3 }; 164*4882a593Smuzhiyun static const unsigned int sdxc_d47_a_pins[] = { GPIOX_4, GPIOX_5, GPIOX_6, 165*4882a593Smuzhiyun GPIOX_7 }; 166*4882a593Smuzhiyun static const unsigned int sdxc_clk_a_pins[] = { GPIOX_8 }; 167*4882a593Smuzhiyun static const unsigned int sdxc_cmd_a_pins[] = { GPIOX_9 }; 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun static const unsigned int pcm_out_a_pins[] = { GPIOX_4 }; 170*4882a593Smuzhiyun static const unsigned int pcm_in_a_pins[] = { GPIOX_5 }; 171*4882a593Smuzhiyun static const unsigned int pcm_fs_a_pins[] = { GPIOX_6 }; 172*4882a593Smuzhiyun static const unsigned int pcm_clk_a_pins[] = { GPIOX_7 }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun static const unsigned int uart_tx_a0_pins[] = { GPIOX_4 }; 175*4882a593Smuzhiyun static const unsigned int uart_rx_a0_pins[] = { GPIOX_5 }; 176*4882a593Smuzhiyun static const unsigned int uart_cts_a0_pins[] = { GPIOX_6 }; 177*4882a593Smuzhiyun static const unsigned int uart_rts_a0_pins[] = { GPIOX_7 }; 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun static const unsigned int uart_tx_a1_pins[] = { GPIOX_12 }; 180*4882a593Smuzhiyun static const unsigned int uart_rx_a1_pins[] = { GPIOX_13 }; 181*4882a593Smuzhiyun static const unsigned int uart_cts_a1_pins[] = { GPIOX_14 }; 182*4882a593Smuzhiyun static const unsigned int uart_rts_a1_pins[] = { GPIOX_15 }; 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun static const unsigned int uart_tx_b0_pins[] = { GPIOX_16 }; 185*4882a593Smuzhiyun static const unsigned int uart_rx_b0_pins[] = { GPIOX_17 }; 186*4882a593Smuzhiyun static const unsigned int uart_cts_b0_pins[] = { GPIOX_18 }; 187*4882a593Smuzhiyun static const unsigned int uart_rts_b0_pins[] = { GPIOX_19 }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun static const unsigned int iso7816_det_pins[] = { GPIOX_16 }; 190*4882a593Smuzhiyun static const unsigned int iso7816_reset_pins[] = { GPIOX_17 }; 191*4882a593Smuzhiyun static const unsigned int iso7816_clk_pins[] = { GPIOX_18 }; 192*4882a593Smuzhiyun static const unsigned int iso7816_data_pins[] = { GPIOX_19 }; 193*4882a593Smuzhiyun 194*4882a593Smuzhiyun static const unsigned int i2c_sda_d0_pins[] = { GPIOX_16 }; 195*4882a593Smuzhiyun static const unsigned int i2c_sck_d0_pins[] = { GPIOX_17 }; 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun static const unsigned int xtal_32k_out_pins[] = { GPIOX_10 }; 198*4882a593Smuzhiyun static const unsigned int xtal_24m_out_pins[] = { GPIOX_11 }; 199*4882a593Smuzhiyun 200*4882a593Smuzhiyun static const unsigned int pwm_e_pins[] = { GPIOX_10 }; 201*4882a593Smuzhiyun static const unsigned int pwm_b_x_pins[] = { GPIOX_11 }; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* bank Y */ 204*4882a593Smuzhiyun static const unsigned int uart_tx_c_pins[] = { GPIOY_0 }; 205*4882a593Smuzhiyun static const unsigned int uart_rx_c_pins[] = { GPIOY_1 }; 206*4882a593Smuzhiyun static const unsigned int uart_cts_c_pins[] = { GPIOY_2 }; 207*4882a593Smuzhiyun static const unsigned int uart_rts_c_pins[] = { GPIOY_3 }; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun static const unsigned int pcm_out_b_pins[] = { GPIOY_4 }; 210*4882a593Smuzhiyun static const unsigned int pcm_in_b_pins[] = { GPIOY_5 }; 211*4882a593Smuzhiyun static const unsigned int pcm_fs_b_pins[] = { GPIOY_6 }; 212*4882a593Smuzhiyun static const unsigned int pcm_clk_b_pins[] = { GPIOY_7 }; 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun static const unsigned int i2c_sda_c0_pins[] = { GPIOY_0 }; 215*4882a593Smuzhiyun static const unsigned int i2c_sck_c0_pins[] = { GPIOY_1 }; 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun static const unsigned int pwm_a_y_pins[] = { GPIOY_16 }; 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun static const unsigned int i2s_out_ch45_pins[] = { GPIOY_0 }; 220*4882a593Smuzhiyun static const unsigned int i2s_out_ch23_pins[] = { GPIOY_1 }; 221*4882a593Smuzhiyun static const unsigned int i2s_out_ch01_pins[] = { GPIOY_4 }; 222*4882a593Smuzhiyun static const unsigned int i2s_in_ch01_pins[] = { GPIOY_5 }; 223*4882a593Smuzhiyun static const unsigned int i2s_lr_clk_in_pins[] = { GPIOY_6 }; 224*4882a593Smuzhiyun static const unsigned int i2s_ao_clk_in_pins[] = { GPIOY_7 }; 225*4882a593Smuzhiyun static const unsigned int i2s_am_clk_pins[] = { GPIOY_8 }; 226*4882a593Smuzhiyun static const unsigned int i2s_out_ch78_pins[] = { GPIOY_9 }; 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun static const unsigned int spdif_in_pins[] = { GPIOY_2 }; 229*4882a593Smuzhiyun static const unsigned int spdif_out_pins[] = { GPIOY_3 }; 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* bank DV */ 232*4882a593Smuzhiyun static const unsigned int dvin_rgb_pins[] = { 233*4882a593Smuzhiyun GPIODV_0, GPIODV_1, GPIODV_2, GPIODV_3, GPIODV_4, GPIODV_5, 234*4882a593Smuzhiyun GPIODV_6, GPIODV_7, GPIODV_8, GPIODV_9, GPIODV_10, GPIODV_11, 235*4882a593Smuzhiyun GPIODV_12, GPIODV_13, GPIODV_14, GPIODV_15, GPIODV_16, GPIODV_17, 236*4882a593Smuzhiyun GPIODV_18, GPIODV_19, GPIODV_20, GPIODV_21, GPIODV_22, GPIODV_23 237*4882a593Smuzhiyun }; 238*4882a593Smuzhiyun static const unsigned int dvin_vs_pins[] = { GPIODV_24 }; 239*4882a593Smuzhiyun static const unsigned int dvin_hs_pins[] = { GPIODV_25 }; 240*4882a593Smuzhiyun static const unsigned int dvin_clk_pins[] = { GPIODV_26 }; 241*4882a593Smuzhiyun static const unsigned int dvin_de_pins[] = { GPIODV_27 }; 242*4882a593Smuzhiyun 243*4882a593Smuzhiyun static const unsigned int enc_0_pins[] = { GPIODV_0 }; 244*4882a593Smuzhiyun static const unsigned int enc_1_pins[] = { GPIODV_1 }; 245*4882a593Smuzhiyun static const unsigned int enc_2_pins[] = { GPIODV_2 }; 246*4882a593Smuzhiyun static const unsigned int enc_3_pins[] = { GPIODV_3 }; 247*4882a593Smuzhiyun static const unsigned int enc_4_pins[] = { GPIODV_4 }; 248*4882a593Smuzhiyun static const unsigned int enc_5_pins[] = { GPIODV_5 }; 249*4882a593Smuzhiyun static const unsigned int enc_6_pins[] = { GPIODV_6 }; 250*4882a593Smuzhiyun static const unsigned int enc_7_pins[] = { GPIODV_7 }; 251*4882a593Smuzhiyun static const unsigned int enc_8_pins[] = { GPIODV_8 }; 252*4882a593Smuzhiyun static const unsigned int enc_9_pins[] = { GPIODV_9 }; 253*4882a593Smuzhiyun static const unsigned int enc_10_pins[] = { GPIODV_10 }; 254*4882a593Smuzhiyun static const unsigned int enc_11_pins[] = { GPIODV_11 }; 255*4882a593Smuzhiyun static const unsigned int enc_12_pins[] = { GPIODV_12 }; 256*4882a593Smuzhiyun static const unsigned int enc_13_pins[] = { GPIODV_13 }; 257*4882a593Smuzhiyun static const unsigned int enc_14_pins[] = { GPIODV_14 }; 258*4882a593Smuzhiyun static const unsigned int enc_15_pins[] = { GPIODV_15 }; 259*4882a593Smuzhiyun static const unsigned int enc_16_pins[] = { GPIODV_16 }; 260*4882a593Smuzhiyun static const unsigned int enc_17_pins[] = { GPIODV_17 }; 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun static const unsigned int uart_tx_b1_pins[] = { GPIODV_24 }; 263*4882a593Smuzhiyun static const unsigned int uart_rx_b1_pins[] = { GPIODV_25 }; 264*4882a593Smuzhiyun static const unsigned int uart_cts_b1_pins[] = { GPIODV_26 }; 265*4882a593Smuzhiyun static const unsigned int uart_rts_b1_pins[] = { GPIODV_27 }; 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun static const unsigned int vga_vs_pins[] = { GPIODV_24 }; 268*4882a593Smuzhiyun static const unsigned int vga_hs_pins[] = { GPIODV_25 }; 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun static const unsigned int pwm_c_dv9_pins[] = { GPIODV_9 }; 271*4882a593Smuzhiyun static const unsigned int pwm_c_dv29_pins[] = { GPIODV_29 }; 272*4882a593Smuzhiyun static const unsigned int pwm_d_pins[] = { GPIODV_28 }; 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun /* bank H */ 275*4882a593Smuzhiyun static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; 276*4882a593Smuzhiyun static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; 277*4882a593Smuzhiyun static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; 278*4882a593Smuzhiyun static const unsigned int hdmi_cec_pins[] = { GPIOH_3 }; 279*4882a593Smuzhiyun 280*4882a593Smuzhiyun static const unsigned int spi_ss0_0_pins[] = { GPIOH_3 }; 281*4882a593Smuzhiyun static const unsigned int spi_miso_0_pins[] = { GPIOH_4 }; 282*4882a593Smuzhiyun static const unsigned int spi_mosi_0_pins[] = { GPIOH_5 }; 283*4882a593Smuzhiyun static const unsigned int spi_sclk_0_pins[] = { GPIOH_6 }; 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun static const unsigned int i2c_sda_d1_pins[] = { GPIOH_7 }; 286*4882a593Smuzhiyun static const unsigned int i2c_sck_d1_pins[] = { GPIOH_8 }; 287*4882a593Smuzhiyun 288*4882a593Smuzhiyun /* bank Z */ 289*4882a593Smuzhiyun static const unsigned int spi_ss0_1_pins[] = { GPIOZ_9 }; 290*4882a593Smuzhiyun static const unsigned int spi_ss1_1_pins[] = { GPIOZ_10 }; 291*4882a593Smuzhiyun static const unsigned int spi_sclk_1_pins[] = { GPIOZ_11 }; 292*4882a593Smuzhiyun static const unsigned int spi_mosi_1_pins[] = { GPIOZ_12 }; 293*4882a593Smuzhiyun static const unsigned int spi_miso_1_pins[] = { GPIOZ_13 }; 294*4882a593Smuzhiyun static const unsigned int spi_ss2_1_pins[] = { GPIOZ_14 }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun static const unsigned int eth_txd3_pins[] = { GPIOZ_0 }; 297*4882a593Smuzhiyun static const unsigned int eth_txd2_pins[] = { GPIOZ_1 }; 298*4882a593Smuzhiyun static const unsigned int eth_rxd3_pins[] = { GPIOZ_2 }; 299*4882a593Smuzhiyun static const unsigned int eth_rxd2_pins[] = { GPIOZ_3 }; 300*4882a593Smuzhiyun static const unsigned int eth_tx_clk_50m_pins[] = { GPIOZ_4 }; 301*4882a593Smuzhiyun static const unsigned int eth_tx_en_pins[] = { GPIOZ_5 }; 302*4882a593Smuzhiyun static const unsigned int eth_txd1_pins[] = { GPIOZ_6 }; 303*4882a593Smuzhiyun static const unsigned int eth_txd0_pins[] = { GPIOZ_7 }; 304*4882a593Smuzhiyun static const unsigned int eth_rx_clk_in_pins[] = { GPIOZ_8 }; 305*4882a593Smuzhiyun static const unsigned int eth_rx_dv_pins[] = { GPIOZ_9 }; 306*4882a593Smuzhiyun static const unsigned int eth_rxd1_pins[] = { GPIOZ_10 }; 307*4882a593Smuzhiyun static const unsigned int eth_rxd0_pins[] = { GPIOZ_11 }; 308*4882a593Smuzhiyun static const unsigned int eth_mdio_pins[] = { GPIOZ_12 }; 309*4882a593Smuzhiyun static const unsigned int eth_mdc_pins[] = { GPIOZ_13 }; 310*4882a593Smuzhiyun 311*4882a593Smuzhiyun static const unsigned int i2c_sda_a0_pins[] = { GPIOZ_0 }; 312*4882a593Smuzhiyun static const unsigned int i2c_sck_a0_pins[] = { GPIOZ_1 }; 313*4882a593Smuzhiyun 314*4882a593Smuzhiyun static const unsigned int i2c_sda_b_pins[] = { GPIOZ_2 }; 315*4882a593Smuzhiyun static const unsigned int i2c_sck_b_pins[] = { GPIOZ_3 }; 316*4882a593Smuzhiyun 317*4882a593Smuzhiyun static const unsigned int i2c_sda_c1_pins[] = { GPIOZ_4 }; 318*4882a593Smuzhiyun static const unsigned int i2c_sck_c1_pins[] = { GPIOZ_5 }; 319*4882a593Smuzhiyun 320*4882a593Smuzhiyun static const unsigned int i2c_sda_a1_pins[] = { GPIOZ_0 }; 321*4882a593Smuzhiyun static const unsigned int i2c_sck_a1_pins[] = { GPIOZ_1 }; 322*4882a593Smuzhiyun 323*4882a593Smuzhiyun static const unsigned int i2c_sda_a2_pins[] = { GPIOZ_0 }; 324*4882a593Smuzhiyun static const unsigned int i2c_sck_a2_pins[] = { GPIOZ_1 }; 325*4882a593Smuzhiyun 326*4882a593Smuzhiyun static const unsigned int pwm_a_z0_pins[] = { GPIOZ_0 }; 327*4882a593Smuzhiyun static const unsigned int pwm_a_z7_pins[] = { GPIOZ_7 }; 328*4882a593Smuzhiyun static const unsigned int pwm_b_z_pins[] = { GPIOZ_1 }; 329*4882a593Smuzhiyun static const unsigned int pwm_c_z_pins[] = { GPIOZ_8 }; 330*4882a593Smuzhiyun 331*4882a593Smuzhiyun /* bank BOOT */ 332*4882a593Smuzhiyun static const unsigned int sd_d0_c_pins[] = { BOOT_0 }; 333*4882a593Smuzhiyun static const unsigned int sd_d1_c_pins[] = { BOOT_1 }; 334*4882a593Smuzhiyun static const unsigned int sd_d2_c_pins[] = { BOOT_2 }; 335*4882a593Smuzhiyun static const unsigned int sd_d3_c_pins[] = { BOOT_3 }; 336*4882a593Smuzhiyun static const unsigned int sd_cmd_c_pins[] = { BOOT_16 }; 337*4882a593Smuzhiyun static const unsigned int sd_clk_c_pins[] = { BOOT_17 }; 338*4882a593Smuzhiyun 339*4882a593Smuzhiyun static const unsigned int sdxc_d0_c_pins[] = { BOOT_0}; 340*4882a593Smuzhiyun static const unsigned int sdxc_d13_c_pins[] = { BOOT_1, BOOT_2, BOOT_3 }; 341*4882a593Smuzhiyun static const unsigned int sdxc_d47_c_pins[] = { BOOT_4, BOOT_5, BOOT_6, 342*4882a593Smuzhiyun BOOT_7 }; 343*4882a593Smuzhiyun static const unsigned int sdxc_cmd_c_pins[] = { BOOT_16 }; 344*4882a593Smuzhiyun static const unsigned int sdxc_clk_c_pins[] = { BOOT_17 }; 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun static const unsigned int nand_io_pins[] = { 347*4882a593Smuzhiyun BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7 348*4882a593Smuzhiyun }; 349*4882a593Smuzhiyun static const unsigned int nand_io_ce0_pins[] = { BOOT_8 }; 350*4882a593Smuzhiyun static const unsigned int nand_io_ce1_pins[] = { BOOT_9 }; 351*4882a593Smuzhiyun static const unsigned int nand_io_rb0_pins[] = { BOOT_10 }; 352*4882a593Smuzhiyun static const unsigned int nand_ale_pins[] = { BOOT_11 }; 353*4882a593Smuzhiyun static const unsigned int nand_cle_pins[] = { BOOT_12 }; 354*4882a593Smuzhiyun static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; 355*4882a593Smuzhiyun static const unsigned int nand_ren_clk_pins[] = { BOOT_14 }; 356*4882a593Smuzhiyun static const unsigned int nand_dqs_pins[] = { BOOT_15 }; 357*4882a593Smuzhiyun static const unsigned int nand_ce2_pins[] = { BOOT_16 }; 358*4882a593Smuzhiyun static const unsigned int nand_ce3_pins[] = { BOOT_17 }; 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun static const unsigned int nor_d_pins[] = { BOOT_11 }; 361*4882a593Smuzhiyun static const unsigned int nor_q_pins[] = { BOOT_12 }; 362*4882a593Smuzhiyun static const unsigned int nor_c_pins[] = { BOOT_13 }; 363*4882a593Smuzhiyun static const unsigned int nor_cs_pins[] = { BOOT_18 }; 364*4882a593Smuzhiyun 365*4882a593Smuzhiyun /* bank CARD */ 366*4882a593Smuzhiyun static const unsigned int sd_d1_b_pins[] = { CARD_0 }; 367*4882a593Smuzhiyun static const unsigned int sd_d0_b_pins[] = { CARD_1 }; 368*4882a593Smuzhiyun static const unsigned int sd_clk_b_pins[] = { CARD_2 }; 369*4882a593Smuzhiyun static const unsigned int sd_cmd_b_pins[] = { CARD_3 }; 370*4882a593Smuzhiyun static const unsigned int sd_d3_b_pins[] = { CARD_4 }; 371*4882a593Smuzhiyun static const unsigned int sd_d2_b_pins[] = { CARD_5 }; 372*4882a593Smuzhiyun 373*4882a593Smuzhiyun static const unsigned int sdxc_d13_b_pins[] = { CARD_0, CARD_4, CARD_5 }; 374*4882a593Smuzhiyun static const unsigned int sdxc_d0_b_pins[] = { CARD_1 }; 375*4882a593Smuzhiyun static const unsigned int sdxc_clk_b_pins[] = { CARD_2 }; 376*4882a593Smuzhiyun static const unsigned int sdxc_cmd_b_pins[] = { CARD_3 }; 377*4882a593Smuzhiyun 378*4882a593Smuzhiyun /* bank AO */ 379*4882a593Smuzhiyun static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; 380*4882a593Smuzhiyun static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; 381*4882a593Smuzhiyun static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; 382*4882a593Smuzhiyun static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; 383*4882a593Smuzhiyun 384*4882a593Smuzhiyun static const unsigned int remote_input_pins[] = { GPIOAO_7 }; 385*4882a593Smuzhiyun static const unsigned int remote_output_ao_pins[] = { GPIOAO_13 }; 386*4882a593Smuzhiyun 387*4882a593Smuzhiyun static const unsigned int i2c_slave_sck_ao_pins[] = { GPIOAO_4 }; 388*4882a593Smuzhiyun static const unsigned int i2c_slave_sda_ao_pins[] = { GPIOAO_5 }; 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun static const unsigned int uart_tx_ao_b0_pins[] = { GPIOAO_0 }; 391*4882a593Smuzhiyun static const unsigned int uart_rx_ao_b0_pins[] = { GPIOAO_1 }; 392*4882a593Smuzhiyun 393*4882a593Smuzhiyun static const unsigned int uart_tx_ao_b1_pins[] = { GPIOAO_4 }; 394*4882a593Smuzhiyun static const unsigned int uart_rx_ao_b1_pins[] = { GPIOAO_5 }; 395*4882a593Smuzhiyun 396*4882a593Smuzhiyun static const unsigned int i2c_mst_sck_ao_pins[] = { GPIOAO_4 }; 397*4882a593Smuzhiyun static const unsigned int i2c_mst_sda_ao_pins[] = { GPIOAO_5 }; 398*4882a593Smuzhiyun 399*4882a593Smuzhiyun static const unsigned int pwm_f_ao_pins[] = { GPIO_TEST_N }; 400*4882a593Smuzhiyun 401*4882a593Smuzhiyun static const unsigned int i2s_am_clk_out_ao_pins[] = { GPIOAO_8 }; 402*4882a593Smuzhiyun static const unsigned int i2s_ao_clk_out_ao_pins[] = { GPIOAO_9 }; 403*4882a593Smuzhiyun static const unsigned int i2s_lr_clk_out_ao_pins[] = { GPIOAO_10 }; 404*4882a593Smuzhiyun static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 }; 405*4882a593Smuzhiyun 406*4882a593Smuzhiyun static const unsigned int hdmi_cec_ao_pins[] = { GPIOAO_12 }; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun static struct meson_pmx_group meson8_cbus_groups[] = { 409*4882a593Smuzhiyun GPIO_GROUP(GPIOX_0), 410*4882a593Smuzhiyun GPIO_GROUP(GPIOX_1), 411*4882a593Smuzhiyun GPIO_GROUP(GPIOX_2), 412*4882a593Smuzhiyun GPIO_GROUP(GPIOX_3), 413*4882a593Smuzhiyun GPIO_GROUP(GPIOX_4), 414*4882a593Smuzhiyun GPIO_GROUP(GPIOX_5), 415*4882a593Smuzhiyun GPIO_GROUP(GPIOX_6), 416*4882a593Smuzhiyun GPIO_GROUP(GPIOX_7), 417*4882a593Smuzhiyun GPIO_GROUP(GPIOX_8), 418*4882a593Smuzhiyun GPIO_GROUP(GPIOX_9), 419*4882a593Smuzhiyun GPIO_GROUP(GPIOX_10), 420*4882a593Smuzhiyun GPIO_GROUP(GPIOX_11), 421*4882a593Smuzhiyun GPIO_GROUP(GPIOX_12), 422*4882a593Smuzhiyun GPIO_GROUP(GPIOX_13), 423*4882a593Smuzhiyun GPIO_GROUP(GPIOX_14), 424*4882a593Smuzhiyun GPIO_GROUP(GPIOX_15), 425*4882a593Smuzhiyun GPIO_GROUP(GPIOX_16), 426*4882a593Smuzhiyun GPIO_GROUP(GPIOX_17), 427*4882a593Smuzhiyun GPIO_GROUP(GPIOX_18), 428*4882a593Smuzhiyun GPIO_GROUP(GPIOX_19), 429*4882a593Smuzhiyun GPIO_GROUP(GPIOX_20), 430*4882a593Smuzhiyun GPIO_GROUP(GPIOX_21), 431*4882a593Smuzhiyun GPIO_GROUP(GPIOY_0), 432*4882a593Smuzhiyun GPIO_GROUP(GPIOY_1), 433*4882a593Smuzhiyun GPIO_GROUP(GPIOY_2), 434*4882a593Smuzhiyun GPIO_GROUP(GPIOY_3), 435*4882a593Smuzhiyun GPIO_GROUP(GPIOY_4), 436*4882a593Smuzhiyun GPIO_GROUP(GPIOY_5), 437*4882a593Smuzhiyun GPIO_GROUP(GPIOY_6), 438*4882a593Smuzhiyun GPIO_GROUP(GPIOY_7), 439*4882a593Smuzhiyun GPIO_GROUP(GPIOY_8), 440*4882a593Smuzhiyun GPIO_GROUP(GPIOY_9), 441*4882a593Smuzhiyun GPIO_GROUP(GPIOY_10), 442*4882a593Smuzhiyun GPIO_GROUP(GPIOY_11), 443*4882a593Smuzhiyun GPIO_GROUP(GPIOY_12), 444*4882a593Smuzhiyun GPIO_GROUP(GPIOY_13), 445*4882a593Smuzhiyun GPIO_GROUP(GPIOY_14), 446*4882a593Smuzhiyun GPIO_GROUP(GPIOY_15), 447*4882a593Smuzhiyun GPIO_GROUP(GPIOY_16), 448*4882a593Smuzhiyun GPIO_GROUP(GPIODV_0), 449*4882a593Smuzhiyun GPIO_GROUP(GPIODV_1), 450*4882a593Smuzhiyun GPIO_GROUP(GPIODV_2), 451*4882a593Smuzhiyun GPIO_GROUP(GPIODV_3), 452*4882a593Smuzhiyun GPIO_GROUP(GPIODV_4), 453*4882a593Smuzhiyun GPIO_GROUP(GPIODV_5), 454*4882a593Smuzhiyun GPIO_GROUP(GPIODV_6), 455*4882a593Smuzhiyun GPIO_GROUP(GPIODV_7), 456*4882a593Smuzhiyun GPIO_GROUP(GPIODV_8), 457*4882a593Smuzhiyun GPIO_GROUP(GPIODV_9), 458*4882a593Smuzhiyun GPIO_GROUP(GPIODV_10), 459*4882a593Smuzhiyun GPIO_GROUP(GPIODV_11), 460*4882a593Smuzhiyun GPIO_GROUP(GPIODV_12), 461*4882a593Smuzhiyun GPIO_GROUP(GPIODV_13), 462*4882a593Smuzhiyun GPIO_GROUP(GPIODV_14), 463*4882a593Smuzhiyun GPIO_GROUP(GPIODV_15), 464*4882a593Smuzhiyun GPIO_GROUP(GPIODV_16), 465*4882a593Smuzhiyun GPIO_GROUP(GPIODV_17), 466*4882a593Smuzhiyun GPIO_GROUP(GPIODV_18), 467*4882a593Smuzhiyun GPIO_GROUP(GPIODV_19), 468*4882a593Smuzhiyun GPIO_GROUP(GPIODV_20), 469*4882a593Smuzhiyun GPIO_GROUP(GPIODV_21), 470*4882a593Smuzhiyun GPIO_GROUP(GPIODV_22), 471*4882a593Smuzhiyun GPIO_GROUP(GPIODV_23), 472*4882a593Smuzhiyun GPIO_GROUP(GPIODV_24), 473*4882a593Smuzhiyun GPIO_GROUP(GPIODV_25), 474*4882a593Smuzhiyun GPIO_GROUP(GPIODV_26), 475*4882a593Smuzhiyun GPIO_GROUP(GPIODV_27), 476*4882a593Smuzhiyun GPIO_GROUP(GPIODV_28), 477*4882a593Smuzhiyun GPIO_GROUP(GPIODV_29), 478*4882a593Smuzhiyun GPIO_GROUP(GPIOH_0), 479*4882a593Smuzhiyun GPIO_GROUP(GPIOH_1), 480*4882a593Smuzhiyun GPIO_GROUP(GPIOH_2), 481*4882a593Smuzhiyun GPIO_GROUP(GPIOH_3), 482*4882a593Smuzhiyun GPIO_GROUP(GPIOH_4), 483*4882a593Smuzhiyun GPIO_GROUP(GPIOH_5), 484*4882a593Smuzhiyun GPIO_GROUP(GPIOH_6), 485*4882a593Smuzhiyun GPIO_GROUP(GPIOH_7), 486*4882a593Smuzhiyun GPIO_GROUP(GPIOH_8), 487*4882a593Smuzhiyun GPIO_GROUP(GPIOH_9), 488*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_0), 489*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_1), 490*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_2), 491*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_3), 492*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_4), 493*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_5), 494*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_6), 495*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_7), 496*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_8), 497*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_9), 498*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_10), 499*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_11), 500*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_12), 501*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_13), 502*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_14), 503*4882a593Smuzhiyun GPIO_GROUP(CARD_0), 504*4882a593Smuzhiyun GPIO_GROUP(CARD_1), 505*4882a593Smuzhiyun GPIO_GROUP(CARD_2), 506*4882a593Smuzhiyun GPIO_GROUP(CARD_3), 507*4882a593Smuzhiyun GPIO_GROUP(CARD_4), 508*4882a593Smuzhiyun GPIO_GROUP(CARD_5), 509*4882a593Smuzhiyun GPIO_GROUP(CARD_6), 510*4882a593Smuzhiyun GPIO_GROUP(BOOT_0), 511*4882a593Smuzhiyun GPIO_GROUP(BOOT_1), 512*4882a593Smuzhiyun GPIO_GROUP(BOOT_2), 513*4882a593Smuzhiyun GPIO_GROUP(BOOT_3), 514*4882a593Smuzhiyun GPIO_GROUP(BOOT_4), 515*4882a593Smuzhiyun GPIO_GROUP(BOOT_5), 516*4882a593Smuzhiyun GPIO_GROUP(BOOT_6), 517*4882a593Smuzhiyun GPIO_GROUP(BOOT_7), 518*4882a593Smuzhiyun GPIO_GROUP(BOOT_8), 519*4882a593Smuzhiyun GPIO_GROUP(BOOT_9), 520*4882a593Smuzhiyun GPIO_GROUP(BOOT_10), 521*4882a593Smuzhiyun GPIO_GROUP(BOOT_11), 522*4882a593Smuzhiyun GPIO_GROUP(BOOT_12), 523*4882a593Smuzhiyun GPIO_GROUP(BOOT_13), 524*4882a593Smuzhiyun GPIO_GROUP(BOOT_14), 525*4882a593Smuzhiyun GPIO_GROUP(BOOT_15), 526*4882a593Smuzhiyun GPIO_GROUP(BOOT_16), 527*4882a593Smuzhiyun GPIO_GROUP(BOOT_17), 528*4882a593Smuzhiyun GPIO_GROUP(BOOT_18), 529*4882a593Smuzhiyun 530*4882a593Smuzhiyun /* bank X */ 531*4882a593Smuzhiyun GROUP(sd_d0_a, 8, 5), 532*4882a593Smuzhiyun GROUP(sd_d1_a, 8, 4), 533*4882a593Smuzhiyun GROUP(sd_d2_a, 8, 3), 534*4882a593Smuzhiyun GROUP(sd_d3_a, 8, 2), 535*4882a593Smuzhiyun GROUP(sd_clk_a, 8, 1), 536*4882a593Smuzhiyun GROUP(sd_cmd_a, 8, 0), 537*4882a593Smuzhiyun 538*4882a593Smuzhiyun GROUP(sdxc_d0_a, 5, 14), 539*4882a593Smuzhiyun GROUP(sdxc_d13_a, 5, 13), 540*4882a593Smuzhiyun GROUP(sdxc_d47_a, 5, 12), 541*4882a593Smuzhiyun GROUP(sdxc_clk_a, 5, 11), 542*4882a593Smuzhiyun GROUP(sdxc_cmd_a, 5, 10), 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun GROUP(pcm_out_a, 3, 30), 545*4882a593Smuzhiyun GROUP(pcm_in_a, 3, 29), 546*4882a593Smuzhiyun GROUP(pcm_fs_a, 3, 28), 547*4882a593Smuzhiyun GROUP(pcm_clk_a, 3, 27), 548*4882a593Smuzhiyun 549*4882a593Smuzhiyun GROUP(uart_tx_a0, 4, 17), 550*4882a593Smuzhiyun GROUP(uart_rx_a0, 4, 16), 551*4882a593Smuzhiyun GROUP(uart_cts_a0, 4, 15), 552*4882a593Smuzhiyun GROUP(uart_rts_a0, 4, 14), 553*4882a593Smuzhiyun 554*4882a593Smuzhiyun GROUP(uart_tx_a1, 4, 13), 555*4882a593Smuzhiyun GROUP(uart_rx_a1, 4, 12), 556*4882a593Smuzhiyun GROUP(uart_cts_a1, 4, 11), 557*4882a593Smuzhiyun GROUP(uart_rts_a1, 4, 10), 558*4882a593Smuzhiyun 559*4882a593Smuzhiyun GROUP(uart_tx_b0, 4, 9), 560*4882a593Smuzhiyun GROUP(uart_rx_b0, 4, 8), 561*4882a593Smuzhiyun GROUP(uart_cts_b0, 4, 7), 562*4882a593Smuzhiyun GROUP(uart_rts_b0, 4, 6), 563*4882a593Smuzhiyun 564*4882a593Smuzhiyun GROUP(iso7816_det, 4, 21), 565*4882a593Smuzhiyun GROUP(iso7816_reset, 4, 20), 566*4882a593Smuzhiyun GROUP(iso7816_clk, 4, 19), 567*4882a593Smuzhiyun GROUP(iso7816_data, 4, 18), 568*4882a593Smuzhiyun 569*4882a593Smuzhiyun GROUP(i2c_sda_d0, 4, 5), 570*4882a593Smuzhiyun GROUP(i2c_sck_d0, 4, 4), 571*4882a593Smuzhiyun 572*4882a593Smuzhiyun GROUP(xtal_32k_out, 3, 22), 573*4882a593Smuzhiyun GROUP(xtal_24m_out, 3, 23), 574*4882a593Smuzhiyun 575*4882a593Smuzhiyun GROUP(pwm_e, 9, 19), 576*4882a593Smuzhiyun GROUP(pwm_b_x, 2, 3), 577*4882a593Smuzhiyun 578*4882a593Smuzhiyun /* bank Y */ 579*4882a593Smuzhiyun GROUP(uart_tx_c, 1, 19), 580*4882a593Smuzhiyun GROUP(uart_rx_c, 1, 18), 581*4882a593Smuzhiyun GROUP(uart_cts_c, 1, 17), 582*4882a593Smuzhiyun GROUP(uart_rts_c, 1, 16), 583*4882a593Smuzhiyun 584*4882a593Smuzhiyun GROUP(pcm_out_b, 4, 25), 585*4882a593Smuzhiyun GROUP(pcm_in_b, 4, 24), 586*4882a593Smuzhiyun GROUP(pcm_fs_b, 4, 23), 587*4882a593Smuzhiyun GROUP(pcm_clk_b, 4, 22), 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun GROUP(i2c_sda_c0, 1, 15), 590*4882a593Smuzhiyun GROUP(i2c_sck_c0, 1, 14), 591*4882a593Smuzhiyun 592*4882a593Smuzhiyun GROUP(pwm_a_y, 9, 14), 593*4882a593Smuzhiyun 594*4882a593Smuzhiyun GROUP(i2s_out_ch45, 1, 10), 595*4882a593Smuzhiyun GROUP(i2s_out_ch23, 1, 19), 596*4882a593Smuzhiyun GROUP(i2s_out_ch01, 1, 6), 597*4882a593Smuzhiyun GROUP(i2s_in_ch01, 1, 5), 598*4882a593Smuzhiyun GROUP(i2s_lr_clk_in, 1, 4), 599*4882a593Smuzhiyun GROUP(i2s_ao_clk_in, 1, 2), 600*4882a593Smuzhiyun GROUP(i2s_am_clk, 1, 0), 601*4882a593Smuzhiyun GROUP(i2s_out_ch78, 1, 11), 602*4882a593Smuzhiyun 603*4882a593Smuzhiyun GROUP(spdif_in, 1, 8), 604*4882a593Smuzhiyun GROUP(spdif_out, 1, 7), 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun /* bank DV */ 607*4882a593Smuzhiyun GROUP(dvin_rgb, 0, 6), 608*4882a593Smuzhiyun GROUP(dvin_vs, 0, 9), 609*4882a593Smuzhiyun GROUP(dvin_hs, 0, 8), 610*4882a593Smuzhiyun GROUP(dvin_clk, 0, 7), 611*4882a593Smuzhiyun GROUP(dvin_de, 0, 10), 612*4882a593Smuzhiyun 613*4882a593Smuzhiyun GROUP(enc_0, 7, 0), 614*4882a593Smuzhiyun GROUP(enc_1, 7, 1), 615*4882a593Smuzhiyun GROUP(enc_2, 7, 2), 616*4882a593Smuzhiyun GROUP(enc_3, 7, 3), 617*4882a593Smuzhiyun GROUP(enc_4, 7, 4), 618*4882a593Smuzhiyun GROUP(enc_5, 7, 5), 619*4882a593Smuzhiyun GROUP(enc_6, 7, 6), 620*4882a593Smuzhiyun GROUP(enc_7, 7, 7), 621*4882a593Smuzhiyun GROUP(enc_8, 7, 8), 622*4882a593Smuzhiyun GROUP(enc_9, 7, 9), 623*4882a593Smuzhiyun GROUP(enc_10, 7, 10), 624*4882a593Smuzhiyun GROUP(enc_11, 7, 11), 625*4882a593Smuzhiyun GROUP(enc_12, 7, 12), 626*4882a593Smuzhiyun GROUP(enc_13, 7, 13), 627*4882a593Smuzhiyun GROUP(enc_14, 7, 14), 628*4882a593Smuzhiyun GROUP(enc_15, 7, 15), 629*4882a593Smuzhiyun GROUP(enc_16, 7, 16), 630*4882a593Smuzhiyun GROUP(enc_17, 7, 17), 631*4882a593Smuzhiyun 632*4882a593Smuzhiyun GROUP(uart_tx_b1, 6, 23), 633*4882a593Smuzhiyun GROUP(uart_rx_b1, 6, 22), 634*4882a593Smuzhiyun GROUP(uart_cts_b1, 6, 21), 635*4882a593Smuzhiyun GROUP(uart_rts_b1, 6, 20), 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun GROUP(vga_vs, 0, 21), 638*4882a593Smuzhiyun GROUP(vga_hs, 0, 20), 639*4882a593Smuzhiyun 640*4882a593Smuzhiyun GROUP(pwm_c_dv9, 3, 24), 641*4882a593Smuzhiyun GROUP(pwm_c_dv29, 3, 25), 642*4882a593Smuzhiyun GROUP(pwm_d, 3, 26), 643*4882a593Smuzhiyun 644*4882a593Smuzhiyun /* bank H */ 645*4882a593Smuzhiyun GROUP(hdmi_hpd, 1, 26), 646*4882a593Smuzhiyun GROUP(hdmi_sda, 1, 25), 647*4882a593Smuzhiyun GROUP(hdmi_scl, 1, 24), 648*4882a593Smuzhiyun GROUP(hdmi_cec, 1, 23), 649*4882a593Smuzhiyun 650*4882a593Smuzhiyun GROUP(spi_ss0_0, 9, 13), 651*4882a593Smuzhiyun GROUP(spi_miso_0, 9, 12), 652*4882a593Smuzhiyun GROUP(spi_mosi_0, 9, 11), 653*4882a593Smuzhiyun GROUP(spi_sclk_0, 9, 10), 654*4882a593Smuzhiyun 655*4882a593Smuzhiyun GROUP(i2c_sda_d1, 4, 3), 656*4882a593Smuzhiyun GROUP(i2c_sck_d1, 4, 2), 657*4882a593Smuzhiyun 658*4882a593Smuzhiyun /* bank Z */ 659*4882a593Smuzhiyun GROUP(spi_ss0_1, 8, 16), 660*4882a593Smuzhiyun GROUP(spi_ss1_1, 8, 12), 661*4882a593Smuzhiyun GROUP(spi_sclk_1, 8, 15), 662*4882a593Smuzhiyun GROUP(spi_mosi_1, 8, 14), 663*4882a593Smuzhiyun GROUP(spi_miso_1, 8, 13), 664*4882a593Smuzhiyun GROUP(spi_ss2_1, 8, 17), 665*4882a593Smuzhiyun 666*4882a593Smuzhiyun GROUP(eth_tx_clk_50m, 6, 15), 667*4882a593Smuzhiyun GROUP(eth_tx_en, 6, 14), 668*4882a593Smuzhiyun GROUP(eth_txd1, 6, 13), 669*4882a593Smuzhiyun GROUP(eth_txd0, 6, 12), 670*4882a593Smuzhiyun GROUP(eth_rx_clk_in, 6, 10), 671*4882a593Smuzhiyun GROUP(eth_rx_dv, 6, 11), 672*4882a593Smuzhiyun GROUP(eth_rxd1, 6, 8), 673*4882a593Smuzhiyun GROUP(eth_rxd0, 6, 7), 674*4882a593Smuzhiyun GROUP(eth_mdio, 6, 6), 675*4882a593Smuzhiyun GROUP(eth_mdc, 6, 5), 676*4882a593Smuzhiyun 677*4882a593Smuzhiyun /* NOTE: the following four groups are only available on Meson8m2: */ 678*4882a593Smuzhiyun GROUP(eth_rxd2, 6, 3), 679*4882a593Smuzhiyun GROUP(eth_rxd3, 6, 2), 680*4882a593Smuzhiyun GROUP(eth_txd2, 6, 1), 681*4882a593Smuzhiyun GROUP(eth_txd3, 6, 0), 682*4882a593Smuzhiyun 683*4882a593Smuzhiyun GROUP(i2c_sda_a0, 5, 31), 684*4882a593Smuzhiyun GROUP(i2c_sck_a0, 5, 30), 685*4882a593Smuzhiyun 686*4882a593Smuzhiyun GROUP(i2c_sda_b, 5, 27), 687*4882a593Smuzhiyun GROUP(i2c_sck_b, 5, 26), 688*4882a593Smuzhiyun 689*4882a593Smuzhiyun GROUP(i2c_sda_c1, 5, 25), 690*4882a593Smuzhiyun GROUP(i2c_sck_c1, 5, 24), 691*4882a593Smuzhiyun 692*4882a593Smuzhiyun GROUP(i2c_sda_a1, 5, 9), 693*4882a593Smuzhiyun GROUP(i2c_sck_a1, 5, 8), 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun GROUP(i2c_sda_a2, 5, 7), 696*4882a593Smuzhiyun GROUP(i2c_sck_a2, 5, 6), 697*4882a593Smuzhiyun 698*4882a593Smuzhiyun GROUP(pwm_a_z0, 9, 16), 699*4882a593Smuzhiyun GROUP(pwm_a_z7, 2, 0), 700*4882a593Smuzhiyun GROUP(pwm_b_z, 9, 15), 701*4882a593Smuzhiyun GROUP(pwm_c_z, 2, 1), 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun /* bank BOOT */ 704*4882a593Smuzhiyun GROUP(sd_d0_c, 6, 29), 705*4882a593Smuzhiyun GROUP(sd_d1_c, 6, 28), 706*4882a593Smuzhiyun GROUP(sd_d2_c, 6, 27), 707*4882a593Smuzhiyun GROUP(sd_d3_c, 6, 26), 708*4882a593Smuzhiyun GROUP(sd_cmd_c, 6, 25), 709*4882a593Smuzhiyun GROUP(sd_clk_c, 6, 24), 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun GROUP(sdxc_d0_c, 4, 30), 712*4882a593Smuzhiyun GROUP(sdxc_d13_c, 4, 29), 713*4882a593Smuzhiyun GROUP(sdxc_d47_c, 4, 28), 714*4882a593Smuzhiyun GROUP(sdxc_cmd_c, 4, 27), 715*4882a593Smuzhiyun GROUP(sdxc_clk_c, 4, 26), 716*4882a593Smuzhiyun 717*4882a593Smuzhiyun GROUP(nand_io, 2, 26), 718*4882a593Smuzhiyun GROUP(nand_io_ce0, 2, 25), 719*4882a593Smuzhiyun GROUP(nand_io_ce1, 2, 24), 720*4882a593Smuzhiyun GROUP(nand_io_rb0, 2, 17), 721*4882a593Smuzhiyun GROUP(nand_ale, 2, 21), 722*4882a593Smuzhiyun GROUP(nand_cle, 2, 20), 723*4882a593Smuzhiyun GROUP(nand_wen_clk, 2, 19), 724*4882a593Smuzhiyun GROUP(nand_ren_clk, 2, 18), 725*4882a593Smuzhiyun GROUP(nand_dqs, 2, 27), 726*4882a593Smuzhiyun GROUP(nand_ce2, 2, 23), 727*4882a593Smuzhiyun GROUP(nand_ce3, 2, 22), 728*4882a593Smuzhiyun 729*4882a593Smuzhiyun GROUP(nor_d, 5, 1), 730*4882a593Smuzhiyun GROUP(nor_q, 5, 3), 731*4882a593Smuzhiyun GROUP(nor_c, 5, 2), 732*4882a593Smuzhiyun GROUP(nor_cs, 5, 0), 733*4882a593Smuzhiyun 734*4882a593Smuzhiyun /* bank CARD */ 735*4882a593Smuzhiyun GROUP(sd_d1_b, 2, 14), 736*4882a593Smuzhiyun GROUP(sd_d0_b, 2, 15), 737*4882a593Smuzhiyun GROUP(sd_clk_b, 2, 11), 738*4882a593Smuzhiyun GROUP(sd_cmd_b, 2, 10), 739*4882a593Smuzhiyun GROUP(sd_d3_b, 2, 12), 740*4882a593Smuzhiyun GROUP(sd_d2_b, 2, 13), 741*4882a593Smuzhiyun 742*4882a593Smuzhiyun GROUP(sdxc_d13_b, 2, 6), 743*4882a593Smuzhiyun GROUP(sdxc_d0_b, 2, 7), 744*4882a593Smuzhiyun GROUP(sdxc_clk_b, 2, 5), 745*4882a593Smuzhiyun GROUP(sdxc_cmd_b, 2, 4), 746*4882a593Smuzhiyun }; 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun static struct meson_pmx_group meson8_aobus_groups[] = { 749*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_0), 750*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_1), 751*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_2), 752*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_3), 753*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_4), 754*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_5), 755*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_6), 756*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_7), 757*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_8), 758*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_9), 759*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_10), 760*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_11), 761*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_12), 762*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_13), 763*4882a593Smuzhiyun GPIO_GROUP(GPIO_BSD_EN), 764*4882a593Smuzhiyun GPIO_GROUP(GPIO_TEST_N), 765*4882a593Smuzhiyun 766*4882a593Smuzhiyun /* bank AO */ 767*4882a593Smuzhiyun GROUP(uart_tx_ao_a, 0, 12), 768*4882a593Smuzhiyun GROUP(uart_rx_ao_a, 0, 11), 769*4882a593Smuzhiyun GROUP(uart_cts_ao_a, 0, 10), 770*4882a593Smuzhiyun GROUP(uart_rts_ao_a, 0, 9), 771*4882a593Smuzhiyun 772*4882a593Smuzhiyun GROUP(remote_input, 0, 0), 773*4882a593Smuzhiyun GROUP(remote_output_ao, 0, 31), 774*4882a593Smuzhiyun 775*4882a593Smuzhiyun GROUP(i2c_slave_sck_ao, 0, 2), 776*4882a593Smuzhiyun GROUP(i2c_slave_sda_ao, 0, 1), 777*4882a593Smuzhiyun 778*4882a593Smuzhiyun GROUP(uart_tx_ao_b0, 0, 26), 779*4882a593Smuzhiyun GROUP(uart_rx_ao_b0, 0, 25), 780*4882a593Smuzhiyun 781*4882a593Smuzhiyun GROUP(uart_tx_ao_b1, 0, 24), 782*4882a593Smuzhiyun GROUP(uart_rx_ao_b1, 0, 23), 783*4882a593Smuzhiyun 784*4882a593Smuzhiyun GROUP(i2c_mst_sck_ao, 0, 6), 785*4882a593Smuzhiyun GROUP(i2c_mst_sda_ao, 0, 5), 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun GROUP(pwm_f_ao, 0, 19), 788*4882a593Smuzhiyun 789*4882a593Smuzhiyun GROUP(i2s_am_clk_out_ao, 0, 30), 790*4882a593Smuzhiyun GROUP(i2s_ao_clk_out_ao, 0, 29), 791*4882a593Smuzhiyun GROUP(i2s_lr_clk_out_ao, 0, 28), 792*4882a593Smuzhiyun GROUP(i2s_out_ch01_ao, 0, 27), 793*4882a593Smuzhiyun 794*4882a593Smuzhiyun GROUP(hdmi_cec_ao, 0, 17), 795*4882a593Smuzhiyun }; 796*4882a593Smuzhiyun 797*4882a593Smuzhiyun static const char * const gpio_periphs_groups[] = { 798*4882a593Smuzhiyun "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", 799*4882a593Smuzhiyun "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", 800*4882a593Smuzhiyun "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", 801*4882a593Smuzhiyun "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", 802*4882a593Smuzhiyun "GPIOX_20", "GPIOX_21", 803*4882a593Smuzhiyun 804*4882a593Smuzhiyun "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", 805*4882a593Smuzhiyun "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", 806*4882a593Smuzhiyun "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", 807*4882a593Smuzhiyun "GPIOY_15", "GPIOY_16", 808*4882a593Smuzhiyun 809*4882a593Smuzhiyun "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4", 810*4882a593Smuzhiyun "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9", 811*4882a593Smuzhiyun "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14", 812*4882a593Smuzhiyun "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19", 813*4882a593Smuzhiyun "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24", 814*4882a593Smuzhiyun "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29", 815*4882a593Smuzhiyun 816*4882a593Smuzhiyun "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", 817*4882a593Smuzhiyun "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", 818*4882a593Smuzhiyun 819*4882a593Smuzhiyun "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", 820*4882a593Smuzhiyun "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", 821*4882a593Smuzhiyun "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", 822*4882a593Smuzhiyun 823*4882a593Smuzhiyun "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", 824*4882a593Smuzhiyun "CARD_5", "CARD_6", 825*4882a593Smuzhiyun 826*4882a593Smuzhiyun "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", 827*4882a593Smuzhiyun "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", 828*4882a593Smuzhiyun "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", 829*4882a593Smuzhiyun "BOOT_15", "BOOT_16", "BOOT_17", "BOOT_18", 830*4882a593Smuzhiyun }; 831*4882a593Smuzhiyun 832*4882a593Smuzhiyun static const char * const gpio_aobus_groups[] = { 833*4882a593Smuzhiyun "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", 834*4882a593Smuzhiyun "GPIOAO_4", "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", 835*4882a593Smuzhiyun "GPIOAO_8", "GPIOAO_9", "GPIOAO_10", "GPIOAO_11", 836*4882a593Smuzhiyun "GPIOAO_12", "GPIOAO_13", "GPIO_BSD_EN", "GPIO_TEST_N" 837*4882a593Smuzhiyun }; 838*4882a593Smuzhiyun 839*4882a593Smuzhiyun static const char * const sd_a_groups[] = { 840*4882a593Smuzhiyun "sd_d0_a", "sd_d1_a", "sd_d2_a", "sd_d3_a", "sd_clk_a", "sd_cmd_a" 841*4882a593Smuzhiyun }; 842*4882a593Smuzhiyun 843*4882a593Smuzhiyun static const char * const sdxc_a_groups[] = { 844*4882a593Smuzhiyun "sdxc_d0_a", "sdxc_d13_a", "sdxc_d47_a", "sdxc_clk_a", "sdxc_cmd_a" 845*4882a593Smuzhiyun }; 846*4882a593Smuzhiyun 847*4882a593Smuzhiyun static const char * const pcm_a_groups[] = { 848*4882a593Smuzhiyun "pcm_out_a", "pcm_in_a", "pcm_fs_a", "pcm_clk_a" 849*4882a593Smuzhiyun }; 850*4882a593Smuzhiyun 851*4882a593Smuzhiyun static const char * const uart_a_groups[] = { 852*4882a593Smuzhiyun "uart_tx_a0", "uart_rx_a0", "uart_cts_a0", "uart_rts_a0", 853*4882a593Smuzhiyun "uart_tx_a1", "uart_rx_a1", "uart_cts_a1", "uart_rts_a1" 854*4882a593Smuzhiyun }; 855*4882a593Smuzhiyun 856*4882a593Smuzhiyun static const char * const uart_b_groups[] = { 857*4882a593Smuzhiyun "uart_tx_b0", "uart_rx_b0", "uart_cts_b0", "uart_rts_b0", 858*4882a593Smuzhiyun "uart_tx_b1", "uart_rx_b1", "uart_cts_b1", "uart_rts_b1" 859*4882a593Smuzhiyun }; 860*4882a593Smuzhiyun 861*4882a593Smuzhiyun static const char * const iso7816_groups[] = { 862*4882a593Smuzhiyun "iso7816_det", "iso7816_reset", "iso7816_clk", "iso7816_data" 863*4882a593Smuzhiyun }; 864*4882a593Smuzhiyun 865*4882a593Smuzhiyun static const char * const i2c_d_groups[] = { 866*4882a593Smuzhiyun "i2c_sda_d0", "i2c_sck_d0", "i2c_sda_d1", "i2c_sck_d1" 867*4882a593Smuzhiyun }; 868*4882a593Smuzhiyun 869*4882a593Smuzhiyun static const char * const xtal_groups[] = { 870*4882a593Smuzhiyun "xtal_32k_out", "xtal_24m_out" 871*4882a593Smuzhiyun }; 872*4882a593Smuzhiyun 873*4882a593Smuzhiyun static const char * const uart_c_groups[] = { 874*4882a593Smuzhiyun "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c" 875*4882a593Smuzhiyun }; 876*4882a593Smuzhiyun 877*4882a593Smuzhiyun static const char * const pcm_b_groups[] = { 878*4882a593Smuzhiyun "pcm_out_b", "pcm_in_b", "pcm_fs_b", "pcm_clk_b" 879*4882a593Smuzhiyun }; 880*4882a593Smuzhiyun 881*4882a593Smuzhiyun static const char * const i2c_c_groups[] = { 882*4882a593Smuzhiyun "i2c_sda_c0", "i2c_sck_c0", "i2c_sda_c1", "i2c_sck_c1" 883*4882a593Smuzhiyun }; 884*4882a593Smuzhiyun 885*4882a593Smuzhiyun static const char * const dvin_groups[] = { 886*4882a593Smuzhiyun "dvin_rgb", "dvin_vs", "dvin_hs", "dvin_clk", "dvin_de" 887*4882a593Smuzhiyun }; 888*4882a593Smuzhiyun 889*4882a593Smuzhiyun static const char * const enc_groups[] = { 890*4882a593Smuzhiyun "enc_0", "enc_1", "enc_2", "enc_3", "enc_4", "enc_5", 891*4882a593Smuzhiyun "enc_6", "enc_7", "enc_8", "enc_9", "enc_10", "enc_11", 892*4882a593Smuzhiyun "enc_12", "enc_13", "enc_14", "enc_15", "enc_16", "enc_17" 893*4882a593Smuzhiyun }; 894*4882a593Smuzhiyun 895*4882a593Smuzhiyun static const char * const vga_groups[] = { 896*4882a593Smuzhiyun "vga_vs", "vga_hs" 897*4882a593Smuzhiyun }; 898*4882a593Smuzhiyun 899*4882a593Smuzhiyun static const char * const hdmi_groups[] = { 900*4882a593Smuzhiyun "hdmi_hpd", "hdmi_sda", "hdmi_scl", "hdmi_cec" 901*4882a593Smuzhiyun }; 902*4882a593Smuzhiyun 903*4882a593Smuzhiyun static const char * const spi_groups[] = { 904*4882a593Smuzhiyun "spi_ss0_0", "spi_miso_0", "spi_mosi_0", "spi_sclk_0", 905*4882a593Smuzhiyun "spi_ss0_1", "spi_ss1_1", "spi_sclk_1", "spi_mosi_1", 906*4882a593Smuzhiyun "spi_miso_1", "spi_ss2_1" 907*4882a593Smuzhiyun }; 908*4882a593Smuzhiyun 909*4882a593Smuzhiyun static const char * const ethernet_groups[] = { 910*4882a593Smuzhiyun "eth_tx_clk_50m", "eth_tx_en", "eth_txd1", 911*4882a593Smuzhiyun "eth_txd0", "eth_rx_clk_in", "eth_rx_dv", 912*4882a593Smuzhiyun "eth_rxd1", "eth_rxd0", "eth_mdio", "eth_mdc", "eth_rxd2", 913*4882a593Smuzhiyun "eth_rxd3", "eth_txd2", "eth_txd3" 914*4882a593Smuzhiyun }; 915*4882a593Smuzhiyun 916*4882a593Smuzhiyun static const char * const i2c_a_groups[] = { 917*4882a593Smuzhiyun "i2c_sda_a0", "i2c_sck_a0", "i2c_sda_a1", "i2c_sck_a1", 918*4882a593Smuzhiyun "i2c_sda_a2", "i2c_sck_a2" 919*4882a593Smuzhiyun }; 920*4882a593Smuzhiyun 921*4882a593Smuzhiyun static const char * const i2c_b_groups[] = { 922*4882a593Smuzhiyun "i2c_sda_b", "i2c_sck_b" 923*4882a593Smuzhiyun }; 924*4882a593Smuzhiyun 925*4882a593Smuzhiyun static const char * const i2s_groups[] = { 926*4882a593Smuzhiyun "i2s_out_ch45", "i2s_out_ch23_pins", "i2s_out_ch01_pins", 927*4882a593Smuzhiyun "i2s_in_ch01_pins", "i2s_lr_clk_in_pins", "i2s_ao_clk_in_pins", 928*4882a593Smuzhiyun "i2s_am_clk_pins", "i2s_out_ch78_pins" 929*4882a593Smuzhiyun }; 930*4882a593Smuzhiyun 931*4882a593Smuzhiyun static const char * const sd_c_groups[] = { 932*4882a593Smuzhiyun "sd_d0_c", "sd_d1_c", "sd_d2_c", "sd_d3_c", 933*4882a593Smuzhiyun "sd_cmd_c", "sd_clk_c" 934*4882a593Smuzhiyun }; 935*4882a593Smuzhiyun 936*4882a593Smuzhiyun static const char * const sdxc_c_groups[] = { 937*4882a593Smuzhiyun "sdxc_d0_c", "sdxc_d13_c", "sdxc_d47_c", "sdxc_cmd_c", 938*4882a593Smuzhiyun "sdxc_clk_c" 939*4882a593Smuzhiyun }; 940*4882a593Smuzhiyun 941*4882a593Smuzhiyun static const char * const nand_groups[] = { 942*4882a593Smuzhiyun "nand_io", "nand_io_ce0", "nand_io_ce1", 943*4882a593Smuzhiyun "nand_io_rb0", "nand_ale", "nand_cle", 944*4882a593Smuzhiyun "nand_wen_clk", "nand_ren_clk", "nand_dqs", 945*4882a593Smuzhiyun "nand_ce2", "nand_ce3" 946*4882a593Smuzhiyun }; 947*4882a593Smuzhiyun 948*4882a593Smuzhiyun static const char * const nor_groups[] = { 949*4882a593Smuzhiyun "nor_d", "nor_q", "nor_c", "nor_cs" 950*4882a593Smuzhiyun }; 951*4882a593Smuzhiyun 952*4882a593Smuzhiyun static const char * const pwm_a_groups[] = { 953*4882a593Smuzhiyun "pwm_a_y", "pwm_a_z0", "pwm_a_z7" 954*4882a593Smuzhiyun }; 955*4882a593Smuzhiyun 956*4882a593Smuzhiyun static const char * const pwm_b_groups[] = { 957*4882a593Smuzhiyun "pwm_b_x", "pwm_b_z" 958*4882a593Smuzhiyun }; 959*4882a593Smuzhiyun 960*4882a593Smuzhiyun static const char * const pwm_c_groups[] = { 961*4882a593Smuzhiyun "pwm_c_dv9", "pwm_c_dv29", "pwm_c_z" 962*4882a593Smuzhiyun }; 963*4882a593Smuzhiyun 964*4882a593Smuzhiyun static const char * const pwm_d_groups[] = { 965*4882a593Smuzhiyun "pwm_d" 966*4882a593Smuzhiyun }; 967*4882a593Smuzhiyun 968*4882a593Smuzhiyun static const char * const pwm_e_groups[] = { 969*4882a593Smuzhiyun "pwm_e" 970*4882a593Smuzhiyun }; 971*4882a593Smuzhiyun 972*4882a593Smuzhiyun static const char * const sd_b_groups[] = { 973*4882a593Smuzhiyun "sd_d1_b", "sd_d0_b", "sd_clk_b", "sd_cmd_b", 974*4882a593Smuzhiyun "sd_d3_b", "sd_d2_b" 975*4882a593Smuzhiyun }; 976*4882a593Smuzhiyun 977*4882a593Smuzhiyun static const char * const sdxc_b_groups[] = { 978*4882a593Smuzhiyun "sdxc_d13_b", "sdxc_d0_b", "sdxc_clk_b", "sdxc_cmd_b" 979*4882a593Smuzhiyun }; 980*4882a593Smuzhiyun 981*4882a593Smuzhiyun static const char * const spdif_groups[] = { 982*4882a593Smuzhiyun "spdif_in", "spdif_out" 983*4882a593Smuzhiyun }; 984*4882a593Smuzhiyun 985*4882a593Smuzhiyun static const char * const uart_ao_groups[] = { 986*4882a593Smuzhiyun "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a" 987*4882a593Smuzhiyun }; 988*4882a593Smuzhiyun 989*4882a593Smuzhiyun static const char * const remote_groups[] = { 990*4882a593Smuzhiyun "remote_input", "remote_output_ao" 991*4882a593Smuzhiyun }; 992*4882a593Smuzhiyun 993*4882a593Smuzhiyun static const char * const i2c_slave_ao_groups[] = { 994*4882a593Smuzhiyun "i2c_slave_sck_ao", "i2c_slave_sda_ao" 995*4882a593Smuzhiyun }; 996*4882a593Smuzhiyun 997*4882a593Smuzhiyun static const char * const uart_ao_b_groups[] = { 998*4882a593Smuzhiyun "uart_tx_ao_b0", "uart_rx_ao_b0", "uart_tx_ao_b1", "uart_rx_ao_b1" 999*4882a593Smuzhiyun }; 1000*4882a593Smuzhiyun 1001*4882a593Smuzhiyun static const char * const i2c_mst_ao_groups[] = { 1002*4882a593Smuzhiyun "i2c_mst_sck_ao", "i2c_mst_sda_ao" 1003*4882a593Smuzhiyun }; 1004*4882a593Smuzhiyun 1005*4882a593Smuzhiyun static const char * const pwm_f_ao_groups[] = { 1006*4882a593Smuzhiyun "pwm_f_ao" 1007*4882a593Smuzhiyun }; 1008*4882a593Smuzhiyun 1009*4882a593Smuzhiyun static const char * const i2s_ao_groups[] = { 1010*4882a593Smuzhiyun "i2s_am_clk_out_ao", "i2s_ao_clk_out_ao", "i2s_lr_clk_out_ao", 1011*4882a593Smuzhiyun "i2s_out_ch01_ao" 1012*4882a593Smuzhiyun }; 1013*4882a593Smuzhiyun 1014*4882a593Smuzhiyun static const char * const hdmi_cec_ao_groups[] = { 1015*4882a593Smuzhiyun "hdmi_cec_ao" 1016*4882a593Smuzhiyun }; 1017*4882a593Smuzhiyun 1018*4882a593Smuzhiyun static struct meson_pmx_func meson8_cbus_functions[] = { 1019*4882a593Smuzhiyun FUNCTION(gpio_periphs), 1020*4882a593Smuzhiyun FUNCTION(sd_a), 1021*4882a593Smuzhiyun FUNCTION(sdxc_a), 1022*4882a593Smuzhiyun FUNCTION(pcm_a), 1023*4882a593Smuzhiyun FUNCTION(uart_a), 1024*4882a593Smuzhiyun FUNCTION(uart_b), 1025*4882a593Smuzhiyun FUNCTION(iso7816), 1026*4882a593Smuzhiyun FUNCTION(i2c_d), 1027*4882a593Smuzhiyun FUNCTION(xtal), 1028*4882a593Smuzhiyun FUNCTION(uart_c), 1029*4882a593Smuzhiyun FUNCTION(pcm_b), 1030*4882a593Smuzhiyun FUNCTION(i2c_c), 1031*4882a593Smuzhiyun FUNCTION(dvin), 1032*4882a593Smuzhiyun FUNCTION(enc), 1033*4882a593Smuzhiyun FUNCTION(vga), 1034*4882a593Smuzhiyun FUNCTION(hdmi), 1035*4882a593Smuzhiyun FUNCTION(spi), 1036*4882a593Smuzhiyun FUNCTION(ethernet), 1037*4882a593Smuzhiyun FUNCTION(i2c_a), 1038*4882a593Smuzhiyun FUNCTION(i2c_b), 1039*4882a593Smuzhiyun FUNCTION(sd_c), 1040*4882a593Smuzhiyun FUNCTION(sdxc_c), 1041*4882a593Smuzhiyun FUNCTION(nand), 1042*4882a593Smuzhiyun FUNCTION(nor), 1043*4882a593Smuzhiyun FUNCTION(sd_b), 1044*4882a593Smuzhiyun FUNCTION(sdxc_b), 1045*4882a593Smuzhiyun FUNCTION(pwm_a), 1046*4882a593Smuzhiyun FUNCTION(pwm_b), 1047*4882a593Smuzhiyun FUNCTION(pwm_c), 1048*4882a593Smuzhiyun FUNCTION(pwm_d), 1049*4882a593Smuzhiyun FUNCTION(pwm_e), 1050*4882a593Smuzhiyun FUNCTION(i2s), 1051*4882a593Smuzhiyun FUNCTION(spdif), 1052*4882a593Smuzhiyun }; 1053*4882a593Smuzhiyun 1054*4882a593Smuzhiyun static struct meson_pmx_func meson8_aobus_functions[] = { 1055*4882a593Smuzhiyun FUNCTION(gpio_aobus), 1056*4882a593Smuzhiyun FUNCTION(uart_ao), 1057*4882a593Smuzhiyun FUNCTION(remote), 1058*4882a593Smuzhiyun FUNCTION(i2c_slave_ao), 1059*4882a593Smuzhiyun FUNCTION(uart_ao_b), 1060*4882a593Smuzhiyun FUNCTION(i2c_mst_ao), 1061*4882a593Smuzhiyun FUNCTION(pwm_f_ao), 1062*4882a593Smuzhiyun FUNCTION(i2s_ao), 1063*4882a593Smuzhiyun FUNCTION(hdmi_cec_ao), 1064*4882a593Smuzhiyun }; 1065*4882a593Smuzhiyun 1066*4882a593Smuzhiyun static struct meson_bank meson8_cbus_banks[] = { 1067*4882a593Smuzhiyun /* name first last irq pullen pull dir out in */ 1068*4882a593Smuzhiyun BANK("X", GPIOX_0, GPIOX_21, 112, 133, 4, 0, 4, 0, 0, 0, 1, 0, 2, 0), 1069*4882a593Smuzhiyun BANK("Y", GPIOY_0, GPIOY_16, 95, 111, 3, 0, 3, 0, 3, 0, 4, 0, 5, 0), 1070*4882a593Smuzhiyun BANK("DV", GPIODV_0, GPIODV_29, 65, 94, 0, 0, 0, 0, 7, 0, 8, 0, 9, 0), 1071*4882a593Smuzhiyun BANK("H", GPIOH_0, GPIOH_9, 29, 38, 1, 16, 1, 16, 9, 19, 10, 19, 11, 19), 1072*4882a593Smuzhiyun BANK("Z", GPIOZ_0, GPIOZ_14, 14, 28, 1, 0, 1, 0, 3, 17, 4, 17, 5, 17), 1073*4882a593Smuzhiyun BANK("CARD", CARD_0, CARD_6, 58, 64, 2, 20, 2, 20, 0, 22, 1, 22, 2, 22), 1074*4882a593Smuzhiyun BANK("BOOT", BOOT_0, BOOT_18, 39, 57, 2, 0, 2, 0, 9, 0, 10, 0, 11, 0), 1075*4882a593Smuzhiyun }; 1076*4882a593Smuzhiyun 1077*4882a593Smuzhiyun static struct meson_bank meson8_aobus_banks[] = { 1078*4882a593Smuzhiyun /* name first last irq pullen pull dir out in */ 1079*4882a593Smuzhiyun BANK("AO", GPIOAO_0, GPIO_TEST_N, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), 1080*4882a593Smuzhiyun }; 1081*4882a593Smuzhiyun 1082*4882a593Smuzhiyun static struct meson_pinctrl_data meson8_cbus_pinctrl_data = { 1083*4882a593Smuzhiyun .name = "cbus-banks", 1084*4882a593Smuzhiyun .pins = meson8_cbus_pins, 1085*4882a593Smuzhiyun .groups = meson8_cbus_groups, 1086*4882a593Smuzhiyun .funcs = meson8_cbus_functions, 1087*4882a593Smuzhiyun .banks = meson8_cbus_banks, 1088*4882a593Smuzhiyun .num_pins = ARRAY_SIZE(meson8_cbus_pins), 1089*4882a593Smuzhiyun .num_groups = ARRAY_SIZE(meson8_cbus_groups), 1090*4882a593Smuzhiyun .num_funcs = ARRAY_SIZE(meson8_cbus_functions), 1091*4882a593Smuzhiyun .num_banks = ARRAY_SIZE(meson8_cbus_banks), 1092*4882a593Smuzhiyun .pmx_ops = &meson8_pmx_ops, 1093*4882a593Smuzhiyun }; 1094*4882a593Smuzhiyun 1095*4882a593Smuzhiyun static struct meson_pinctrl_data meson8_aobus_pinctrl_data = { 1096*4882a593Smuzhiyun .name = "ao-bank", 1097*4882a593Smuzhiyun .pins = meson8_aobus_pins, 1098*4882a593Smuzhiyun .groups = meson8_aobus_groups, 1099*4882a593Smuzhiyun .funcs = meson8_aobus_functions, 1100*4882a593Smuzhiyun .banks = meson8_aobus_banks, 1101*4882a593Smuzhiyun .num_pins = ARRAY_SIZE(meson8_aobus_pins), 1102*4882a593Smuzhiyun .num_groups = ARRAY_SIZE(meson8_aobus_groups), 1103*4882a593Smuzhiyun .num_funcs = ARRAY_SIZE(meson8_aobus_functions), 1104*4882a593Smuzhiyun .num_banks = ARRAY_SIZE(meson8_aobus_banks), 1105*4882a593Smuzhiyun .pmx_ops = &meson8_pmx_ops, 1106*4882a593Smuzhiyun .parse_dt = &meson8_aobus_parse_dt_extra, 1107*4882a593Smuzhiyun }; 1108*4882a593Smuzhiyun 1109*4882a593Smuzhiyun static const struct of_device_id meson8_pinctrl_dt_match[] = { 1110*4882a593Smuzhiyun { 1111*4882a593Smuzhiyun .compatible = "amlogic,meson8-cbus-pinctrl", 1112*4882a593Smuzhiyun .data = &meson8_cbus_pinctrl_data, 1113*4882a593Smuzhiyun }, 1114*4882a593Smuzhiyun { 1115*4882a593Smuzhiyun .compatible = "amlogic,meson8-aobus-pinctrl", 1116*4882a593Smuzhiyun .data = &meson8_aobus_pinctrl_data, 1117*4882a593Smuzhiyun }, 1118*4882a593Smuzhiyun { 1119*4882a593Smuzhiyun .compatible = "amlogic,meson8m2-cbus-pinctrl", 1120*4882a593Smuzhiyun .data = &meson8_cbus_pinctrl_data, 1121*4882a593Smuzhiyun }, 1122*4882a593Smuzhiyun { 1123*4882a593Smuzhiyun .compatible = "amlogic,meson8m2-aobus-pinctrl", 1124*4882a593Smuzhiyun .data = &meson8_aobus_pinctrl_data, 1125*4882a593Smuzhiyun }, 1126*4882a593Smuzhiyun { }, 1127*4882a593Smuzhiyun }; 1128*4882a593Smuzhiyun 1129*4882a593Smuzhiyun static struct platform_driver meson8_pinctrl_driver = { 1130*4882a593Smuzhiyun .probe = meson_pinctrl_probe, 1131*4882a593Smuzhiyun .driver = { 1132*4882a593Smuzhiyun .name = "meson8-pinctrl", 1133*4882a593Smuzhiyun .of_match_table = meson8_pinctrl_dt_match, 1134*4882a593Smuzhiyun }, 1135*4882a593Smuzhiyun }; 1136*4882a593Smuzhiyun builtin_platform_driver(meson8_pinctrl_driver); 1137