1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * First generation of pinmux driver for Amlogic Meson SoCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
6*4882a593Smuzhiyun * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun /* For this first generation of pinctrl driver every pinmux group can be
10*4882a593Smuzhiyun * enabled by a specific bit in the first register range. When all groups for
11*4882a593Smuzhiyun * a given pin are disabled the pin acts as a GPIO.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun #include <linux/device.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
16*4882a593Smuzhiyun #include <linux/pinctrl/pinmux.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "pinctrl-meson.h"
19*4882a593Smuzhiyun #include "pinctrl-meson8-pmx.h"
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun /**
22*4882a593Smuzhiyun * meson8_pmx_disable_other_groups() - disable other groups using a given pin
23*4882a593Smuzhiyun *
24*4882a593Smuzhiyun * @pc: meson pin controller device
25*4882a593Smuzhiyun * @pin: number of the pin
26*4882a593Smuzhiyun * @sel_group: index of the selected group, or -1 if none
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * The function disables all pinmux groups using a pin except the
29*4882a593Smuzhiyun * selected one. If @sel_group is -1 all groups are disabled, leaving
30*4882a593Smuzhiyun * the pin in GPIO mode.
31*4882a593Smuzhiyun */
meson8_pmx_disable_other_groups(struct meson_pinctrl * pc,unsigned int pin,int sel_group)32*4882a593Smuzhiyun static void meson8_pmx_disable_other_groups(struct meson_pinctrl *pc,
33*4882a593Smuzhiyun unsigned int pin, int sel_group)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun struct meson_pmx_group *group;
36*4882a593Smuzhiyun struct meson8_pmx_data *pmx_data;
37*4882a593Smuzhiyun int i, j;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun for (i = 0; i < pc->data->num_groups; i++) {
40*4882a593Smuzhiyun group = &pc->data->groups[i];
41*4882a593Smuzhiyun pmx_data = (struct meson8_pmx_data *)group->data;
42*4882a593Smuzhiyun if (pmx_data->is_gpio || i == sel_group)
43*4882a593Smuzhiyun continue;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun for (j = 0; j < group->num_pins; j++) {
46*4882a593Smuzhiyun if (group->pins[j] == pin) {
47*4882a593Smuzhiyun /* We have found a group using the pin */
48*4882a593Smuzhiyun regmap_update_bits(pc->reg_mux,
49*4882a593Smuzhiyun pmx_data->reg * 4,
50*4882a593Smuzhiyun BIT(pmx_data->bit), 0);
51*4882a593Smuzhiyun }
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun }
54*4882a593Smuzhiyun }
55*4882a593Smuzhiyun
meson8_pmx_set_mux(struct pinctrl_dev * pcdev,unsigned func_num,unsigned group_num)56*4882a593Smuzhiyun static int meson8_pmx_set_mux(struct pinctrl_dev *pcdev, unsigned func_num,
57*4882a593Smuzhiyun unsigned group_num)
58*4882a593Smuzhiyun {
59*4882a593Smuzhiyun struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
60*4882a593Smuzhiyun struct meson_pmx_func *func = &pc->data->funcs[func_num];
61*4882a593Smuzhiyun struct meson_pmx_group *group = &pc->data->groups[group_num];
62*4882a593Smuzhiyun struct meson8_pmx_data *pmx_data =
63*4882a593Smuzhiyun (struct meson8_pmx_data *)group->data;
64*4882a593Smuzhiyun int i, ret = 0;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
67*4882a593Smuzhiyun group->name);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * Disable groups using the same pin.
71*4882a593Smuzhiyun * The selected group is not disabled to avoid glitches.
72*4882a593Smuzhiyun */
73*4882a593Smuzhiyun for (i = 0; i < group->num_pins; i++)
74*4882a593Smuzhiyun meson8_pmx_disable_other_groups(pc, group->pins[i], group_num);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun /* Function 0 (GPIO) doesn't need any additional setting */
77*4882a593Smuzhiyun if (func_num)
78*4882a593Smuzhiyun ret = regmap_update_bits(pc->reg_mux, pmx_data->reg * 4,
79*4882a593Smuzhiyun BIT(pmx_data->bit),
80*4882a593Smuzhiyun BIT(pmx_data->bit));
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun return ret;
83*4882a593Smuzhiyun }
84*4882a593Smuzhiyun
meson8_pmx_request_gpio(struct pinctrl_dev * pcdev,struct pinctrl_gpio_range * range,unsigned offset)85*4882a593Smuzhiyun static int meson8_pmx_request_gpio(struct pinctrl_dev *pcdev,
86*4882a593Smuzhiyun struct pinctrl_gpio_range *range,
87*4882a593Smuzhiyun unsigned offset)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun meson8_pmx_disable_other_groups(pc, offset, -1);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun return 0;
94*4882a593Smuzhiyun }
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun const struct pinmux_ops meson8_pmx_ops = {
97*4882a593Smuzhiyun .set_mux = meson8_pmx_set_mux,
98*4882a593Smuzhiyun .get_functions_count = meson_pmx_get_funcs_count,
99*4882a593Smuzhiyun .get_function_name = meson_pmx_get_func_name,
100*4882a593Smuzhiyun .get_function_groups = meson_pmx_get_groups,
101*4882a593Smuzhiyun .gpio_request_enable = meson8_pmx_request_gpio,
102*4882a593Smuzhiyun };
103*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(meson8_pmx_ops);
104*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
105