1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Pin controller and GPIO driver for Amlogic Meson SoCs 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/gpio/driver.h> 9*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h> 10*4882a593Smuzhiyun #include <linux/platform_device.h> 11*4882a593Smuzhiyun #include <linux/regmap.h> 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun #include <linux/module.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct meson_pinctrl; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /** 18*4882a593Smuzhiyun * struct meson_pmx_group - a pinmux group 19*4882a593Smuzhiyun * 20*4882a593Smuzhiyun * @name: group name 21*4882a593Smuzhiyun * @pins: pins in the group 22*4882a593Smuzhiyun * @num_pins: number of pins in the group 23*4882a593Smuzhiyun * @is_gpio: whether the group is a single GPIO group 24*4882a593Smuzhiyun * @reg: register offset for the group in the domain mux registers 25*4882a593Smuzhiyun * @bit bit index enabling the group 26*4882a593Smuzhiyun * @domain: index of the domain this group belongs to 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun struct meson_pmx_group { 29*4882a593Smuzhiyun const char *name; 30*4882a593Smuzhiyun const unsigned int *pins; 31*4882a593Smuzhiyun unsigned int num_pins; 32*4882a593Smuzhiyun const void *data; 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /** 36*4882a593Smuzhiyun * struct meson_pmx_func - a pinmux function 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * @name: function name 39*4882a593Smuzhiyun * @groups: groups in the function 40*4882a593Smuzhiyun * @num_groups: number of groups in the function 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun struct meson_pmx_func { 43*4882a593Smuzhiyun const char *name; 44*4882a593Smuzhiyun const char * const *groups; 45*4882a593Smuzhiyun unsigned int num_groups; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun /** 49*4882a593Smuzhiyun * struct meson_reg_desc - a register descriptor 50*4882a593Smuzhiyun * 51*4882a593Smuzhiyun * @reg: register offset in the regmap 52*4882a593Smuzhiyun * @bit: bit index in register 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * The structure describes the information needed to control pull, 55*4882a593Smuzhiyun * pull-enable, direction, etc. for a single pin 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun struct meson_reg_desc { 58*4882a593Smuzhiyun unsigned int reg; 59*4882a593Smuzhiyun unsigned int bit; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /** 63*4882a593Smuzhiyun * enum meson_reg_type - type of registers encoded in @meson_reg_desc 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun enum meson_reg_type { 66*4882a593Smuzhiyun REG_PULLEN, 67*4882a593Smuzhiyun REG_PULL, 68*4882a593Smuzhiyun REG_DIR, 69*4882a593Smuzhiyun REG_OUT, 70*4882a593Smuzhiyun REG_IN, 71*4882a593Smuzhiyun REG_DS, 72*4882a593Smuzhiyun NUM_REG, 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /** 76*4882a593Smuzhiyun * enum meson_pinconf_drv - value of drive-strength supported 77*4882a593Smuzhiyun */ 78*4882a593Smuzhiyun enum meson_pinconf_drv { 79*4882a593Smuzhiyun MESON_PINCONF_DRV_500UA, 80*4882a593Smuzhiyun MESON_PINCONF_DRV_2500UA, 81*4882a593Smuzhiyun MESON_PINCONF_DRV_3000UA, 82*4882a593Smuzhiyun MESON_PINCONF_DRV_4000UA, 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /** 86*4882a593Smuzhiyun * struct meson bank 87*4882a593Smuzhiyun * 88*4882a593Smuzhiyun * @name: bank name 89*4882a593Smuzhiyun * @first: first pin of the bank 90*4882a593Smuzhiyun * @last: last pin of the bank 91*4882a593Smuzhiyun * @irq: hwirq base number of the bank 92*4882a593Smuzhiyun * @regs: array of register descriptors 93*4882a593Smuzhiyun * 94*4882a593Smuzhiyun * A bank represents a set of pins controlled by a contiguous set of 95*4882a593Smuzhiyun * bits in the domain registers. The structure specifies which bits in 96*4882a593Smuzhiyun * the regmap control the different functionalities. Each member of 97*4882a593Smuzhiyun * the @regs array refers to the first pin of the bank. 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun struct meson_bank { 100*4882a593Smuzhiyun const char *name; 101*4882a593Smuzhiyun unsigned int first; 102*4882a593Smuzhiyun unsigned int last; 103*4882a593Smuzhiyun int irq_first; 104*4882a593Smuzhiyun int irq_last; 105*4882a593Smuzhiyun struct meson_reg_desc regs[NUM_REG]; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun struct meson_pinctrl_data { 109*4882a593Smuzhiyun const char *name; 110*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins; 111*4882a593Smuzhiyun struct meson_pmx_group *groups; 112*4882a593Smuzhiyun struct meson_pmx_func *funcs; 113*4882a593Smuzhiyun unsigned int num_pins; 114*4882a593Smuzhiyun unsigned int num_groups; 115*4882a593Smuzhiyun unsigned int num_funcs; 116*4882a593Smuzhiyun struct meson_bank *banks; 117*4882a593Smuzhiyun unsigned int num_banks; 118*4882a593Smuzhiyun const struct pinmux_ops *pmx_ops; 119*4882a593Smuzhiyun void *pmx_data; 120*4882a593Smuzhiyun int (*parse_dt)(struct meson_pinctrl *pc); 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct meson_pinctrl { 124*4882a593Smuzhiyun struct device *dev; 125*4882a593Smuzhiyun struct pinctrl_dev *pcdev; 126*4882a593Smuzhiyun struct pinctrl_desc desc; 127*4882a593Smuzhiyun struct meson_pinctrl_data *data; 128*4882a593Smuzhiyun struct regmap *reg_mux; 129*4882a593Smuzhiyun struct regmap *reg_pullen; 130*4882a593Smuzhiyun struct regmap *reg_pull; 131*4882a593Smuzhiyun struct regmap *reg_gpio; 132*4882a593Smuzhiyun struct regmap *reg_ds; 133*4882a593Smuzhiyun struct gpio_chip chip; 134*4882a593Smuzhiyun struct device_node *of_node; 135*4882a593Smuzhiyun }; 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define FUNCTION(fn) \ 138*4882a593Smuzhiyun { \ 139*4882a593Smuzhiyun .name = #fn, \ 140*4882a593Smuzhiyun .groups = fn ## _groups, \ 141*4882a593Smuzhiyun .num_groups = ARRAY_SIZE(fn ## _groups), \ 142*4882a593Smuzhiyun } 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, \ 145*4882a593Smuzhiyun dsr, dsb) \ 146*4882a593Smuzhiyun { \ 147*4882a593Smuzhiyun .name = n, \ 148*4882a593Smuzhiyun .first = f, \ 149*4882a593Smuzhiyun .last = l, \ 150*4882a593Smuzhiyun .irq_first = fi, \ 151*4882a593Smuzhiyun .irq_last = li, \ 152*4882a593Smuzhiyun .regs = { \ 153*4882a593Smuzhiyun [REG_PULLEN] = { per, peb }, \ 154*4882a593Smuzhiyun [REG_PULL] = { pr, pb }, \ 155*4882a593Smuzhiyun [REG_DIR] = { dr, db }, \ 156*4882a593Smuzhiyun [REG_OUT] = { or, ob }, \ 157*4882a593Smuzhiyun [REG_IN] = { ir, ib }, \ 158*4882a593Smuzhiyun [REG_DS] = { dsr, dsb }, \ 159*4882a593Smuzhiyun }, \ 160*4882a593Smuzhiyun } 161*4882a593Smuzhiyun 162*4882a593Smuzhiyun #define BANK(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib) \ 163*4882a593Smuzhiyun BANK_DS(n, f, l, fi, li, per, peb, pr, pb, dr, db, or, ob, ir, ib, 0, 0) 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun #define MESON_PIN(x) PINCTRL_PIN(x, #x) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun /* Common pmx functions */ 168*4882a593Smuzhiyun int meson_pmx_get_funcs_count(struct pinctrl_dev *pcdev); 169*4882a593Smuzhiyun const char *meson_pmx_get_func_name(struct pinctrl_dev *pcdev, 170*4882a593Smuzhiyun unsigned selector); 171*4882a593Smuzhiyun int meson_pmx_get_groups(struct pinctrl_dev *pcdev, 172*4882a593Smuzhiyun unsigned selector, 173*4882a593Smuzhiyun const char * const **groups, 174*4882a593Smuzhiyun unsigned * const num_groups); 175*4882a593Smuzhiyun 176*4882a593Smuzhiyun /* Common probe function */ 177*4882a593Smuzhiyun int meson_pinctrl_probe(struct platform_device *pdev); 178*4882a593Smuzhiyun /* Common ao groups extra dt parse function for SoCs before g12a */ 179*4882a593Smuzhiyun int meson8_aobus_parse_dt_extra(struct meson_pinctrl *pc); 180*4882a593Smuzhiyun /* Common extra dt parse function for SoCs like A1 */ 181*4882a593Smuzhiyun int meson_a1_parse_dt_extra(struct meson_pinctrl *pc); 182