1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Pin controller and GPIO driver for Amlogic Meson GXBB. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Endless Mobile, Inc. 6*4882a593Smuzhiyun * Author: Carlo Caione <carlo@endlessm.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <dt-bindings/gpio/meson-gxbb-gpio.h> 10*4882a593Smuzhiyun #include "pinctrl-meson.h" 11*4882a593Smuzhiyun #include "pinctrl-meson8-pmx.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = { 14*4882a593Smuzhiyun MESON_PIN(GPIOZ_0), 15*4882a593Smuzhiyun MESON_PIN(GPIOZ_1), 16*4882a593Smuzhiyun MESON_PIN(GPIOZ_2), 17*4882a593Smuzhiyun MESON_PIN(GPIOZ_3), 18*4882a593Smuzhiyun MESON_PIN(GPIOZ_4), 19*4882a593Smuzhiyun MESON_PIN(GPIOZ_5), 20*4882a593Smuzhiyun MESON_PIN(GPIOZ_6), 21*4882a593Smuzhiyun MESON_PIN(GPIOZ_7), 22*4882a593Smuzhiyun MESON_PIN(GPIOZ_8), 23*4882a593Smuzhiyun MESON_PIN(GPIOZ_9), 24*4882a593Smuzhiyun MESON_PIN(GPIOZ_10), 25*4882a593Smuzhiyun MESON_PIN(GPIOZ_11), 26*4882a593Smuzhiyun MESON_PIN(GPIOZ_12), 27*4882a593Smuzhiyun MESON_PIN(GPIOZ_13), 28*4882a593Smuzhiyun MESON_PIN(GPIOZ_14), 29*4882a593Smuzhiyun MESON_PIN(GPIOZ_15), 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun MESON_PIN(GPIOH_0), 32*4882a593Smuzhiyun MESON_PIN(GPIOH_1), 33*4882a593Smuzhiyun MESON_PIN(GPIOH_2), 34*4882a593Smuzhiyun MESON_PIN(GPIOH_3), 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun MESON_PIN(BOOT_0), 37*4882a593Smuzhiyun MESON_PIN(BOOT_1), 38*4882a593Smuzhiyun MESON_PIN(BOOT_2), 39*4882a593Smuzhiyun MESON_PIN(BOOT_3), 40*4882a593Smuzhiyun MESON_PIN(BOOT_4), 41*4882a593Smuzhiyun MESON_PIN(BOOT_5), 42*4882a593Smuzhiyun MESON_PIN(BOOT_6), 43*4882a593Smuzhiyun MESON_PIN(BOOT_7), 44*4882a593Smuzhiyun MESON_PIN(BOOT_8), 45*4882a593Smuzhiyun MESON_PIN(BOOT_9), 46*4882a593Smuzhiyun MESON_PIN(BOOT_10), 47*4882a593Smuzhiyun MESON_PIN(BOOT_11), 48*4882a593Smuzhiyun MESON_PIN(BOOT_12), 49*4882a593Smuzhiyun MESON_PIN(BOOT_13), 50*4882a593Smuzhiyun MESON_PIN(BOOT_14), 51*4882a593Smuzhiyun MESON_PIN(BOOT_15), 52*4882a593Smuzhiyun MESON_PIN(BOOT_16), 53*4882a593Smuzhiyun MESON_PIN(BOOT_17), 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun MESON_PIN(CARD_0), 56*4882a593Smuzhiyun MESON_PIN(CARD_1), 57*4882a593Smuzhiyun MESON_PIN(CARD_2), 58*4882a593Smuzhiyun MESON_PIN(CARD_3), 59*4882a593Smuzhiyun MESON_PIN(CARD_4), 60*4882a593Smuzhiyun MESON_PIN(CARD_5), 61*4882a593Smuzhiyun MESON_PIN(CARD_6), 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun MESON_PIN(GPIODV_0), 64*4882a593Smuzhiyun MESON_PIN(GPIODV_1), 65*4882a593Smuzhiyun MESON_PIN(GPIODV_2), 66*4882a593Smuzhiyun MESON_PIN(GPIODV_3), 67*4882a593Smuzhiyun MESON_PIN(GPIODV_4), 68*4882a593Smuzhiyun MESON_PIN(GPIODV_5), 69*4882a593Smuzhiyun MESON_PIN(GPIODV_6), 70*4882a593Smuzhiyun MESON_PIN(GPIODV_7), 71*4882a593Smuzhiyun MESON_PIN(GPIODV_8), 72*4882a593Smuzhiyun MESON_PIN(GPIODV_9), 73*4882a593Smuzhiyun MESON_PIN(GPIODV_10), 74*4882a593Smuzhiyun MESON_PIN(GPIODV_11), 75*4882a593Smuzhiyun MESON_PIN(GPIODV_12), 76*4882a593Smuzhiyun MESON_PIN(GPIODV_13), 77*4882a593Smuzhiyun MESON_PIN(GPIODV_14), 78*4882a593Smuzhiyun MESON_PIN(GPIODV_15), 79*4882a593Smuzhiyun MESON_PIN(GPIODV_16), 80*4882a593Smuzhiyun MESON_PIN(GPIODV_17), 81*4882a593Smuzhiyun MESON_PIN(GPIODV_18), 82*4882a593Smuzhiyun MESON_PIN(GPIODV_19), 83*4882a593Smuzhiyun MESON_PIN(GPIODV_20), 84*4882a593Smuzhiyun MESON_PIN(GPIODV_21), 85*4882a593Smuzhiyun MESON_PIN(GPIODV_22), 86*4882a593Smuzhiyun MESON_PIN(GPIODV_23), 87*4882a593Smuzhiyun MESON_PIN(GPIODV_24), 88*4882a593Smuzhiyun MESON_PIN(GPIODV_25), 89*4882a593Smuzhiyun MESON_PIN(GPIODV_26), 90*4882a593Smuzhiyun MESON_PIN(GPIODV_27), 91*4882a593Smuzhiyun MESON_PIN(GPIODV_28), 92*4882a593Smuzhiyun MESON_PIN(GPIODV_29), 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun MESON_PIN(GPIOY_0), 95*4882a593Smuzhiyun MESON_PIN(GPIOY_1), 96*4882a593Smuzhiyun MESON_PIN(GPIOY_2), 97*4882a593Smuzhiyun MESON_PIN(GPIOY_3), 98*4882a593Smuzhiyun MESON_PIN(GPIOY_4), 99*4882a593Smuzhiyun MESON_PIN(GPIOY_5), 100*4882a593Smuzhiyun MESON_PIN(GPIOY_6), 101*4882a593Smuzhiyun MESON_PIN(GPIOY_7), 102*4882a593Smuzhiyun MESON_PIN(GPIOY_8), 103*4882a593Smuzhiyun MESON_PIN(GPIOY_9), 104*4882a593Smuzhiyun MESON_PIN(GPIOY_10), 105*4882a593Smuzhiyun MESON_PIN(GPIOY_11), 106*4882a593Smuzhiyun MESON_PIN(GPIOY_12), 107*4882a593Smuzhiyun MESON_PIN(GPIOY_13), 108*4882a593Smuzhiyun MESON_PIN(GPIOY_14), 109*4882a593Smuzhiyun MESON_PIN(GPIOY_15), 110*4882a593Smuzhiyun MESON_PIN(GPIOY_16), 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun MESON_PIN(GPIOX_0), 113*4882a593Smuzhiyun MESON_PIN(GPIOX_1), 114*4882a593Smuzhiyun MESON_PIN(GPIOX_2), 115*4882a593Smuzhiyun MESON_PIN(GPIOX_3), 116*4882a593Smuzhiyun MESON_PIN(GPIOX_4), 117*4882a593Smuzhiyun MESON_PIN(GPIOX_5), 118*4882a593Smuzhiyun MESON_PIN(GPIOX_6), 119*4882a593Smuzhiyun MESON_PIN(GPIOX_7), 120*4882a593Smuzhiyun MESON_PIN(GPIOX_8), 121*4882a593Smuzhiyun MESON_PIN(GPIOX_9), 122*4882a593Smuzhiyun MESON_PIN(GPIOX_10), 123*4882a593Smuzhiyun MESON_PIN(GPIOX_11), 124*4882a593Smuzhiyun MESON_PIN(GPIOX_12), 125*4882a593Smuzhiyun MESON_PIN(GPIOX_13), 126*4882a593Smuzhiyun MESON_PIN(GPIOX_14), 127*4882a593Smuzhiyun MESON_PIN(GPIOX_15), 128*4882a593Smuzhiyun MESON_PIN(GPIOX_16), 129*4882a593Smuzhiyun MESON_PIN(GPIOX_17), 130*4882a593Smuzhiyun MESON_PIN(GPIOX_18), 131*4882a593Smuzhiyun MESON_PIN(GPIOX_19), 132*4882a593Smuzhiyun MESON_PIN(GPIOX_20), 133*4882a593Smuzhiyun MESON_PIN(GPIOX_21), 134*4882a593Smuzhiyun MESON_PIN(GPIOX_22), 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun MESON_PIN(GPIOCLK_0), 137*4882a593Smuzhiyun MESON_PIN(GPIOCLK_1), 138*4882a593Smuzhiyun MESON_PIN(GPIOCLK_2), 139*4882a593Smuzhiyun MESON_PIN(GPIOCLK_3), 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun static const unsigned int emmc_nand_d07_pins[] = { 143*4882a593Smuzhiyun BOOT_0, BOOT_1, BOOT_2, BOOT_3, BOOT_4, BOOT_5, BOOT_6, BOOT_7, 144*4882a593Smuzhiyun }; 145*4882a593Smuzhiyun static const unsigned int emmc_clk_pins[] = { BOOT_8 }; 146*4882a593Smuzhiyun static const unsigned int emmc_cmd_pins[] = { BOOT_10 }; 147*4882a593Smuzhiyun static const unsigned int emmc_ds_pins[] = { BOOT_15 }; 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun static const unsigned int nor_d_pins[] = { BOOT_11 }; 150*4882a593Smuzhiyun static const unsigned int nor_q_pins[] = { BOOT_12 }; 151*4882a593Smuzhiyun static const unsigned int nor_c_pins[] = { BOOT_13 }; 152*4882a593Smuzhiyun static const unsigned int nor_cs_pins[] = { BOOT_15 }; 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun static const unsigned int spi_sclk_pins[] = { GPIOZ_6 }; 155*4882a593Smuzhiyun static const unsigned int spi_ss0_pins[] = { GPIOZ_7 }; 156*4882a593Smuzhiyun static const unsigned int spi_miso_pins[] = { GPIOZ_12 }; 157*4882a593Smuzhiyun static const unsigned int spi_mosi_pins[] = { GPIOZ_13 }; 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun static const unsigned int sdcard_d0_pins[] = { CARD_1 }; 160*4882a593Smuzhiyun static const unsigned int sdcard_d1_pins[] = { CARD_0 }; 161*4882a593Smuzhiyun static const unsigned int sdcard_d2_pins[] = { CARD_5 }; 162*4882a593Smuzhiyun static const unsigned int sdcard_d3_pins[] = { CARD_4 }; 163*4882a593Smuzhiyun static const unsigned int sdcard_cmd_pins[] = { CARD_3 }; 164*4882a593Smuzhiyun static const unsigned int sdcard_clk_pins[] = { CARD_2 }; 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun static const unsigned int sdio_d0_pins[] = { GPIOX_0 }; 167*4882a593Smuzhiyun static const unsigned int sdio_d1_pins[] = { GPIOX_1 }; 168*4882a593Smuzhiyun static const unsigned int sdio_d2_pins[] = { GPIOX_2 }; 169*4882a593Smuzhiyun static const unsigned int sdio_d3_pins[] = { GPIOX_3 }; 170*4882a593Smuzhiyun static const unsigned int sdio_cmd_pins[] = { GPIOX_4 }; 171*4882a593Smuzhiyun static const unsigned int sdio_clk_pins[] = { GPIOX_5 }; 172*4882a593Smuzhiyun static const unsigned int sdio_irq_pins[] = { GPIOX_7 }; 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun static const unsigned int nand_ce0_pins[] = { BOOT_8 }; 175*4882a593Smuzhiyun static const unsigned int nand_ce1_pins[] = { BOOT_9 }; 176*4882a593Smuzhiyun static const unsigned int nand_rb0_pins[] = { BOOT_10 }; 177*4882a593Smuzhiyun static const unsigned int nand_ale_pins[] = { BOOT_11 }; 178*4882a593Smuzhiyun static const unsigned int nand_cle_pins[] = { BOOT_12 }; 179*4882a593Smuzhiyun static const unsigned int nand_wen_clk_pins[] = { BOOT_13 }; 180*4882a593Smuzhiyun static const unsigned int nand_ren_wr_pins[] = { BOOT_14 }; 181*4882a593Smuzhiyun static const unsigned int nand_dqs_pins[] = { BOOT_15 }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun static const unsigned int uart_tx_a_pins[] = { GPIOX_12 }; 184*4882a593Smuzhiyun static const unsigned int uart_rx_a_pins[] = { GPIOX_13 }; 185*4882a593Smuzhiyun static const unsigned int uart_cts_a_pins[] = { GPIOX_14 }; 186*4882a593Smuzhiyun static const unsigned int uart_rts_a_pins[] = { GPIOX_15 }; 187*4882a593Smuzhiyun 188*4882a593Smuzhiyun static const unsigned int uart_tx_b_pins[] = { GPIODV_24 }; 189*4882a593Smuzhiyun static const unsigned int uart_rx_b_pins[] = { GPIODV_25 }; 190*4882a593Smuzhiyun static const unsigned int uart_cts_b_pins[] = { GPIODV_26 }; 191*4882a593Smuzhiyun static const unsigned int uart_rts_b_pins[] = { GPIODV_27 }; 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun static const unsigned int uart_tx_c_pins[] = { GPIOY_13 }; 194*4882a593Smuzhiyun static const unsigned int uart_rx_c_pins[] = { GPIOY_14 }; 195*4882a593Smuzhiyun static const unsigned int uart_cts_c_pins[] = { GPIOY_11 }; 196*4882a593Smuzhiyun static const unsigned int uart_rts_c_pins[] = { GPIOY_12 }; 197*4882a593Smuzhiyun 198*4882a593Smuzhiyun static const unsigned int i2c_sck_a_pins[] = { GPIODV_25 }; 199*4882a593Smuzhiyun static const unsigned int i2c_sda_a_pins[] = { GPIODV_24 }; 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun static const unsigned int i2c_sck_b_pins[] = { GPIODV_27 }; 202*4882a593Smuzhiyun static const unsigned int i2c_sda_b_pins[] = { GPIODV_26 }; 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun static const unsigned int i2c_sck_c_pins[] = { GPIODV_29 }; 205*4882a593Smuzhiyun static const unsigned int i2c_sda_c_pins[] = { GPIODV_28 }; 206*4882a593Smuzhiyun 207*4882a593Smuzhiyun static const unsigned int eth_mdio_pins[] = { GPIOZ_0 }; 208*4882a593Smuzhiyun static const unsigned int eth_mdc_pins[] = { GPIOZ_1 }; 209*4882a593Smuzhiyun static const unsigned int eth_clk_rx_clk_pins[] = { GPIOZ_2 }; 210*4882a593Smuzhiyun static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 }; 211*4882a593Smuzhiyun static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 }; 212*4882a593Smuzhiyun static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 }; 213*4882a593Smuzhiyun static const unsigned int eth_rxd2_pins[] = { GPIOZ_6 }; 214*4882a593Smuzhiyun static const unsigned int eth_rxd3_pins[] = { GPIOZ_7 }; 215*4882a593Smuzhiyun static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 }; 216*4882a593Smuzhiyun static const unsigned int eth_tx_en_pins[] = { GPIOZ_9 }; 217*4882a593Smuzhiyun static const unsigned int eth_txd0_pins[] = { GPIOZ_10 }; 218*4882a593Smuzhiyun static const unsigned int eth_txd1_pins[] = { GPIOZ_11 }; 219*4882a593Smuzhiyun static const unsigned int eth_txd2_pins[] = { GPIOZ_12 }; 220*4882a593Smuzhiyun static const unsigned int eth_txd3_pins[] = { GPIOZ_13 }; 221*4882a593Smuzhiyun 222*4882a593Smuzhiyun static const unsigned int pwm_a_x_pins[] = { GPIOX_6 }; 223*4882a593Smuzhiyun static const unsigned int pwm_a_y_pins[] = { GPIOY_16 }; 224*4882a593Smuzhiyun static const unsigned int pwm_b_pins[] = { GPIODV_29 }; 225*4882a593Smuzhiyun static const unsigned int pwm_d_pins[] = { GPIODV_28 }; 226*4882a593Smuzhiyun static const unsigned int pwm_e_pins[] = { GPIOX_19 }; 227*4882a593Smuzhiyun static const unsigned int pwm_f_x_pins[] = { GPIOX_7 }; 228*4882a593Smuzhiyun static const unsigned int pwm_f_y_pins[] = { GPIOY_15 }; 229*4882a593Smuzhiyun 230*4882a593Smuzhiyun static const unsigned int hdmi_hpd_pins[] = { GPIOH_0 }; 231*4882a593Smuzhiyun static const unsigned int hdmi_sda_pins[] = { GPIOH_1 }; 232*4882a593Smuzhiyun static const unsigned int hdmi_scl_pins[] = { GPIOH_2 }; 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun static const unsigned int tsin_a_d_valid_pins[] = { GPIOY_0 }; 235*4882a593Smuzhiyun static const unsigned int tsin_a_sop_pins[] = { GPIOY_1 }; 236*4882a593Smuzhiyun static const unsigned int tsin_a_clk_pins[] = { GPIOY_2 }; 237*4882a593Smuzhiyun static const unsigned int tsin_a_d0_pins[] = { GPIOY_3 }; 238*4882a593Smuzhiyun static const unsigned int tsin_a_dp_pins[] = { 239*4882a593Smuzhiyun GPIOY_4, GPIOY_5, GPIOY_6, GPIOY_7, GPIOY_8, GPIOY_9, GPIOY_10 240*4882a593Smuzhiyun }; 241*4882a593Smuzhiyun 242*4882a593Smuzhiyun static const unsigned int tsin_a_fail_pins[] = { GPIOY_11 }; 243*4882a593Smuzhiyun static const unsigned int i2s_out_ch23_y_pins[] = { GPIOY_8 }; 244*4882a593Smuzhiyun static const unsigned int i2s_out_ch45_y_pins[] = { GPIOY_9 }; 245*4882a593Smuzhiyun static const unsigned int i2s_out_ch67_y_pins[] = { GPIOY_10 }; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun static const unsigned int tsin_b_d_valid_pins[] = { GPIOX_6 }; 248*4882a593Smuzhiyun static const unsigned int tsin_b_sop_pins[] = { GPIOX_7 }; 249*4882a593Smuzhiyun static const unsigned int tsin_b_clk_pins[] = { GPIOX_8 }; 250*4882a593Smuzhiyun static const unsigned int tsin_b_d0_pins[] = { GPIOX_9 }; 251*4882a593Smuzhiyun 252*4882a593Smuzhiyun static const unsigned int spdif_out_y_pins[] = { GPIOY_12 }; 253*4882a593Smuzhiyun 254*4882a593Smuzhiyun static const unsigned int gen_clk_out_pins[] = { GPIOY_15 }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = { 257*4882a593Smuzhiyun MESON_PIN(GPIOAO_0), 258*4882a593Smuzhiyun MESON_PIN(GPIOAO_1), 259*4882a593Smuzhiyun MESON_PIN(GPIOAO_2), 260*4882a593Smuzhiyun MESON_PIN(GPIOAO_3), 261*4882a593Smuzhiyun MESON_PIN(GPIOAO_4), 262*4882a593Smuzhiyun MESON_PIN(GPIOAO_5), 263*4882a593Smuzhiyun MESON_PIN(GPIOAO_6), 264*4882a593Smuzhiyun MESON_PIN(GPIOAO_7), 265*4882a593Smuzhiyun MESON_PIN(GPIOAO_8), 266*4882a593Smuzhiyun MESON_PIN(GPIOAO_9), 267*4882a593Smuzhiyun MESON_PIN(GPIOAO_10), 268*4882a593Smuzhiyun MESON_PIN(GPIOAO_11), 269*4882a593Smuzhiyun MESON_PIN(GPIOAO_12), 270*4882a593Smuzhiyun MESON_PIN(GPIOAO_13), 271*4882a593Smuzhiyun 272*4882a593Smuzhiyun MESON_PIN(GPIO_TEST_N), 273*4882a593Smuzhiyun }; 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun static const unsigned int uart_tx_ao_a_pins[] = { GPIOAO_0 }; 276*4882a593Smuzhiyun static const unsigned int uart_rx_ao_a_pins[] = { GPIOAO_1 }; 277*4882a593Smuzhiyun static const unsigned int uart_cts_ao_a_pins[] = { GPIOAO_2 }; 278*4882a593Smuzhiyun static const unsigned int uart_rts_ao_a_pins[] = { GPIOAO_3 }; 279*4882a593Smuzhiyun static const unsigned int uart_tx_ao_b_pins[] = { GPIOAO_4 }; 280*4882a593Smuzhiyun static const unsigned int uart_rx_ao_b_pins[] = { GPIOAO_5 }; 281*4882a593Smuzhiyun static const unsigned int uart_cts_ao_b_pins[] = { GPIOAO_2 }; 282*4882a593Smuzhiyun static const unsigned int uart_rts_ao_b_pins[] = { GPIOAO_3 }; 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun static const unsigned int i2c_sck_ao_pins[] = { GPIOAO_4 }; 285*4882a593Smuzhiyun static const unsigned int i2c_sda_ao_pins[] = { GPIOAO_5 }; 286*4882a593Smuzhiyun static const unsigned int i2c_slave_sck_ao_pins[] = {GPIOAO_4 }; 287*4882a593Smuzhiyun static const unsigned int i2c_slave_sda_ao_pins[] = {GPIOAO_5 }; 288*4882a593Smuzhiyun 289*4882a593Smuzhiyun static const unsigned int remote_input_ao_pins[] = { GPIOAO_7 }; 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun static const unsigned int pwm_ao_a_3_pins[] = { GPIOAO_3 }; 292*4882a593Smuzhiyun static const unsigned int pwm_ao_a_6_pins[] = { GPIOAO_6 }; 293*4882a593Smuzhiyun static const unsigned int pwm_ao_a_12_pins[] = { GPIOAO_12 }; 294*4882a593Smuzhiyun static const unsigned int pwm_ao_b_pins[] = { GPIOAO_13 }; 295*4882a593Smuzhiyun 296*4882a593Smuzhiyun static const unsigned int i2s_am_clk_pins[] = { GPIOAO_8 }; 297*4882a593Smuzhiyun static const unsigned int i2s_out_ao_clk_pins[] = { GPIOAO_9 }; 298*4882a593Smuzhiyun static const unsigned int i2s_out_lr_clk_pins[] = { GPIOAO_10 }; 299*4882a593Smuzhiyun static const unsigned int i2s_out_ch01_ao_pins[] = { GPIOAO_11 }; 300*4882a593Smuzhiyun static const unsigned int i2s_out_ch23_ao_pins[] = { GPIOAO_12 }; 301*4882a593Smuzhiyun static const unsigned int i2s_out_ch45_ao_pins[] = { GPIOAO_13 }; 302*4882a593Smuzhiyun static const unsigned int i2s_out_ch67_ao_pins[] = { GPIO_TEST_N }; 303*4882a593Smuzhiyun 304*4882a593Smuzhiyun static const unsigned int spdif_out_ao_6_pins[] = { GPIOAO_6 }; 305*4882a593Smuzhiyun static const unsigned int spdif_out_ao_13_pins[] = { GPIOAO_13 }; 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun static const unsigned int ao_cec_pins[] = { GPIOAO_12 }; 308*4882a593Smuzhiyun static const unsigned int ee_cec_pins[] = { GPIOAO_12 }; 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun static struct meson_pmx_group meson_gxbb_periphs_groups[] = { 311*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_0), 312*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_1), 313*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_2), 314*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_3), 315*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_4), 316*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_5), 317*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_6), 318*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_7), 319*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_8), 320*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_9), 321*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_10), 322*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_11), 323*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_12), 324*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_13), 325*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_14), 326*4882a593Smuzhiyun GPIO_GROUP(GPIOZ_15), 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun GPIO_GROUP(GPIOH_0), 329*4882a593Smuzhiyun GPIO_GROUP(GPIOH_1), 330*4882a593Smuzhiyun GPIO_GROUP(GPIOH_2), 331*4882a593Smuzhiyun GPIO_GROUP(GPIOH_3), 332*4882a593Smuzhiyun 333*4882a593Smuzhiyun GPIO_GROUP(BOOT_0), 334*4882a593Smuzhiyun GPIO_GROUP(BOOT_1), 335*4882a593Smuzhiyun GPIO_GROUP(BOOT_2), 336*4882a593Smuzhiyun GPIO_GROUP(BOOT_3), 337*4882a593Smuzhiyun GPIO_GROUP(BOOT_4), 338*4882a593Smuzhiyun GPIO_GROUP(BOOT_5), 339*4882a593Smuzhiyun GPIO_GROUP(BOOT_6), 340*4882a593Smuzhiyun GPIO_GROUP(BOOT_7), 341*4882a593Smuzhiyun GPIO_GROUP(BOOT_8), 342*4882a593Smuzhiyun GPIO_GROUP(BOOT_9), 343*4882a593Smuzhiyun GPIO_GROUP(BOOT_10), 344*4882a593Smuzhiyun GPIO_GROUP(BOOT_11), 345*4882a593Smuzhiyun GPIO_GROUP(BOOT_12), 346*4882a593Smuzhiyun GPIO_GROUP(BOOT_13), 347*4882a593Smuzhiyun GPIO_GROUP(BOOT_14), 348*4882a593Smuzhiyun GPIO_GROUP(BOOT_15), 349*4882a593Smuzhiyun GPIO_GROUP(BOOT_16), 350*4882a593Smuzhiyun GPIO_GROUP(BOOT_17), 351*4882a593Smuzhiyun 352*4882a593Smuzhiyun GPIO_GROUP(CARD_0), 353*4882a593Smuzhiyun GPIO_GROUP(CARD_1), 354*4882a593Smuzhiyun GPIO_GROUP(CARD_2), 355*4882a593Smuzhiyun GPIO_GROUP(CARD_3), 356*4882a593Smuzhiyun GPIO_GROUP(CARD_4), 357*4882a593Smuzhiyun GPIO_GROUP(CARD_5), 358*4882a593Smuzhiyun GPIO_GROUP(CARD_6), 359*4882a593Smuzhiyun 360*4882a593Smuzhiyun GPIO_GROUP(GPIODV_0), 361*4882a593Smuzhiyun GPIO_GROUP(GPIODV_1), 362*4882a593Smuzhiyun GPIO_GROUP(GPIODV_2), 363*4882a593Smuzhiyun GPIO_GROUP(GPIODV_3), 364*4882a593Smuzhiyun GPIO_GROUP(GPIODV_4), 365*4882a593Smuzhiyun GPIO_GROUP(GPIODV_5), 366*4882a593Smuzhiyun GPIO_GROUP(GPIODV_6), 367*4882a593Smuzhiyun GPIO_GROUP(GPIODV_7), 368*4882a593Smuzhiyun GPIO_GROUP(GPIODV_8), 369*4882a593Smuzhiyun GPIO_GROUP(GPIODV_9), 370*4882a593Smuzhiyun GPIO_GROUP(GPIODV_10), 371*4882a593Smuzhiyun GPIO_GROUP(GPIODV_11), 372*4882a593Smuzhiyun GPIO_GROUP(GPIODV_12), 373*4882a593Smuzhiyun GPIO_GROUP(GPIODV_13), 374*4882a593Smuzhiyun GPIO_GROUP(GPIODV_14), 375*4882a593Smuzhiyun GPIO_GROUP(GPIODV_15), 376*4882a593Smuzhiyun GPIO_GROUP(GPIODV_16), 377*4882a593Smuzhiyun GPIO_GROUP(GPIODV_17), 378*4882a593Smuzhiyun GPIO_GROUP(GPIODV_19), 379*4882a593Smuzhiyun GPIO_GROUP(GPIODV_20), 380*4882a593Smuzhiyun GPIO_GROUP(GPIODV_21), 381*4882a593Smuzhiyun GPIO_GROUP(GPIODV_22), 382*4882a593Smuzhiyun GPIO_GROUP(GPIODV_23), 383*4882a593Smuzhiyun GPIO_GROUP(GPIODV_24), 384*4882a593Smuzhiyun GPIO_GROUP(GPIODV_25), 385*4882a593Smuzhiyun GPIO_GROUP(GPIODV_26), 386*4882a593Smuzhiyun GPIO_GROUP(GPIODV_27), 387*4882a593Smuzhiyun GPIO_GROUP(GPIODV_28), 388*4882a593Smuzhiyun GPIO_GROUP(GPIODV_29), 389*4882a593Smuzhiyun 390*4882a593Smuzhiyun GPIO_GROUP(GPIOY_0), 391*4882a593Smuzhiyun GPIO_GROUP(GPIOY_1), 392*4882a593Smuzhiyun GPIO_GROUP(GPIOY_2), 393*4882a593Smuzhiyun GPIO_GROUP(GPIOY_3), 394*4882a593Smuzhiyun GPIO_GROUP(GPIOY_4), 395*4882a593Smuzhiyun GPIO_GROUP(GPIOY_5), 396*4882a593Smuzhiyun GPIO_GROUP(GPIOY_6), 397*4882a593Smuzhiyun GPIO_GROUP(GPIOY_7), 398*4882a593Smuzhiyun GPIO_GROUP(GPIOY_8), 399*4882a593Smuzhiyun GPIO_GROUP(GPIOY_9), 400*4882a593Smuzhiyun GPIO_GROUP(GPIOY_10), 401*4882a593Smuzhiyun GPIO_GROUP(GPIOY_11), 402*4882a593Smuzhiyun GPIO_GROUP(GPIOY_12), 403*4882a593Smuzhiyun GPIO_GROUP(GPIOY_13), 404*4882a593Smuzhiyun GPIO_GROUP(GPIOY_14), 405*4882a593Smuzhiyun GPIO_GROUP(GPIOY_15), 406*4882a593Smuzhiyun GPIO_GROUP(GPIOY_16), 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun GPIO_GROUP(GPIOX_0), 409*4882a593Smuzhiyun GPIO_GROUP(GPIOX_1), 410*4882a593Smuzhiyun GPIO_GROUP(GPIOX_2), 411*4882a593Smuzhiyun GPIO_GROUP(GPIOX_3), 412*4882a593Smuzhiyun GPIO_GROUP(GPIOX_4), 413*4882a593Smuzhiyun GPIO_GROUP(GPIOX_5), 414*4882a593Smuzhiyun GPIO_GROUP(GPIOX_6), 415*4882a593Smuzhiyun GPIO_GROUP(GPIOX_7), 416*4882a593Smuzhiyun GPIO_GROUP(GPIOX_8), 417*4882a593Smuzhiyun GPIO_GROUP(GPIOX_9), 418*4882a593Smuzhiyun GPIO_GROUP(GPIOX_10), 419*4882a593Smuzhiyun GPIO_GROUP(GPIOX_11), 420*4882a593Smuzhiyun GPIO_GROUP(GPIOX_12), 421*4882a593Smuzhiyun GPIO_GROUP(GPIOX_13), 422*4882a593Smuzhiyun GPIO_GROUP(GPIOX_14), 423*4882a593Smuzhiyun GPIO_GROUP(GPIOX_15), 424*4882a593Smuzhiyun GPIO_GROUP(GPIOX_16), 425*4882a593Smuzhiyun GPIO_GROUP(GPIOX_17), 426*4882a593Smuzhiyun GPIO_GROUP(GPIOX_18), 427*4882a593Smuzhiyun GPIO_GROUP(GPIOX_19), 428*4882a593Smuzhiyun GPIO_GROUP(GPIOX_20), 429*4882a593Smuzhiyun GPIO_GROUP(GPIOX_21), 430*4882a593Smuzhiyun GPIO_GROUP(GPIOX_22), 431*4882a593Smuzhiyun 432*4882a593Smuzhiyun GPIO_GROUP(GPIOCLK_0), 433*4882a593Smuzhiyun GPIO_GROUP(GPIOCLK_1), 434*4882a593Smuzhiyun GPIO_GROUP(GPIOCLK_2), 435*4882a593Smuzhiyun GPIO_GROUP(GPIOCLK_3), 436*4882a593Smuzhiyun 437*4882a593Smuzhiyun GPIO_GROUP(GPIO_TEST_N), 438*4882a593Smuzhiyun 439*4882a593Smuzhiyun /* Bank X */ 440*4882a593Smuzhiyun GROUP(sdio_d0, 8, 5), 441*4882a593Smuzhiyun GROUP(sdio_d1, 8, 4), 442*4882a593Smuzhiyun GROUP(sdio_d2, 8, 3), 443*4882a593Smuzhiyun GROUP(sdio_d3, 8, 2), 444*4882a593Smuzhiyun GROUP(sdio_cmd, 8, 1), 445*4882a593Smuzhiyun GROUP(sdio_clk, 8, 0), 446*4882a593Smuzhiyun GROUP(sdio_irq, 8, 11), 447*4882a593Smuzhiyun GROUP(uart_tx_a, 4, 13), 448*4882a593Smuzhiyun GROUP(uart_rx_a, 4, 12), 449*4882a593Smuzhiyun GROUP(uart_cts_a, 4, 11), 450*4882a593Smuzhiyun GROUP(uart_rts_a, 4, 10), 451*4882a593Smuzhiyun GROUP(pwm_a_x, 3, 17), 452*4882a593Smuzhiyun GROUP(pwm_e, 2, 30), 453*4882a593Smuzhiyun GROUP(pwm_f_x, 3, 18), 454*4882a593Smuzhiyun GROUP(tsin_b_d_valid, 3, 9), 455*4882a593Smuzhiyun GROUP(tsin_b_sop, 3, 8), 456*4882a593Smuzhiyun GROUP(tsin_b_clk, 3, 10), 457*4882a593Smuzhiyun GROUP(tsin_b_d0, 3, 7), 458*4882a593Smuzhiyun 459*4882a593Smuzhiyun /* Bank Y */ 460*4882a593Smuzhiyun GROUP(uart_cts_c, 1, 17), 461*4882a593Smuzhiyun GROUP(uart_rts_c, 1, 16), 462*4882a593Smuzhiyun GROUP(uart_tx_c, 1, 19), 463*4882a593Smuzhiyun GROUP(uart_rx_c, 1, 18), 464*4882a593Smuzhiyun GROUP(tsin_a_fail, 3, 3), 465*4882a593Smuzhiyun GROUP(tsin_a_d_valid, 3, 2), 466*4882a593Smuzhiyun GROUP(tsin_a_sop, 3, 1), 467*4882a593Smuzhiyun GROUP(tsin_a_clk, 3, 0), 468*4882a593Smuzhiyun GROUP(tsin_a_d0, 3, 4), 469*4882a593Smuzhiyun GROUP(tsin_a_dp, 3, 5), 470*4882a593Smuzhiyun GROUP(pwm_a_y, 1, 21), 471*4882a593Smuzhiyun GROUP(pwm_f_y, 1, 20), 472*4882a593Smuzhiyun GROUP(i2s_out_ch23_y, 1, 5), 473*4882a593Smuzhiyun GROUP(i2s_out_ch45_y, 1, 6), 474*4882a593Smuzhiyun GROUP(i2s_out_ch67_y, 1, 7), 475*4882a593Smuzhiyun GROUP(spdif_out_y, 1, 9), 476*4882a593Smuzhiyun GROUP(gen_clk_out, 6, 15), 477*4882a593Smuzhiyun 478*4882a593Smuzhiyun /* Bank Z */ 479*4882a593Smuzhiyun GROUP(eth_mdio, 6, 1), 480*4882a593Smuzhiyun GROUP(eth_mdc, 6, 0), 481*4882a593Smuzhiyun GROUP(eth_clk_rx_clk, 6, 13), 482*4882a593Smuzhiyun GROUP(eth_rx_dv, 6, 12), 483*4882a593Smuzhiyun GROUP(eth_rxd0, 6, 11), 484*4882a593Smuzhiyun GROUP(eth_rxd1, 6, 10), 485*4882a593Smuzhiyun GROUP(eth_rxd2, 6, 9), 486*4882a593Smuzhiyun GROUP(eth_rxd3, 6, 8), 487*4882a593Smuzhiyun GROUP(eth_rgmii_tx_clk, 6, 7), 488*4882a593Smuzhiyun GROUP(eth_tx_en, 6, 6), 489*4882a593Smuzhiyun GROUP(eth_txd0, 6, 5), 490*4882a593Smuzhiyun GROUP(eth_txd1, 6, 4), 491*4882a593Smuzhiyun GROUP(eth_txd2, 6, 3), 492*4882a593Smuzhiyun GROUP(eth_txd3, 6, 2), 493*4882a593Smuzhiyun GROUP(spi_ss0, 5, 26), 494*4882a593Smuzhiyun GROUP(spi_sclk, 5, 27), 495*4882a593Smuzhiyun GROUP(spi_miso, 5, 28), 496*4882a593Smuzhiyun GROUP(spi_mosi, 5, 29), 497*4882a593Smuzhiyun 498*4882a593Smuzhiyun /* Bank H */ 499*4882a593Smuzhiyun GROUP(hdmi_hpd, 1, 26), 500*4882a593Smuzhiyun GROUP(hdmi_sda, 1, 25), 501*4882a593Smuzhiyun GROUP(hdmi_scl, 1, 24), 502*4882a593Smuzhiyun 503*4882a593Smuzhiyun /* Bank DV */ 504*4882a593Smuzhiyun GROUP(uart_tx_b, 2, 29), 505*4882a593Smuzhiyun GROUP(uart_rx_b, 2, 28), 506*4882a593Smuzhiyun GROUP(uart_cts_b, 2, 27), 507*4882a593Smuzhiyun GROUP(uart_rts_b, 2, 26), 508*4882a593Smuzhiyun GROUP(pwm_b, 3, 21), 509*4882a593Smuzhiyun GROUP(pwm_d, 3, 20), 510*4882a593Smuzhiyun GROUP(i2c_sck_a, 7, 27), 511*4882a593Smuzhiyun GROUP(i2c_sda_a, 7, 26), 512*4882a593Smuzhiyun GROUP(i2c_sck_b, 7, 25), 513*4882a593Smuzhiyun GROUP(i2c_sda_b, 7, 24), 514*4882a593Smuzhiyun GROUP(i2c_sck_c, 7, 23), 515*4882a593Smuzhiyun GROUP(i2c_sda_c, 7, 22), 516*4882a593Smuzhiyun 517*4882a593Smuzhiyun /* Bank BOOT */ 518*4882a593Smuzhiyun GROUP(emmc_nand_d07, 4, 30), 519*4882a593Smuzhiyun GROUP(emmc_clk, 4, 18), 520*4882a593Smuzhiyun GROUP(emmc_cmd, 4, 19), 521*4882a593Smuzhiyun GROUP(emmc_ds, 4, 31), 522*4882a593Smuzhiyun GROUP(nor_d, 5, 1), 523*4882a593Smuzhiyun GROUP(nor_q, 5, 3), 524*4882a593Smuzhiyun GROUP(nor_c, 5, 2), 525*4882a593Smuzhiyun GROUP(nor_cs, 5, 0), 526*4882a593Smuzhiyun GROUP(nand_ce0, 4, 26), 527*4882a593Smuzhiyun GROUP(nand_ce1, 4, 27), 528*4882a593Smuzhiyun GROUP(nand_rb0, 4, 25), 529*4882a593Smuzhiyun GROUP(nand_ale, 4, 24), 530*4882a593Smuzhiyun GROUP(nand_cle, 4, 23), 531*4882a593Smuzhiyun GROUP(nand_wen_clk, 4, 22), 532*4882a593Smuzhiyun GROUP(nand_ren_wr, 4, 21), 533*4882a593Smuzhiyun GROUP(nand_dqs, 4, 20), 534*4882a593Smuzhiyun 535*4882a593Smuzhiyun /* Bank CARD */ 536*4882a593Smuzhiyun GROUP(sdcard_d1, 2, 14), 537*4882a593Smuzhiyun GROUP(sdcard_d0, 2, 15), 538*4882a593Smuzhiyun GROUP(sdcard_d3, 2, 12), 539*4882a593Smuzhiyun GROUP(sdcard_d2, 2, 13), 540*4882a593Smuzhiyun GROUP(sdcard_cmd, 2, 10), 541*4882a593Smuzhiyun GROUP(sdcard_clk, 2, 11), 542*4882a593Smuzhiyun }; 543*4882a593Smuzhiyun 544*4882a593Smuzhiyun static struct meson_pmx_group meson_gxbb_aobus_groups[] = { 545*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_0), 546*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_1), 547*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_2), 548*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_3), 549*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_4), 550*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_5), 551*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_6), 552*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_7), 553*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_8), 554*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_9), 555*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_10), 556*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_11), 557*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_12), 558*4882a593Smuzhiyun GPIO_GROUP(GPIOAO_13), 559*4882a593Smuzhiyun 560*4882a593Smuzhiyun /* bank AO */ 561*4882a593Smuzhiyun GROUP(uart_tx_ao_b, 0, 24), 562*4882a593Smuzhiyun GROUP(uart_rx_ao_b, 0, 25), 563*4882a593Smuzhiyun GROUP(uart_tx_ao_a, 0, 12), 564*4882a593Smuzhiyun GROUP(uart_rx_ao_a, 0, 11), 565*4882a593Smuzhiyun GROUP(uart_cts_ao_a, 0, 10), 566*4882a593Smuzhiyun GROUP(uart_rts_ao_a, 0, 9), 567*4882a593Smuzhiyun GROUP(uart_cts_ao_b, 0, 8), 568*4882a593Smuzhiyun GROUP(uart_rts_ao_b, 0, 7), 569*4882a593Smuzhiyun GROUP(i2c_sck_ao, 0, 6), 570*4882a593Smuzhiyun GROUP(i2c_sda_ao, 0, 5), 571*4882a593Smuzhiyun GROUP(i2c_slave_sck_ao, 0, 2), 572*4882a593Smuzhiyun GROUP(i2c_slave_sda_ao, 0, 1), 573*4882a593Smuzhiyun GROUP(remote_input_ao, 0, 0), 574*4882a593Smuzhiyun GROUP(pwm_ao_a_3, 0, 22), 575*4882a593Smuzhiyun GROUP(pwm_ao_a_6, 0, 18), 576*4882a593Smuzhiyun GROUP(pwm_ao_a_12, 0, 17), 577*4882a593Smuzhiyun GROUP(pwm_ao_b, 0, 3), 578*4882a593Smuzhiyun GROUP(i2s_am_clk, 0, 30), 579*4882a593Smuzhiyun GROUP(i2s_out_ao_clk, 0, 29), 580*4882a593Smuzhiyun GROUP(i2s_out_lr_clk, 0, 28), 581*4882a593Smuzhiyun GROUP(i2s_out_ch01_ao, 0, 27), 582*4882a593Smuzhiyun GROUP(i2s_out_ch23_ao, 1, 0), 583*4882a593Smuzhiyun GROUP(i2s_out_ch45_ao, 1, 1), 584*4882a593Smuzhiyun GROUP(spdif_out_ao_6, 0, 16), 585*4882a593Smuzhiyun GROUP(spdif_out_ao_13, 0, 4), 586*4882a593Smuzhiyun GROUP(ao_cec, 0, 15), 587*4882a593Smuzhiyun GROUP(ee_cec, 0, 14), 588*4882a593Smuzhiyun 589*4882a593Smuzhiyun /* test n pin */ 590*4882a593Smuzhiyun GROUP(i2s_out_ch67_ao, 1, 2), 591*4882a593Smuzhiyun }; 592*4882a593Smuzhiyun 593*4882a593Smuzhiyun static const char * const gpio_periphs_groups[] = { 594*4882a593Smuzhiyun "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", 595*4882a593Smuzhiyun "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", 596*4882a593Smuzhiyun "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13", "GPIOZ_14", 597*4882a593Smuzhiyun "GPIOZ_15", 598*4882a593Smuzhiyun 599*4882a593Smuzhiyun "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", 600*4882a593Smuzhiyun 601*4882a593Smuzhiyun "BOOT_0", "BOOT_1", "BOOT_2", "BOOT_3", "BOOT_4", 602*4882a593Smuzhiyun "BOOT_5", "BOOT_6", "BOOT_7", "BOOT_8", "BOOT_9", 603*4882a593Smuzhiyun "BOOT_10", "BOOT_11", "BOOT_12", "BOOT_13", "BOOT_14", 604*4882a593Smuzhiyun "BOOT_15", "BOOT_16", "BOOT_17", 605*4882a593Smuzhiyun 606*4882a593Smuzhiyun "CARD_0", "CARD_1", "CARD_2", "CARD_3", "CARD_4", 607*4882a593Smuzhiyun "CARD_5", "CARD_6", 608*4882a593Smuzhiyun 609*4882a593Smuzhiyun "GPIODV_0", "GPIODV_1", "GPIODV_2", "GPIODV_3", "GPIODV_4", 610*4882a593Smuzhiyun "GPIODV_5", "GPIODV_6", "GPIODV_7", "GPIODV_8", "GPIODV_9", 611*4882a593Smuzhiyun "GPIODV_10", "GPIODV_11", "GPIODV_12", "GPIODV_13", "GPIODV_14", 612*4882a593Smuzhiyun "GPIODV_15", "GPIODV_16", "GPIODV_17", "GPIODV_18", "GPIODV_19", 613*4882a593Smuzhiyun "GPIODV_20", "GPIODV_21", "GPIODV_22", "GPIODV_23", "GPIODV_24", 614*4882a593Smuzhiyun "GPIODV_25", "GPIODV_26", "GPIODV_27", "GPIODV_28", "GPIODV_29", 615*4882a593Smuzhiyun 616*4882a593Smuzhiyun "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", 617*4882a593Smuzhiyun "GPIOY_5", "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", 618*4882a593Smuzhiyun "GPIOY_10", "GPIOY_11", "GPIOY_12", "GPIOY_13", "GPIOY_14", 619*4882a593Smuzhiyun "GPIOY_15", "GPIOY_16", 620*4882a593Smuzhiyun 621*4882a593Smuzhiyun "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", 622*4882a593Smuzhiyun "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", 623*4882a593Smuzhiyun "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14", 624*4882a593Smuzhiyun "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19", 625*4882a593Smuzhiyun "GPIOX_20", "GPIOX_21", "GPIOX_22", 626*4882a593Smuzhiyun }; 627*4882a593Smuzhiyun 628*4882a593Smuzhiyun static const char * const tsin_a_groups[] = { 629*4882a593Smuzhiyun "tsin_a_clk", "tsin_a_sop", "tsin_a_d_valid", "tsin_a_d0", 630*4882a593Smuzhiyun "tsin_a_dp", "tsin_a_fail", 631*4882a593Smuzhiyun }; 632*4882a593Smuzhiyun 633*4882a593Smuzhiyun static const char * const tsin_b_groups[] = { 634*4882a593Smuzhiyun "tsin_b_clk", "tsin_b_sop", "tsin_b_d_valid", "tsin_b_d0", 635*4882a593Smuzhiyun }; 636*4882a593Smuzhiyun 637*4882a593Smuzhiyun static const char * const emmc_groups[] = { 638*4882a593Smuzhiyun "emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds", 639*4882a593Smuzhiyun }; 640*4882a593Smuzhiyun 641*4882a593Smuzhiyun static const char * const nor_groups[] = { 642*4882a593Smuzhiyun "nor_d", "nor_q", "nor_c", "nor_cs", 643*4882a593Smuzhiyun }; 644*4882a593Smuzhiyun 645*4882a593Smuzhiyun static const char * const spi_groups[] = { 646*4882a593Smuzhiyun "spi_mosi", "spi_miso", "spi_ss0", "spi_sclk", 647*4882a593Smuzhiyun }; 648*4882a593Smuzhiyun 649*4882a593Smuzhiyun static const char * const sdcard_groups[] = { 650*4882a593Smuzhiyun "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", 651*4882a593Smuzhiyun "sdcard_cmd", "sdcard_clk", 652*4882a593Smuzhiyun }; 653*4882a593Smuzhiyun 654*4882a593Smuzhiyun static const char * const sdio_groups[] = { 655*4882a593Smuzhiyun "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", 656*4882a593Smuzhiyun "sdio_cmd", "sdio_clk", "sdio_irq", 657*4882a593Smuzhiyun }; 658*4882a593Smuzhiyun 659*4882a593Smuzhiyun static const char * const nand_groups[] = { 660*4882a593Smuzhiyun "emmc_nand_d07", "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", 661*4882a593Smuzhiyun "nand_cle", "nand_wen_clk", "nand_ren_wr", "nand_dqs", 662*4882a593Smuzhiyun }; 663*4882a593Smuzhiyun 664*4882a593Smuzhiyun static const char * const uart_a_groups[] = { 665*4882a593Smuzhiyun "uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a", 666*4882a593Smuzhiyun }; 667*4882a593Smuzhiyun 668*4882a593Smuzhiyun static const char * const uart_b_groups[] = { 669*4882a593Smuzhiyun "uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b", 670*4882a593Smuzhiyun }; 671*4882a593Smuzhiyun 672*4882a593Smuzhiyun static const char * const uart_c_groups[] = { 673*4882a593Smuzhiyun "uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c", 674*4882a593Smuzhiyun }; 675*4882a593Smuzhiyun 676*4882a593Smuzhiyun static const char * const i2c_a_groups[] = { 677*4882a593Smuzhiyun "i2c_sck_a", "i2c_sda_a", 678*4882a593Smuzhiyun }; 679*4882a593Smuzhiyun 680*4882a593Smuzhiyun static const char * const i2c_b_groups[] = { 681*4882a593Smuzhiyun "i2c_sck_b", "i2c_sda_b", 682*4882a593Smuzhiyun }; 683*4882a593Smuzhiyun 684*4882a593Smuzhiyun static const char * const i2c_c_groups[] = { 685*4882a593Smuzhiyun "i2c_sck_c", "i2c_sda_c", 686*4882a593Smuzhiyun }; 687*4882a593Smuzhiyun 688*4882a593Smuzhiyun static const char * const eth_groups[] = { 689*4882a593Smuzhiyun "eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv", 690*4882a593Smuzhiyun "eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3", 691*4882a593Smuzhiyun "eth_rgmii_tx_clk", "eth_tx_en", 692*4882a593Smuzhiyun "eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3", 693*4882a593Smuzhiyun }; 694*4882a593Smuzhiyun 695*4882a593Smuzhiyun static const char * const pwm_a_x_groups[] = { 696*4882a593Smuzhiyun "pwm_a_x", 697*4882a593Smuzhiyun }; 698*4882a593Smuzhiyun 699*4882a593Smuzhiyun static const char * const pwm_a_y_groups[] = { 700*4882a593Smuzhiyun "pwm_a_y", 701*4882a593Smuzhiyun }; 702*4882a593Smuzhiyun 703*4882a593Smuzhiyun static const char * const pwm_b_groups[] = { 704*4882a593Smuzhiyun "pwm_b", 705*4882a593Smuzhiyun }; 706*4882a593Smuzhiyun 707*4882a593Smuzhiyun static const char * const pwm_d_groups[] = { 708*4882a593Smuzhiyun "pwm_d", 709*4882a593Smuzhiyun }; 710*4882a593Smuzhiyun 711*4882a593Smuzhiyun static const char * const pwm_e_groups[] = { 712*4882a593Smuzhiyun "pwm_e", 713*4882a593Smuzhiyun }; 714*4882a593Smuzhiyun 715*4882a593Smuzhiyun static const char * const pwm_f_x_groups[] = { 716*4882a593Smuzhiyun "pwm_f_x", 717*4882a593Smuzhiyun }; 718*4882a593Smuzhiyun 719*4882a593Smuzhiyun static const char * const pwm_f_y_groups[] = { 720*4882a593Smuzhiyun "pwm_f_y", 721*4882a593Smuzhiyun }; 722*4882a593Smuzhiyun 723*4882a593Smuzhiyun static const char * const hdmi_hpd_groups[] = { 724*4882a593Smuzhiyun "hdmi_hpd", 725*4882a593Smuzhiyun }; 726*4882a593Smuzhiyun 727*4882a593Smuzhiyun static const char * const hdmi_i2c_groups[] = { 728*4882a593Smuzhiyun "hdmi_sda", "hdmi_scl", 729*4882a593Smuzhiyun }; 730*4882a593Smuzhiyun 731*4882a593Smuzhiyun static const char * const i2s_out_groups[] = { 732*4882a593Smuzhiyun "i2s_out_ch23_y", "i2s_out_ch45_y", "i2s_out_ch67_y", 733*4882a593Smuzhiyun }; 734*4882a593Smuzhiyun 735*4882a593Smuzhiyun static const char * const spdif_out_groups[] = { 736*4882a593Smuzhiyun "spdif_out_y", 737*4882a593Smuzhiyun }; 738*4882a593Smuzhiyun 739*4882a593Smuzhiyun static const char * const gen_clk_out_groups[] = { 740*4882a593Smuzhiyun "gen_clk_out", 741*4882a593Smuzhiyun }; 742*4882a593Smuzhiyun 743*4882a593Smuzhiyun static const char * const gpio_aobus_groups[] = { 744*4882a593Smuzhiyun "GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4", 745*4882a593Smuzhiyun "GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9", 746*4882a593Smuzhiyun "GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13", 747*4882a593Smuzhiyun 748*4882a593Smuzhiyun "GPIO_TEST_N", 749*4882a593Smuzhiyun }; 750*4882a593Smuzhiyun 751*4882a593Smuzhiyun static const char * const uart_ao_groups[] = { 752*4882a593Smuzhiyun "uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a", 753*4882a593Smuzhiyun }; 754*4882a593Smuzhiyun 755*4882a593Smuzhiyun static const char * const uart_ao_b_groups[] = { 756*4882a593Smuzhiyun "uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b", 757*4882a593Smuzhiyun }; 758*4882a593Smuzhiyun 759*4882a593Smuzhiyun static const char * const i2c_ao_groups[] = { 760*4882a593Smuzhiyun "i2c_sck_ao", "i2c_sda_ao", 761*4882a593Smuzhiyun }; 762*4882a593Smuzhiyun 763*4882a593Smuzhiyun static const char * const i2c_slave_ao_groups[] = { 764*4882a593Smuzhiyun "i2c_slave_sck_ao", "i2c_slave_sda_ao", 765*4882a593Smuzhiyun }; 766*4882a593Smuzhiyun 767*4882a593Smuzhiyun static const char * const remote_input_ao_groups[] = { 768*4882a593Smuzhiyun "remote_input_ao", 769*4882a593Smuzhiyun }; 770*4882a593Smuzhiyun 771*4882a593Smuzhiyun static const char * const pwm_ao_a_3_groups[] = { 772*4882a593Smuzhiyun "pwm_ao_a_3", 773*4882a593Smuzhiyun }; 774*4882a593Smuzhiyun 775*4882a593Smuzhiyun static const char * const pwm_ao_a_6_groups[] = { 776*4882a593Smuzhiyun "pwm_ao_a_6", 777*4882a593Smuzhiyun }; 778*4882a593Smuzhiyun 779*4882a593Smuzhiyun static const char * const pwm_ao_a_12_groups[] = { 780*4882a593Smuzhiyun "pwm_ao_a_12", 781*4882a593Smuzhiyun }; 782*4882a593Smuzhiyun 783*4882a593Smuzhiyun static const char * const pwm_ao_b_groups[] = { 784*4882a593Smuzhiyun "pwm_ao_b", 785*4882a593Smuzhiyun }; 786*4882a593Smuzhiyun 787*4882a593Smuzhiyun static const char * const i2s_out_ao_groups[] = { 788*4882a593Smuzhiyun "i2s_am_clk", "i2s_out_ao_clk", "i2s_out_lr_clk", 789*4882a593Smuzhiyun "i2s_out_ch01_ao", "i2s_out_ch23_ao", "i2s_out_ch45_ao", 790*4882a593Smuzhiyun "i2s_out_ch67_ao", 791*4882a593Smuzhiyun }; 792*4882a593Smuzhiyun 793*4882a593Smuzhiyun static const char * const spdif_out_ao_groups[] = { 794*4882a593Smuzhiyun "spdif_out_ao_6", "spdif_out_ao_13", 795*4882a593Smuzhiyun }; 796*4882a593Smuzhiyun 797*4882a593Smuzhiyun static const char * const cec_ao_groups[] = { 798*4882a593Smuzhiyun "ao_cec", "ee_cec", 799*4882a593Smuzhiyun }; 800*4882a593Smuzhiyun 801*4882a593Smuzhiyun static struct meson_pmx_func meson_gxbb_periphs_functions[] = { 802*4882a593Smuzhiyun FUNCTION(gpio_periphs), 803*4882a593Smuzhiyun FUNCTION(emmc), 804*4882a593Smuzhiyun FUNCTION(nor), 805*4882a593Smuzhiyun FUNCTION(spi), 806*4882a593Smuzhiyun FUNCTION(sdcard), 807*4882a593Smuzhiyun FUNCTION(sdio), 808*4882a593Smuzhiyun FUNCTION(nand), 809*4882a593Smuzhiyun FUNCTION(uart_a), 810*4882a593Smuzhiyun FUNCTION(uart_b), 811*4882a593Smuzhiyun FUNCTION(uart_c), 812*4882a593Smuzhiyun FUNCTION(i2c_a), 813*4882a593Smuzhiyun FUNCTION(i2c_b), 814*4882a593Smuzhiyun FUNCTION(i2c_c), 815*4882a593Smuzhiyun FUNCTION(eth), 816*4882a593Smuzhiyun FUNCTION(pwm_a_x), 817*4882a593Smuzhiyun FUNCTION(pwm_a_y), 818*4882a593Smuzhiyun FUNCTION(pwm_b), 819*4882a593Smuzhiyun FUNCTION(pwm_d), 820*4882a593Smuzhiyun FUNCTION(pwm_e), 821*4882a593Smuzhiyun FUNCTION(pwm_f_x), 822*4882a593Smuzhiyun FUNCTION(pwm_f_y), 823*4882a593Smuzhiyun FUNCTION(hdmi_hpd), 824*4882a593Smuzhiyun FUNCTION(hdmi_i2c), 825*4882a593Smuzhiyun FUNCTION(i2s_out), 826*4882a593Smuzhiyun FUNCTION(spdif_out), 827*4882a593Smuzhiyun FUNCTION(gen_clk_out), 828*4882a593Smuzhiyun FUNCTION(tsin_a), 829*4882a593Smuzhiyun FUNCTION(tsin_b), 830*4882a593Smuzhiyun }; 831*4882a593Smuzhiyun 832*4882a593Smuzhiyun static struct meson_pmx_func meson_gxbb_aobus_functions[] = { 833*4882a593Smuzhiyun FUNCTION(gpio_aobus), 834*4882a593Smuzhiyun FUNCTION(uart_ao), 835*4882a593Smuzhiyun FUNCTION(uart_ao_b), 836*4882a593Smuzhiyun FUNCTION(i2c_ao), 837*4882a593Smuzhiyun FUNCTION(i2c_slave_ao), 838*4882a593Smuzhiyun FUNCTION(remote_input_ao), 839*4882a593Smuzhiyun FUNCTION(pwm_ao_a_3), 840*4882a593Smuzhiyun FUNCTION(pwm_ao_a_6), 841*4882a593Smuzhiyun FUNCTION(pwm_ao_a_12), 842*4882a593Smuzhiyun FUNCTION(pwm_ao_b), 843*4882a593Smuzhiyun FUNCTION(i2s_out_ao), 844*4882a593Smuzhiyun FUNCTION(spdif_out_ao), 845*4882a593Smuzhiyun FUNCTION(cec_ao), 846*4882a593Smuzhiyun }; 847*4882a593Smuzhiyun 848*4882a593Smuzhiyun static struct meson_bank meson_gxbb_periphs_banks[] = { 849*4882a593Smuzhiyun /* name first last irq pullen pull dir out in */ 850*4882a593Smuzhiyun BANK("X", GPIOX_0, GPIOX_22, 106, 128, 4, 0, 4, 0, 12, 0, 13, 0, 14, 0), 851*4882a593Smuzhiyun BANK("Y", GPIOY_0, GPIOY_16, 89, 105, 1, 0, 1, 0, 3, 0, 4, 0, 5, 0), 852*4882a593Smuzhiyun BANK("DV", GPIODV_0, GPIODV_29, 59, 88, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0), 853*4882a593Smuzhiyun BANK("H", GPIOH_0, GPIOH_3, 30, 33, 1, 20, 1, 20, 3, 20, 4, 20, 5, 20), 854*4882a593Smuzhiyun BANK("Z", GPIOZ_0, GPIOZ_15, 14, 29, 3, 0, 3, 0, 9, 0, 10, 0, 11, 0), 855*4882a593Smuzhiyun BANK("CARD", CARD_0, CARD_6, 52, 58, 2, 20, 2, 20, 6, 20, 7, 20, 8, 20), 856*4882a593Smuzhiyun BANK("BOOT", BOOT_0, BOOT_17, 34, 51, 2, 0, 2, 0, 6, 0, 7, 0, 8, 0), 857*4882a593Smuzhiyun BANK("CLK", GPIOCLK_0, GPIOCLK_3, 129, 132, 3, 28, 3, 28, 9, 28, 10, 28, 11, 28), 858*4882a593Smuzhiyun }; 859*4882a593Smuzhiyun 860*4882a593Smuzhiyun static struct meson_bank meson_gxbb_aobus_banks[] = { 861*4882a593Smuzhiyun /* name first last irq pullen pull dir out in */ 862*4882a593Smuzhiyun BANK("AO", GPIOAO_0, GPIOAO_13, 0, 13, 0, 16, 0, 0, 0, 0, 0, 16, 1, 0), 863*4882a593Smuzhiyun }; 864*4882a593Smuzhiyun 865*4882a593Smuzhiyun static struct meson_pinctrl_data meson_gxbb_periphs_pinctrl_data = { 866*4882a593Smuzhiyun .name = "periphs-banks", 867*4882a593Smuzhiyun .pins = meson_gxbb_periphs_pins, 868*4882a593Smuzhiyun .groups = meson_gxbb_periphs_groups, 869*4882a593Smuzhiyun .funcs = meson_gxbb_periphs_functions, 870*4882a593Smuzhiyun .banks = meson_gxbb_periphs_banks, 871*4882a593Smuzhiyun .num_pins = ARRAY_SIZE(meson_gxbb_periphs_pins), 872*4882a593Smuzhiyun .num_groups = ARRAY_SIZE(meson_gxbb_periphs_groups), 873*4882a593Smuzhiyun .num_funcs = ARRAY_SIZE(meson_gxbb_periphs_functions), 874*4882a593Smuzhiyun .num_banks = ARRAY_SIZE(meson_gxbb_periphs_banks), 875*4882a593Smuzhiyun .pmx_ops = &meson8_pmx_ops, 876*4882a593Smuzhiyun }; 877*4882a593Smuzhiyun 878*4882a593Smuzhiyun static struct meson_pinctrl_data meson_gxbb_aobus_pinctrl_data = { 879*4882a593Smuzhiyun .name = "aobus-banks", 880*4882a593Smuzhiyun .pins = meson_gxbb_aobus_pins, 881*4882a593Smuzhiyun .groups = meson_gxbb_aobus_groups, 882*4882a593Smuzhiyun .funcs = meson_gxbb_aobus_functions, 883*4882a593Smuzhiyun .banks = meson_gxbb_aobus_banks, 884*4882a593Smuzhiyun .num_pins = ARRAY_SIZE(meson_gxbb_aobus_pins), 885*4882a593Smuzhiyun .num_groups = ARRAY_SIZE(meson_gxbb_aobus_groups), 886*4882a593Smuzhiyun .num_funcs = ARRAY_SIZE(meson_gxbb_aobus_functions), 887*4882a593Smuzhiyun .num_banks = ARRAY_SIZE(meson_gxbb_aobus_banks), 888*4882a593Smuzhiyun .pmx_ops = &meson8_pmx_ops, 889*4882a593Smuzhiyun .parse_dt = meson8_aobus_parse_dt_extra, 890*4882a593Smuzhiyun }; 891*4882a593Smuzhiyun 892*4882a593Smuzhiyun static const struct of_device_id meson_gxbb_pinctrl_dt_match[] = { 893*4882a593Smuzhiyun { 894*4882a593Smuzhiyun .compatible = "amlogic,meson-gxbb-periphs-pinctrl", 895*4882a593Smuzhiyun .data = &meson_gxbb_periphs_pinctrl_data, 896*4882a593Smuzhiyun }, 897*4882a593Smuzhiyun { 898*4882a593Smuzhiyun .compatible = "amlogic,meson-gxbb-aobus-pinctrl", 899*4882a593Smuzhiyun .data = &meson_gxbb_aobus_pinctrl_data, 900*4882a593Smuzhiyun }, 901*4882a593Smuzhiyun { }, 902*4882a593Smuzhiyun }; 903*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, meson_gxbb_pinctrl_dt_match); 904*4882a593Smuzhiyun 905*4882a593Smuzhiyun static struct platform_driver meson_gxbb_pinctrl_driver = { 906*4882a593Smuzhiyun .probe = meson_pinctrl_probe, 907*4882a593Smuzhiyun .driver = { 908*4882a593Smuzhiyun .name = "meson-gxbb-pinctrl", 909*4882a593Smuzhiyun .of_match_table = meson_gxbb_pinctrl_dt_match, 910*4882a593Smuzhiyun }, 911*4882a593Smuzhiyun }; 912*4882a593Smuzhiyun module_platform_driver(meson_gxbb_pinctrl_driver); 913*4882a593Smuzhiyun MODULE_LICENSE("GPL v2"); 914