1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Second generation of pinmux driver for Amlogic Meson-AXG SoC.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (c) 2017 Baylibre SAS.
5*4882a593Smuzhiyun * Author: Jerome Brunet <jbrunet@baylibre.com>
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
8*4882a593Smuzhiyun * Author: Xingyu Chen <xingyu.chen@amlogic.com>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * SPDX-License-Identifier: (GPL-2.0+ or MIT)
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /*
14*4882a593Smuzhiyun * This new generation of pinctrl IP is mainly adopted by the
15*4882a593Smuzhiyun * Meson-AXG SoC and later series, which use 4-width continuous
16*4882a593Smuzhiyun * register bit to select the function for each pin.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * The value 0 is always selecting the GPIO mode, while other
19*4882a593Smuzhiyun * values (start from 1) for selecting the function mode.
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun #include <linux/device.h>
22*4882a593Smuzhiyun #include <linux/regmap.h>
23*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
24*4882a593Smuzhiyun #include <linux/pinctrl/pinmux.h>
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #include "pinctrl-meson.h"
27*4882a593Smuzhiyun #include "pinctrl-meson-axg-pmx.h"
28*4882a593Smuzhiyun
meson_axg_pmx_get_bank(struct meson_pinctrl * pc,unsigned int pin,struct meson_pmx_bank ** bank)29*4882a593Smuzhiyun static int meson_axg_pmx_get_bank(struct meson_pinctrl *pc,
30*4882a593Smuzhiyun unsigned int pin,
31*4882a593Smuzhiyun struct meson_pmx_bank **bank)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun int i;
34*4882a593Smuzhiyun struct meson_axg_pmx_data *pmx = pc->data->pmx_data;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun for (i = 0; i < pmx->num_pmx_banks; i++)
37*4882a593Smuzhiyun if (pin >= pmx->pmx_banks[i].first &&
38*4882a593Smuzhiyun pin <= pmx->pmx_banks[i].last) {
39*4882a593Smuzhiyun *bank = &pmx->pmx_banks[i];
40*4882a593Smuzhiyun return 0;
41*4882a593Smuzhiyun }
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return -EINVAL;
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun
meson_pmx_calc_reg_and_offset(struct meson_pmx_bank * bank,unsigned int pin,unsigned int * reg,unsigned int * offset)46*4882a593Smuzhiyun static int meson_pmx_calc_reg_and_offset(struct meson_pmx_bank *bank,
47*4882a593Smuzhiyun unsigned int pin, unsigned int *reg,
48*4882a593Smuzhiyun unsigned int *offset)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun int shift;
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun shift = pin - bank->first;
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun *reg = bank->reg + (bank->offset + (shift << 2)) / 32;
55*4882a593Smuzhiyun *offset = (bank->offset + (shift << 2)) % 32;
56*4882a593Smuzhiyun
57*4882a593Smuzhiyun return 0;
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun
meson_axg_pmx_update_function(struct meson_pinctrl * pc,unsigned int pin,unsigned int func)60*4882a593Smuzhiyun static int meson_axg_pmx_update_function(struct meson_pinctrl *pc,
61*4882a593Smuzhiyun unsigned int pin, unsigned int func)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun int ret;
64*4882a593Smuzhiyun int reg;
65*4882a593Smuzhiyun int offset;
66*4882a593Smuzhiyun struct meson_pmx_bank *bank;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun ret = meson_axg_pmx_get_bank(pc, pin, &bank);
69*4882a593Smuzhiyun if (ret)
70*4882a593Smuzhiyun return ret;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun meson_pmx_calc_reg_and_offset(bank, pin, ®, &offset);
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun ret = regmap_update_bits(pc->reg_mux, reg << 2,
75*4882a593Smuzhiyun 0xf << offset, (func & 0xf) << offset);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun return ret;
78*4882a593Smuzhiyun }
79*4882a593Smuzhiyun
meson_axg_pmx_set_mux(struct pinctrl_dev * pcdev,unsigned int func_num,unsigned int group_num)80*4882a593Smuzhiyun static int meson_axg_pmx_set_mux(struct pinctrl_dev *pcdev,
81*4882a593Smuzhiyun unsigned int func_num, unsigned int group_num)
82*4882a593Smuzhiyun {
83*4882a593Smuzhiyun int i;
84*4882a593Smuzhiyun int ret;
85*4882a593Smuzhiyun struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
86*4882a593Smuzhiyun struct meson_pmx_func *func = &pc->data->funcs[func_num];
87*4882a593Smuzhiyun struct meson_pmx_group *group = &pc->data->groups[group_num];
88*4882a593Smuzhiyun struct meson_pmx_axg_data *pmx_data =
89*4882a593Smuzhiyun (struct meson_pmx_axg_data *)group->data;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun dev_dbg(pc->dev, "enable function %s, group %s\n", func->name,
92*4882a593Smuzhiyun group->name);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun for (i = 0; i < group->num_pins; i++) {
95*4882a593Smuzhiyun ret = meson_axg_pmx_update_function(pc, group->pins[i],
96*4882a593Smuzhiyun pmx_data->func);
97*4882a593Smuzhiyun if (ret)
98*4882a593Smuzhiyun return ret;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun return 0;
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun
meson_axg_pmx_request_gpio(struct pinctrl_dev * pcdev,struct pinctrl_gpio_range * range,unsigned int offset)104*4882a593Smuzhiyun static int meson_axg_pmx_request_gpio(struct pinctrl_dev *pcdev,
105*4882a593Smuzhiyun struct pinctrl_gpio_range *range, unsigned int offset)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct meson_pinctrl *pc = pinctrl_dev_get_drvdata(pcdev);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun return meson_axg_pmx_update_function(pc, offset, 0);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun
112*4882a593Smuzhiyun const struct pinmux_ops meson_axg_pmx_ops = {
113*4882a593Smuzhiyun .set_mux = meson_axg_pmx_set_mux,
114*4882a593Smuzhiyun .get_functions_count = meson_pmx_get_funcs_count,
115*4882a593Smuzhiyun .get_function_name = meson_pmx_get_func_name,
116*4882a593Smuzhiyun .get_function_groups = meson_pmx_get_groups,
117*4882a593Smuzhiyun .gpio_request_enable = meson_axg_pmx_request_gpio,
118*4882a593Smuzhiyun };
119*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(meson_axg_pmx_ops);
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun MODULE_LICENSE("Dual BSD/GPL");
122