1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2018 MediaTek Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Sean Wang <sean.wang@mediatek.com> 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __PINCTRL_MTK_COMMON_V2_H 10*4882a593Smuzhiyun #define __PINCTRL_MTK_COMMON_V2_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/gpio/driver.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MTK_INPUT 0 15*4882a593Smuzhiyun #define MTK_OUTPUT 1 16*4882a593Smuzhiyun #define MTK_DISABLE 0 17*4882a593Smuzhiyun #define MTK_ENABLE 1 18*4882a593Smuzhiyun #define MTK_PULLDOWN 0 19*4882a593Smuzhiyun #define MTK_PULLUP 1 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define EINT_NA U16_MAX 22*4882a593Smuzhiyun #define NO_EINT_SUPPORT EINT_NA 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, \ 25*4882a593Smuzhiyun _s_bit, _x_bits, _sz_reg, _fixed) { \ 26*4882a593Smuzhiyun .s_pin = _s_pin, \ 27*4882a593Smuzhiyun .e_pin = _e_pin, \ 28*4882a593Smuzhiyun .i_base = _i_base, \ 29*4882a593Smuzhiyun .s_addr = _s_addr, \ 30*4882a593Smuzhiyun .x_addrs = _x_addrs, \ 31*4882a593Smuzhiyun .s_bit = _s_bit, \ 32*4882a593Smuzhiyun .x_bits = _x_bits, \ 33*4882a593Smuzhiyun .sz_reg = _sz_reg, \ 34*4882a593Smuzhiyun .fixed = _fixed, \ 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ 38*4882a593Smuzhiyun PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ 39*4882a593Smuzhiyun _x_bits, 32, 0) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \ 42*4882a593Smuzhiyun PIN_FIELD_CALC(_s_pin, _e_pin, 0, _s_addr, _x_addrs, _s_bit, \ 43*4882a593Smuzhiyun _x_bits, 32, 1) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* List these attributes which could be modified for the pin */ 46*4882a593Smuzhiyun enum { 47*4882a593Smuzhiyun PINCTRL_PIN_REG_MODE, 48*4882a593Smuzhiyun PINCTRL_PIN_REG_DIR, 49*4882a593Smuzhiyun PINCTRL_PIN_REG_DI, 50*4882a593Smuzhiyun PINCTRL_PIN_REG_DO, 51*4882a593Smuzhiyun PINCTRL_PIN_REG_SR, 52*4882a593Smuzhiyun PINCTRL_PIN_REG_SMT, 53*4882a593Smuzhiyun PINCTRL_PIN_REG_PD, 54*4882a593Smuzhiyun PINCTRL_PIN_REG_PU, 55*4882a593Smuzhiyun PINCTRL_PIN_REG_E4, 56*4882a593Smuzhiyun PINCTRL_PIN_REG_E8, 57*4882a593Smuzhiyun PINCTRL_PIN_REG_TDSEL, 58*4882a593Smuzhiyun PINCTRL_PIN_REG_RDSEL, 59*4882a593Smuzhiyun PINCTRL_PIN_REG_DRV, 60*4882a593Smuzhiyun PINCTRL_PIN_REG_PUPD, 61*4882a593Smuzhiyun PINCTRL_PIN_REG_R0, 62*4882a593Smuzhiyun PINCTRL_PIN_REG_R1, 63*4882a593Smuzhiyun PINCTRL_PIN_REG_IES, 64*4882a593Smuzhiyun PINCTRL_PIN_REG_PULLEN, 65*4882a593Smuzhiyun PINCTRL_PIN_REG_PULLSEL, 66*4882a593Smuzhiyun PINCTRL_PIN_REG_DRV_EN, 67*4882a593Smuzhiyun PINCTRL_PIN_REG_DRV_E0, 68*4882a593Smuzhiyun PINCTRL_PIN_REG_DRV_E1, 69*4882a593Smuzhiyun PINCTRL_PIN_REG_MAX, 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Group the pins by the driving current */ 73*4882a593Smuzhiyun enum { 74*4882a593Smuzhiyun DRV_FIXED, 75*4882a593Smuzhiyun DRV_GRP0, 76*4882a593Smuzhiyun DRV_GRP1, 77*4882a593Smuzhiyun DRV_GRP2, 78*4882a593Smuzhiyun DRV_GRP3, 79*4882a593Smuzhiyun DRV_GRP4, 80*4882a593Smuzhiyun DRV_GRP_MAX, 81*4882a593Smuzhiyun }; 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun static const char * const mtk_default_register_base_names[] __maybe_unused = { 84*4882a593Smuzhiyun "base", 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* struct mtk_pin_field - the structure that holds the information of the field 88*4882a593Smuzhiyun * used to describe the attribute for the pin 89*4882a593Smuzhiyun * @base: the index pointing to the entry in base address list 90*4882a593Smuzhiyun * @offset: the register offset relative to the base address 91*4882a593Smuzhiyun * @mask: the mask used to filter out the field from the register 92*4882a593Smuzhiyun * @bitpos: the start bit relative to the register 93*4882a593Smuzhiyun * @next: the indication that the field would be extended to the 94*4882a593Smuzhiyun next register 95*4882a593Smuzhiyun */ 96*4882a593Smuzhiyun struct mtk_pin_field { 97*4882a593Smuzhiyun u8 index; 98*4882a593Smuzhiyun u32 offset; 99*4882a593Smuzhiyun u32 mask; 100*4882a593Smuzhiyun u8 bitpos; 101*4882a593Smuzhiyun u8 next; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* struct mtk_pin_field_calc - the structure that holds the range providing 105*4882a593Smuzhiyun * the guide used to look up the relevant field 106*4882a593Smuzhiyun * @s_pin: the start pin within the range 107*4882a593Smuzhiyun * @e_pin: the end pin within the range 108*4882a593Smuzhiyun * @i_base: the index pointing to the entry in base address list 109*4882a593Smuzhiyun * @s_addr: the start address for the range 110*4882a593Smuzhiyun * @x_addrs: the address distance between two consecutive registers 111*4882a593Smuzhiyun * within the range 112*4882a593Smuzhiyun * @s_bit: the start bit for the first register within the range 113*4882a593Smuzhiyun * @x_bits: the bit distance between two consecutive pins within 114*4882a593Smuzhiyun * the range 115*4882a593Smuzhiyun * @sz_reg: the size of bits in a register 116*4882a593Smuzhiyun * @fixed: the consecutive pins share the same bits with the 1st 117*4882a593Smuzhiyun * pin 118*4882a593Smuzhiyun */ 119*4882a593Smuzhiyun struct mtk_pin_field_calc { 120*4882a593Smuzhiyun u16 s_pin; 121*4882a593Smuzhiyun u16 e_pin; 122*4882a593Smuzhiyun u8 i_base; 123*4882a593Smuzhiyun u32 s_addr; 124*4882a593Smuzhiyun u8 x_addrs; 125*4882a593Smuzhiyun u8 s_bit; 126*4882a593Smuzhiyun u8 x_bits; 127*4882a593Smuzhiyun u8 sz_reg; 128*4882a593Smuzhiyun u8 fixed; 129*4882a593Smuzhiyun }; 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* struct mtk_pin_reg_calc - the structure that holds all ranges used to 132*4882a593Smuzhiyun * determine which register the pin would make use of 133*4882a593Smuzhiyun * for certain pin attribute. 134*4882a593Smuzhiyun * @range: the start address for the range 135*4882a593Smuzhiyun * @nranges: the number of items in the range 136*4882a593Smuzhiyun */ 137*4882a593Smuzhiyun struct mtk_pin_reg_calc { 138*4882a593Smuzhiyun const struct mtk_pin_field_calc *range; 139*4882a593Smuzhiyun unsigned int nranges; 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /** 143*4882a593Smuzhiyun * struct mtk_func_desc - the structure that providing information 144*4882a593Smuzhiyun * all the funcs for this pin 145*4882a593Smuzhiyun * @name: the name of function 146*4882a593Smuzhiyun * @muxval: the mux to the function 147*4882a593Smuzhiyun */ 148*4882a593Smuzhiyun struct mtk_func_desc { 149*4882a593Smuzhiyun const char *name; 150*4882a593Smuzhiyun u8 muxval; 151*4882a593Smuzhiyun }; 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /** 154*4882a593Smuzhiyun * struct mtk_eint_desc - the structure that providing information 155*4882a593Smuzhiyun * for eint data per pin 156*4882a593Smuzhiyun * @eint_m: the eint mux for this pin 157*4882a593Smuzhiyun * @eitn_n: the eint number for this pin 158*4882a593Smuzhiyun */ 159*4882a593Smuzhiyun struct mtk_eint_desc { 160*4882a593Smuzhiyun u16 eint_m; 161*4882a593Smuzhiyun u16 eint_n; 162*4882a593Smuzhiyun }; 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun /** 165*4882a593Smuzhiyun * struct mtk_pin_desc - the structure that providing information 166*4882a593Smuzhiyun * for each pin of chips 167*4882a593Smuzhiyun * @number: unique pin number from the global pin number space 168*4882a593Smuzhiyun * @name: name for this pin 169*4882a593Smuzhiyun * @eint: the eint data for this pin 170*4882a593Smuzhiyun * @drv_n: the index with the driving group 171*4882a593Smuzhiyun * @funcs: all available functions for this pins (only used in 172*4882a593Smuzhiyun * those drivers compatible to pinctrl-mtk-common.c-like 173*4882a593Smuzhiyun * ones) 174*4882a593Smuzhiyun */ 175*4882a593Smuzhiyun struct mtk_pin_desc { 176*4882a593Smuzhiyun unsigned int number; 177*4882a593Smuzhiyun const char *name; 178*4882a593Smuzhiyun struct mtk_eint_desc eint; 179*4882a593Smuzhiyun u8 drv_n; 180*4882a593Smuzhiyun struct mtk_func_desc *funcs; 181*4882a593Smuzhiyun }; 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun struct mtk_pinctrl_group { 184*4882a593Smuzhiyun const char *name; 185*4882a593Smuzhiyun unsigned long config; 186*4882a593Smuzhiyun unsigned pin; 187*4882a593Smuzhiyun }; 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun struct mtk_pinctrl; 190*4882a593Smuzhiyun 191*4882a593Smuzhiyun /* struct mtk_pin_soc - the structure that holds SoC-specific data */ 192*4882a593Smuzhiyun struct mtk_pin_soc { 193*4882a593Smuzhiyun const struct mtk_pin_reg_calc *reg_cal; 194*4882a593Smuzhiyun const struct mtk_pin_desc *pins; 195*4882a593Smuzhiyun unsigned int npins; 196*4882a593Smuzhiyun const struct group_desc *grps; 197*4882a593Smuzhiyun unsigned int ngrps; 198*4882a593Smuzhiyun const struct function_desc *funcs; 199*4882a593Smuzhiyun unsigned int nfuncs; 200*4882a593Smuzhiyun const struct mtk_eint_regs *eint_regs; 201*4882a593Smuzhiyun const struct mtk_eint_hw *eint_hw; 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Specific parameters per SoC */ 204*4882a593Smuzhiyun u8 gpio_m; 205*4882a593Smuzhiyun bool ies_present; 206*4882a593Smuzhiyun const char * const *base_names; 207*4882a593Smuzhiyun unsigned int nbase_names; 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun /* Specific pinconfig operations */ 210*4882a593Smuzhiyun int (*bias_disable_set)(struct mtk_pinctrl *hw, 211*4882a593Smuzhiyun const struct mtk_pin_desc *desc); 212*4882a593Smuzhiyun int (*bias_disable_get)(struct mtk_pinctrl *hw, 213*4882a593Smuzhiyun const struct mtk_pin_desc *desc, int *res); 214*4882a593Smuzhiyun int (*bias_set)(struct mtk_pinctrl *hw, 215*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup); 216*4882a593Smuzhiyun int (*bias_get)(struct mtk_pinctrl *hw, 217*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup, int *res); 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun int (*bias_set_combo)(struct mtk_pinctrl *hw, 220*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 pullup, u32 arg); 221*4882a593Smuzhiyun int (*bias_get_combo)(struct mtk_pinctrl *hw, 222*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 *pullup, u32 *arg); 223*4882a593Smuzhiyun 224*4882a593Smuzhiyun int (*drive_set)(struct mtk_pinctrl *hw, 225*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 arg); 226*4882a593Smuzhiyun int (*drive_get)(struct mtk_pinctrl *hw, 227*4882a593Smuzhiyun const struct mtk_pin_desc *desc, int *val); 228*4882a593Smuzhiyun 229*4882a593Smuzhiyun int (*adv_pull_set)(struct mtk_pinctrl *hw, 230*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup, 231*4882a593Smuzhiyun u32 arg); 232*4882a593Smuzhiyun int (*adv_pull_get)(struct mtk_pinctrl *hw, 233*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup, 234*4882a593Smuzhiyun u32 *val); 235*4882a593Smuzhiyun int (*adv_drive_set)(struct mtk_pinctrl *hw, 236*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 arg); 237*4882a593Smuzhiyun int (*adv_drive_get)(struct mtk_pinctrl *hw, 238*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 *val); 239*4882a593Smuzhiyun 240*4882a593Smuzhiyun /* Specific driver data */ 241*4882a593Smuzhiyun void *driver_data; 242*4882a593Smuzhiyun }; 243*4882a593Smuzhiyun 244*4882a593Smuzhiyun struct mtk_pinctrl { 245*4882a593Smuzhiyun struct pinctrl_dev *pctrl; 246*4882a593Smuzhiyun void __iomem **base; 247*4882a593Smuzhiyun u8 nbase; 248*4882a593Smuzhiyun struct device *dev; 249*4882a593Smuzhiyun struct gpio_chip chip; 250*4882a593Smuzhiyun const struct mtk_pin_soc *soc; 251*4882a593Smuzhiyun struct mtk_eint *eint; 252*4882a593Smuzhiyun struct mtk_pinctrl_group *groups; 253*4882a593Smuzhiyun const char **grp_names; 254*4882a593Smuzhiyun }; 255*4882a593Smuzhiyun 256*4882a593Smuzhiyun void mtk_rmw(struct mtk_pinctrl *pctl, u8 i, u32 reg, u32 mask, u32 set); 257*4882a593Smuzhiyun 258*4882a593Smuzhiyun int mtk_hw_set_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 259*4882a593Smuzhiyun int field, int value); 260*4882a593Smuzhiyun int mtk_hw_get_value(struct mtk_pinctrl *hw, const struct mtk_pin_desc *desc, 261*4882a593Smuzhiyun int field, int *value); 262*4882a593Smuzhiyun 263*4882a593Smuzhiyun int mtk_build_eint(struct mtk_pinctrl *hw, struct platform_device *pdev); 264*4882a593Smuzhiyun 265*4882a593Smuzhiyun int mtk_pinconf_bias_disable_set(struct mtk_pinctrl *hw, 266*4882a593Smuzhiyun const struct mtk_pin_desc *desc); 267*4882a593Smuzhiyun int mtk_pinconf_bias_disable_get(struct mtk_pinctrl *hw, 268*4882a593Smuzhiyun const struct mtk_pin_desc *desc, int *res); 269*4882a593Smuzhiyun int mtk_pinconf_bias_set(struct mtk_pinctrl *hw, 270*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup); 271*4882a593Smuzhiyun int mtk_pinconf_bias_get(struct mtk_pinctrl *hw, 272*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup, 273*4882a593Smuzhiyun int *res); 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun int mtk_pinconf_bias_disable_set_rev1(struct mtk_pinctrl *hw, 276*4882a593Smuzhiyun const struct mtk_pin_desc *desc); 277*4882a593Smuzhiyun int mtk_pinconf_bias_disable_get_rev1(struct mtk_pinctrl *hw, 278*4882a593Smuzhiyun const struct mtk_pin_desc *desc, 279*4882a593Smuzhiyun int *res); 280*4882a593Smuzhiyun int mtk_pinconf_bias_set_rev1(struct mtk_pinctrl *hw, 281*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup); 282*4882a593Smuzhiyun int mtk_pinconf_bias_get_rev1(struct mtk_pinctrl *hw, 283*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup, 284*4882a593Smuzhiyun int *res); 285*4882a593Smuzhiyun int mtk_pinconf_bias_set_combo(struct mtk_pinctrl *hw, 286*4882a593Smuzhiyun const struct mtk_pin_desc *desc, 287*4882a593Smuzhiyun u32 pullup, u32 enable); 288*4882a593Smuzhiyun int mtk_pinconf_bias_get_combo(struct mtk_pinctrl *hw, 289*4882a593Smuzhiyun const struct mtk_pin_desc *desc, 290*4882a593Smuzhiyun u32 *pullup, u32 *enable); 291*4882a593Smuzhiyun 292*4882a593Smuzhiyun int mtk_pinconf_drive_set(struct mtk_pinctrl *hw, 293*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 arg); 294*4882a593Smuzhiyun int mtk_pinconf_drive_get(struct mtk_pinctrl *hw, 295*4882a593Smuzhiyun const struct mtk_pin_desc *desc, int *val); 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun int mtk_pinconf_drive_set_rev1(struct mtk_pinctrl *hw, 298*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 arg); 299*4882a593Smuzhiyun int mtk_pinconf_drive_get_rev1(struct mtk_pinctrl *hw, 300*4882a593Smuzhiyun const struct mtk_pin_desc *desc, int *val); 301*4882a593Smuzhiyun 302*4882a593Smuzhiyun int mtk_pinconf_drive_set_raw(struct mtk_pinctrl *hw, 303*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 arg); 304*4882a593Smuzhiyun int mtk_pinconf_drive_get_raw(struct mtk_pinctrl *hw, 305*4882a593Smuzhiyun const struct mtk_pin_desc *desc, int *val); 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun int mtk_pinconf_adv_pull_set(struct mtk_pinctrl *hw, 308*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup, 309*4882a593Smuzhiyun u32 arg); 310*4882a593Smuzhiyun int mtk_pinconf_adv_pull_get(struct mtk_pinctrl *hw, 311*4882a593Smuzhiyun const struct mtk_pin_desc *desc, bool pullup, 312*4882a593Smuzhiyun u32 *val); 313*4882a593Smuzhiyun int mtk_pinconf_adv_drive_set(struct mtk_pinctrl *hw, 314*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 arg); 315*4882a593Smuzhiyun int mtk_pinconf_adv_drive_get(struct mtk_pinctrl *hw, 316*4882a593Smuzhiyun const struct mtk_pin_desc *desc, u32 *val); 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun bool mtk_is_virt_gpio(struct mtk_pinctrl *hw, unsigned int gpio_n); 319*4882a593Smuzhiyun #endif /* __PINCTRL_MTK_COMMON_V2_H */ 320