1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Based on pinctrl-mt6765.c
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018 MediaTek Inc.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: ZH Chen <zh.chen@mediatek.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Copyright (C) Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include "pinctrl-mtk-mt6797.h"
14*4882a593Smuzhiyun #include "pinctrl-paris.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /*
17*4882a593Smuzhiyun * MT6797 have multiple bases to program pin configuration listed as the below:
18*4882a593Smuzhiyun * gpio:0x10005000, iocfg[l]:0x10002000, iocfg[b]:0x10002400,
19*4882a593Smuzhiyun * iocfg[r]:0x10002800, iocfg[t]:0x10002C00.
20*4882a593Smuzhiyun * _i_base could be used to indicate what base the pin should be mapped into.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun static const struct mtk_pin_field_calc mt6797_pin_mode_range[] = {
24*4882a593Smuzhiyun PIN_FIELD(0, 261, 0x300, 0x10, 0, 4),
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun static const struct mtk_pin_field_calc mt6797_pin_dir_range[] = {
28*4882a593Smuzhiyun PIN_FIELD(0, 261, 0x0, 0x10, 0, 1),
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun static const struct mtk_pin_field_calc mt6797_pin_di_range[] = {
32*4882a593Smuzhiyun PIN_FIELD(0, 261, 0x200, 0x10, 0, 1),
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun static const struct mtk_pin_field_calc mt6797_pin_do_range[] = {
36*4882a593Smuzhiyun PIN_FIELD(0, 261, 0x100, 0x10, 0, 1),
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static const struct mtk_pin_reg_calc mt6797_reg_cals[PINCTRL_PIN_REG_MAX] = {
40*4882a593Smuzhiyun [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt6797_pin_mode_range),
41*4882a593Smuzhiyun [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt6797_pin_dir_range),
42*4882a593Smuzhiyun [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt6797_pin_di_range),
43*4882a593Smuzhiyun [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt6797_pin_do_range),
44*4882a593Smuzhiyun };
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun static const char * const mt6797_pinctrl_register_base_names[] = {
47*4882a593Smuzhiyun "gpio", "iocfgl", "iocfgb", "iocfgr", "iocfgt",
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct mtk_pin_soc mt6797_data = {
51*4882a593Smuzhiyun .reg_cal = mt6797_reg_cals,
52*4882a593Smuzhiyun .pins = mtk_pins_mt6797,
53*4882a593Smuzhiyun .npins = ARRAY_SIZE(mtk_pins_mt6797),
54*4882a593Smuzhiyun .ngrps = ARRAY_SIZE(mtk_pins_mt6797),
55*4882a593Smuzhiyun .gpio_m = 0,
56*4882a593Smuzhiyun .base_names = mt6797_pinctrl_register_base_names,
57*4882a593Smuzhiyun .nbase_names = ARRAY_SIZE(mt6797_pinctrl_register_base_names),
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct of_device_id mt6797_pinctrl_of_match[] = {
61*4882a593Smuzhiyun { .compatible = "mediatek,mt6797-pinctrl", },
62*4882a593Smuzhiyun { }
63*4882a593Smuzhiyun };
64*4882a593Smuzhiyun
mt6797_pinctrl_probe(struct platform_device * pdev)65*4882a593Smuzhiyun static int mt6797_pinctrl_probe(struct platform_device *pdev)
66*4882a593Smuzhiyun {
67*4882a593Smuzhiyun return mtk_paris_pinctrl_probe(pdev, &mt6797_data);
68*4882a593Smuzhiyun }
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun static struct platform_driver mt6797_pinctrl_driver = {
71*4882a593Smuzhiyun .driver = {
72*4882a593Smuzhiyun .name = "mt6797-pinctrl",
73*4882a593Smuzhiyun .of_match_table = mt6797_pinctrl_of_match,
74*4882a593Smuzhiyun },
75*4882a593Smuzhiyun .probe = mt6797_pinctrl_probe,
76*4882a593Smuzhiyun };
77*4882a593Smuzhiyun
mt6797_pinctrl_init(void)78*4882a593Smuzhiyun static int __init mt6797_pinctrl_init(void)
79*4882a593Smuzhiyun {
80*4882a593Smuzhiyun return platform_driver_register(&mt6797_pinctrl_driver);
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun arch_initcall(mt6797_pinctrl_init);
83