1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun * Copyright 2017-2018 NXP
5*4882a593Smuzhiyun * Dong Aisheng <aisheng.dong@nxp.com>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/firmware/imx/sci.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_address.h>
12*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include "../core.h"
16*4882a593Smuzhiyun #include "pinctrl-imx.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun enum pad_func_e {
19*4882a593Smuzhiyun IMX_SC_PAD_FUNC_SET = 15,
20*4882a593Smuzhiyun IMX_SC_PAD_FUNC_GET = 16,
21*4882a593Smuzhiyun };
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun struct imx_sc_msg_req_pad_set {
24*4882a593Smuzhiyun struct imx_sc_rpc_msg hdr;
25*4882a593Smuzhiyun u32 val;
26*4882a593Smuzhiyun u16 pad;
27*4882a593Smuzhiyun } __packed __aligned(4);
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct imx_sc_msg_req_pad_get {
30*4882a593Smuzhiyun struct imx_sc_rpc_msg hdr;
31*4882a593Smuzhiyun u16 pad;
32*4882a593Smuzhiyun } __packed __aligned(4);
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun struct imx_sc_msg_resp_pad_get {
35*4882a593Smuzhiyun struct imx_sc_rpc_msg hdr;
36*4882a593Smuzhiyun u32 val;
37*4882a593Smuzhiyun } __packed;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun static struct imx_sc_ipc *pinctrl_ipc_handle;
40*4882a593Smuzhiyun
imx_pinctrl_sc_ipc_init(struct platform_device * pdev)41*4882a593Smuzhiyun int imx_pinctrl_sc_ipc_init(struct platform_device *pdev)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun return imx_scu_get_handle(&pinctrl_ipc_handle);
44*4882a593Smuzhiyun }
45*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(imx_pinctrl_sc_ipc_init);
46*4882a593Smuzhiyun
imx_pinconf_get_scu(struct pinctrl_dev * pctldev,unsigned pin_id,unsigned long * config)47*4882a593Smuzhiyun int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
48*4882a593Smuzhiyun unsigned long *config)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun struct imx_sc_msg_req_pad_get msg;
51*4882a593Smuzhiyun struct imx_sc_msg_resp_pad_get *resp;
52*4882a593Smuzhiyun struct imx_sc_rpc_msg *hdr = &msg.hdr;
53*4882a593Smuzhiyun int ret;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun hdr->ver = IMX_SC_RPC_VERSION;
56*4882a593Smuzhiyun hdr->svc = IMX_SC_RPC_SVC_PAD;
57*4882a593Smuzhiyun hdr->func = IMX_SC_PAD_FUNC_GET;
58*4882a593Smuzhiyun hdr->size = 2;
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun msg.pad = pin_id;
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
63*4882a593Smuzhiyun if (ret)
64*4882a593Smuzhiyun return ret;
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun resp = (struct imx_sc_msg_resp_pad_get *)&msg;
67*4882a593Smuzhiyun *config = resp->val;
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun return 0;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(imx_pinconf_get_scu);
72*4882a593Smuzhiyun
imx_pinconf_set_scu(struct pinctrl_dev * pctldev,unsigned pin_id,unsigned long * configs,unsigned num_configs)73*4882a593Smuzhiyun int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id,
74*4882a593Smuzhiyun unsigned long *configs, unsigned num_configs)
75*4882a593Smuzhiyun {
76*4882a593Smuzhiyun struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
77*4882a593Smuzhiyun struct imx_sc_msg_req_pad_set msg;
78*4882a593Smuzhiyun struct imx_sc_rpc_msg *hdr = &msg.hdr;
79*4882a593Smuzhiyun unsigned int mux = configs[0];
80*4882a593Smuzhiyun unsigned int conf = configs[1];
81*4882a593Smuzhiyun unsigned int val;
82*4882a593Smuzhiyun int ret;
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun * Set mux and conf together in one IPC call
86*4882a593Smuzhiyun */
87*4882a593Smuzhiyun WARN_ON(num_configs != 2);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun val = conf | BM_PAD_CTL_IFMUX_ENABLE | BM_PAD_CTL_GP_ENABLE;
90*4882a593Smuzhiyun val |= mux << BP_PAD_CTL_IFMUX;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun hdr->ver = IMX_SC_RPC_VERSION;
93*4882a593Smuzhiyun hdr->svc = IMX_SC_RPC_SVC_PAD;
94*4882a593Smuzhiyun hdr->func = IMX_SC_PAD_FUNC_SET;
95*4882a593Smuzhiyun hdr->size = 3;
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun msg.pad = pin_id;
98*4882a593Smuzhiyun msg.val = val;
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun ret = imx_scu_call_rpc(pinctrl_ipc_handle, &msg, true);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun dev_dbg(ipctl->dev, "write: pin_id %u config 0x%x val 0x%x\n",
103*4882a593Smuzhiyun pin_id, conf, val);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return ret;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(imx_pinconf_set_scu);
108*4882a593Smuzhiyun
imx_pinctrl_parse_pin_scu(struct imx_pinctrl * ipctl,unsigned int * pin_id,struct imx_pin * pin,const __be32 ** list_p)109*4882a593Smuzhiyun void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl,
110*4882a593Smuzhiyun unsigned int *pin_id, struct imx_pin *pin,
111*4882a593Smuzhiyun const __be32 **list_p)
112*4882a593Smuzhiyun {
113*4882a593Smuzhiyun const struct imx_pinctrl_soc_info *info = ipctl->info;
114*4882a593Smuzhiyun struct imx_pin_scu *pin_scu = &pin->conf.scu;
115*4882a593Smuzhiyun const __be32 *list = *list_p;
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun pin->pin = be32_to_cpu(*list++);
118*4882a593Smuzhiyun *pin_id = pin->pin;
119*4882a593Smuzhiyun pin_scu->mux_mode = be32_to_cpu(*list++);
120*4882a593Smuzhiyun pin_scu->config = be32_to_cpu(*list++);
121*4882a593Smuzhiyun *list_p = list;
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin->pin].name,
124*4882a593Smuzhiyun pin_scu->mux_mode, pin_scu->config);
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(imx_pinctrl_parse_pin_scu);
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun MODULE_AUTHOR("Dong Aisheng <aisheng.dong@nxp.com>");
129*4882a593Smuzhiyun MODULE_DESCRIPTION("NXP i.MX SCU common pinctrl driver");
130*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
131