1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright 2012 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __PINCTRL_MXS_H 7*4882a593Smuzhiyun #define __PINCTRL_MXS_H 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/platform_device.h> 10*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define SET 0x4 13*4882a593Smuzhiyun #define CLR 0x8 14*4882a593Smuzhiyun #define TOG 0xc 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define MXS_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) 17*4882a593Smuzhiyun #define PINID(bank, pin) ((bank) * 32 + (pin)) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * pinmux-id bit field definitions 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun * bank: 15..12 (4) 23*4882a593Smuzhiyun * pin: 11..4 (8) 24*4882a593Smuzhiyun * muxsel: 3..0 (4) 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define MUXID_TO_PINID(m) PINID((m) >> 12 & 0xf, (m) >> 4 & 0xff) 27*4882a593Smuzhiyun #define MUXID_TO_MUXSEL(m) ((m) & 0xf) 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define PINID_TO_BANK(p) ((p) >> 5) 30*4882a593Smuzhiyun #define PINID_TO_PIN(p) ((p) % 32) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * pin config bit field definitions 34*4882a593Smuzhiyun * 35*4882a593Smuzhiyun * pull-up: 6..5 (2) 36*4882a593Smuzhiyun * voltage: 4..3 (2) 37*4882a593Smuzhiyun * mA: 2..0 (3) 38*4882a593Smuzhiyun * 39*4882a593Smuzhiyun * MSB of each field is presence bit for the config. 40*4882a593Smuzhiyun */ 41*4882a593Smuzhiyun #define PULL_PRESENT (1 << 6) 42*4882a593Smuzhiyun #define PULL_SHIFT 5 43*4882a593Smuzhiyun #define VOL_PRESENT (1 << 4) 44*4882a593Smuzhiyun #define VOL_SHIFT 3 45*4882a593Smuzhiyun #define MA_PRESENT (1 << 2) 46*4882a593Smuzhiyun #define MA_SHIFT 0 47*4882a593Smuzhiyun #define CONFIG_TO_PULL(c) ((c) >> PULL_SHIFT & 0x1) 48*4882a593Smuzhiyun #define CONFIG_TO_VOL(c) ((c) >> VOL_SHIFT & 0x1) 49*4882a593Smuzhiyun #define CONFIG_TO_MA(c) ((c) >> MA_SHIFT & 0x3) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct mxs_function { 52*4882a593Smuzhiyun const char *name; 53*4882a593Smuzhiyun const char **groups; 54*4882a593Smuzhiyun unsigned ngroups; 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct mxs_group { 58*4882a593Smuzhiyun const char *name; 59*4882a593Smuzhiyun unsigned int *pins; 60*4882a593Smuzhiyun unsigned npins; 61*4882a593Smuzhiyun u8 *muxsel; 62*4882a593Smuzhiyun u8 config; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct mxs_regs { 66*4882a593Smuzhiyun u16 muxsel; 67*4882a593Smuzhiyun u16 drive; 68*4882a593Smuzhiyun u16 pull; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun struct mxs_pinctrl_soc_data { 72*4882a593Smuzhiyun const struct mxs_regs *regs; 73*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins; 74*4882a593Smuzhiyun unsigned npins; 75*4882a593Smuzhiyun struct mxs_function *functions; 76*4882a593Smuzhiyun unsigned nfunctions; 77*4882a593Smuzhiyun struct mxs_group *groups; 78*4882a593Smuzhiyun unsigned ngroups; 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun int mxs_pinctrl_probe(struct platform_device *pdev, 82*4882a593Smuzhiyun struct mxs_pinctrl_soc_data *soc); 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #endif /* __PINCTRL_MXS_H */ 85