1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun * Copyright 2017-2018 NXP
5*4882a593Smuzhiyun * Copyright (C) 2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/io.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #include "pinctrl-imx.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun enum imx8mq_pads {
19*4882a593Smuzhiyun MX8MQ_PAD_RESERVE0 = 0,
20*4882a593Smuzhiyun MX8MQ_PAD_RESERVE1 = 1,
21*4882a593Smuzhiyun MX8MQ_PAD_RESERVE2 = 2,
22*4882a593Smuzhiyun MX8MQ_PAD_RESERVE3 = 3,
23*4882a593Smuzhiyun MX8MQ_PAD_RESERVE4 = 4,
24*4882a593Smuzhiyun MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX = 5,
25*4882a593Smuzhiyun MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX = 6,
26*4882a593Smuzhiyun MX8MQ_IOMUXC_ONOFF_SNVSMIX = 7,
27*4882a593Smuzhiyun MX8MQ_IOMUXC_POR_B_SNVSMIX = 8,
28*4882a593Smuzhiyun MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX = 9,
29*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO00 = 10,
30*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO01 = 11,
31*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO02 = 12,
32*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO03 = 13,
33*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO04 = 14,
34*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO05 = 15,
35*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO06 = 16,
36*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO07 = 17,
37*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO08 = 18,
38*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO09 = 19,
39*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO10 = 20,
40*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO11 = 21,
41*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO12 = 22,
42*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO13 = 23,
43*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO14 = 24,
44*4882a593Smuzhiyun MX8MQ_IOMUXC_GPIO1_IO15 = 25,
45*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_MDC = 26,
46*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_MDIO = 27,
47*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_TD3 = 28,
48*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_TD2 = 29,
49*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_TD1 = 30,
50*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_TD0 = 31,
51*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_TX_CTL = 32,
52*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_TXC = 33,
53*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_RX_CTL = 34,
54*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_RXC = 35,
55*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_RD0 = 36,
56*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_RD1 = 37,
57*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_RD2 = 38,
58*4882a593Smuzhiyun MX8MQ_IOMUXC_ENET_RD3 = 39,
59*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_CLK = 40,
60*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_CMD = 41,
61*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA0 = 42,
62*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA1 = 43,
63*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA2 = 44,
64*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA3 = 45,
65*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA4 = 46,
66*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA5 = 47,
67*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA6 = 48,
68*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_DATA7 = 49,
69*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_RESET_B = 50,
70*4882a593Smuzhiyun MX8MQ_IOMUXC_SD1_STROBE = 51,
71*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CD_B = 52,
72*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CLK = 53,
73*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_CMD = 54,
74*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA0 = 55,
75*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA1 = 56,
76*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA2 = 57,
77*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_DATA3 = 58,
78*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_RESET_B = 59,
79*4882a593Smuzhiyun MX8MQ_IOMUXC_SD2_WP = 60,
80*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_ALE = 61,
81*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_CE0_B = 62,
82*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_CE1_B = 63,
83*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_CE2_B = 64,
84*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_CE3_B = 65,
85*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_CLE = 66,
86*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA00 = 67,
87*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA01 = 68,
88*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA02 = 69,
89*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA03 = 70,
90*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA04 = 71,
91*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA05 = 72,
92*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA06 = 73,
93*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DATA07 = 74,
94*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_DQS = 75,
95*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_RE_B = 76,
96*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_READY_B = 77,
97*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_WE_B = 78,
98*4882a593Smuzhiyun MX8MQ_IOMUXC_NAND_WP_B = 79,
99*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_RXFS = 80,
100*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_RXC = 81,
101*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_RXD0 = 82,
102*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_RXD1 = 83,
103*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_RXD2 = 84,
104*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_RXD3 = 85,
105*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI5_MCLK = 86,
106*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXFS = 87,
107*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXC = 88,
108*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD0 = 89,
109*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD1 = 90,
110*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD2 = 91,
111*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD3 = 92,
112*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD4 = 93,
113*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD5 = 94,
114*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD6 = 95,
115*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_RXD7 = 96,
116*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXFS = 97,
117*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXC = 98,
118*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD0 = 99,
119*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD1 = 100,
120*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD2 = 101,
121*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD3 = 102,
122*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD4 = 103,
123*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD5 = 104,
124*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD6 = 105,
125*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_TXD7 = 106,
126*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI1_MCLK = 107,
127*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_RXFS = 108,
128*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_RXC = 109,
129*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_RXD0 = 110,
130*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_TXFS = 111,
131*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_TXC = 112,
132*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_TXD0 = 113,
133*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI2_MCLK = 114,
134*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI3_RXFS = 115,
135*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI3_RXC = 116,
136*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI3_RXD = 117,
137*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI3_TXFS = 118,
138*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI3_TXC = 119,
139*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI3_TXD = 120,
140*4882a593Smuzhiyun MX8MQ_IOMUXC_SAI3_MCLK = 121,
141*4882a593Smuzhiyun MX8MQ_IOMUXC_SPDIF_TX = 122,
142*4882a593Smuzhiyun MX8MQ_IOMUXC_SPDIF_RX = 123,
143*4882a593Smuzhiyun MX8MQ_IOMUXC_SPDIF_EXT_CLK = 124,
144*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI1_SCLK = 125,
145*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI1_MOSI = 126,
146*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI1_MISO = 127,
147*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI1_SS0 = 128,
148*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI2_SCLK = 129,
149*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI2_MOSI = 130,
150*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI2_MISO = 131,
151*4882a593Smuzhiyun MX8MQ_IOMUXC_ECSPI2_SS0 = 132,
152*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C1_SCL = 133,
153*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C1_SDA = 134,
154*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C2_SCL = 135,
155*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C2_SDA = 136,
156*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C3_SCL = 137,
157*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C3_SDA = 138,
158*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C4_SCL = 139,
159*4882a593Smuzhiyun MX8MQ_IOMUXC_I2C4_SDA = 140,
160*4882a593Smuzhiyun MX8MQ_IOMUXC_UART1_RXD = 141,
161*4882a593Smuzhiyun MX8MQ_IOMUXC_UART1_TXD = 142,
162*4882a593Smuzhiyun MX8MQ_IOMUXC_UART2_RXD = 143,
163*4882a593Smuzhiyun MX8MQ_IOMUXC_UART2_TXD = 144,
164*4882a593Smuzhiyun MX8MQ_IOMUXC_UART3_RXD = 145,
165*4882a593Smuzhiyun MX8MQ_IOMUXC_UART3_TXD = 146,
166*4882a593Smuzhiyun MX8MQ_IOMUXC_UART4_RXD = 147,
167*4882a593Smuzhiyun MX8MQ_IOMUXC_UART4_TXD = 148,
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun /* Pad names for the pinmux subsystem */
171*4882a593Smuzhiyun static const struct pinctrl_pin_desc imx8mq_pinctrl_pads[] = {
172*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE0),
173*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE1),
174*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE2),
175*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE3),
176*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_PAD_RESERVE4),
177*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX),
178*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX),
179*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ONOFF_SNVSMIX),
180*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_POR_B_SNVSMIX),
181*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX),
182*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO00),
183*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO01),
184*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO02),
185*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO03),
186*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO04),
187*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO05),
188*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO06),
189*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO07),
190*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO08),
191*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO09),
192*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO10),
193*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO11),
194*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO12),
195*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO13),
196*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO14),
197*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_GPIO1_IO15),
198*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDC),
199*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_MDIO),
200*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD3),
201*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD2),
202*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD1),
203*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TD0),
204*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TX_CTL),
205*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_TXC),
206*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RX_CTL),
207*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RXC),
208*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD0),
209*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD1),
210*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD2),
211*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ENET_RD3),
212*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CLK),
213*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_CMD),
214*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA0),
215*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA1),
216*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA2),
217*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA3),
218*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA4),
219*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA5),
220*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA6),
221*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_DATA7),
222*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_RESET_B),
223*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD1_STROBE),
224*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CD_B),
225*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CLK),
226*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_CMD),
227*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA0),
228*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA1),
229*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA2),
230*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_DATA3),
231*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_RESET_B),
232*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SD2_WP),
233*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_ALE),
234*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE0_B),
235*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE1_B),
236*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE2_B),
237*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CE3_B),
238*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_CLE),
239*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA00),
240*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA01),
241*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA02),
242*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA03),
243*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA04),
244*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA05),
245*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA06),
246*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DATA07),
247*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_DQS),
248*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_RE_B),
249*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_READY_B),
250*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WE_B),
251*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_NAND_WP_B),
252*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXFS),
253*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXC),
254*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD0),
255*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD1),
256*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD2),
257*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_RXD3),
258*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI5_MCLK),
259*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXFS),
260*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXC),
261*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD0),
262*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD1),
263*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD2),
264*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD3),
265*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD4),
266*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD5),
267*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD6),
268*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_RXD7),
269*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXFS),
270*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXC),
271*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD0),
272*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD1),
273*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD2),
274*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD3),
275*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD4),
276*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD5),
277*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD6),
278*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_TXD7),
279*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI1_MCLK),
280*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXFS),
281*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXC),
282*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_RXD0),
283*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXFS),
284*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXC),
285*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_TXD0),
286*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI2_MCLK),
287*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXFS),
288*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXC),
289*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_RXD),
290*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXFS),
291*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXC),
292*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_TXD),
293*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SAI3_MCLK),
294*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_TX),
295*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_RX),
296*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_SPDIF_EXT_CLK),
297*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SCLK),
298*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MOSI),
299*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_MISO),
300*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI1_SS0),
301*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SCLK),
302*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MOSI),
303*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_MISO),
304*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_ECSPI2_SS0),
305*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SCL),
306*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C1_SDA),
307*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SCL),
308*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C2_SDA),
309*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SCL),
310*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C3_SDA),
311*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SCL),
312*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_I2C4_SDA),
313*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_RXD),
314*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART1_TXD),
315*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_RXD),
316*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART2_TXD),
317*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_RXD),
318*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART3_TXD),
319*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_RXD),
320*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX8MQ_IOMUXC_UART4_TXD),
321*4882a593Smuzhiyun };
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun static const struct imx_pinctrl_soc_info imx8mq_pinctrl_info = {
324*4882a593Smuzhiyun .pins = imx8mq_pinctrl_pads,
325*4882a593Smuzhiyun .npins = ARRAY_SIZE(imx8mq_pinctrl_pads),
326*4882a593Smuzhiyun .gpr_compatible = "fsl,imx8mq-iomuxc-gpr",
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun static const struct of_device_id imx8mq_pinctrl_of_match[] = {
330*4882a593Smuzhiyun { .compatible = "fsl,imx8mq-iomuxc", .data = &imx8mq_pinctrl_info, },
331*4882a593Smuzhiyun { /* sentinel */ }
332*4882a593Smuzhiyun };
333*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, imx8mq_pinctrl_of_match);
334*4882a593Smuzhiyun
imx8mq_pinctrl_probe(struct platform_device * pdev)335*4882a593Smuzhiyun static int imx8mq_pinctrl_probe(struct platform_device *pdev)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun return imx_pinctrl_probe(pdev, &imx8mq_pinctrl_info);
338*4882a593Smuzhiyun }
339*4882a593Smuzhiyun
340*4882a593Smuzhiyun static struct platform_driver imx8mq_pinctrl_driver = {
341*4882a593Smuzhiyun .driver = {
342*4882a593Smuzhiyun .name = "imx8mq-pinctrl",
343*4882a593Smuzhiyun .of_match_table = of_match_ptr(imx8mq_pinctrl_of_match),
344*4882a593Smuzhiyun .pm = &imx_pinctrl_pm_ops,
345*4882a593Smuzhiyun .suppress_bind_attrs = true,
346*4882a593Smuzhiyun },
347*4882a593Smuzhiyun .probe = imx8mq_pinctrl_probe,
348*4882a593Smuzhiyun };
349*4882a593Smuzhiyun
imx8mq_pinctrl_init(void)350*4882a593Smuzhiyun static int __init imx8mq_pinctrl_init(void)
351*4882a593Smuzhiyun {
352*4882a593Smuzhiyun return platform_driver_register(&imx8mq_pinctrl_driver);
353*4882a593Smuzhiyun }
354*4882a593Smuzhiyun arch_initcall(imx8mq_pinctrl_init);
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun MODULE_AUTHOR("Lucas Stach <l.stach@pengutronix.de>");
357*4882a593Smuzhiyun MODULE_DESCRIPTION("NXP i.MX8MQ pinctrl driver");
358*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
359