1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun //
3*4882a593Smuzhiyun // Copyright (C) 2016 Freescale Semiconductor, Inc.
4*4882a593Smuzhiyun // Copyright 2017-2018 NXP.
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/err.h>
7*4882a593Smuzhiyun #include <linux/init.h>
8*4882a593Smuzhiyun #include <linux/io.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/of.h>
11*4882a593Smuzhiyun #include <linux/of_device.h>
12*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include "pinctrl-imx.h"
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun enum imx6sll_pads {
17*4882a593Smuzhiyun MX6SLL_PAD_RESERVE0 = 0,
18*4882a593Smuzhiyun MX6SLL_PAD_RESERVE1 = 1,
19*4882a593Smuzhiyun MX6SLL_PAD_RESERVE2 = 2,
20*4882a593Smuzhiyun MX6SLL_PAD_RESERVE3 = 3,
21*4882a593Smuzhiyun MX6SLL_PAD_RESERVE4 = 4,
22*4882a593Smuzhiyun MX6SLL_PAD_WDOG_B = 5,
23*4882a593Smuzhiyun MX6SLL_PAD_REF_CLK_24M = 6,
24*4882a593Smuzhiyun MX6SLL_PAD_REF_CLK_32K = 7,
25*4882a593Smuzhiyun MX6SLL_PAD_PWM1 = 8,
26*4882a593Smuzhiyun MX6SLL_PAD_KEY_COL0 = 9,
27*4882a593Smuzhiyun MX6SLL_PAD_KEY_ROW0 = 10,
28*4882a593Smuzhiyun MX6SLL_PAD_KEY_COL1 = 11,
29*4882a593Smuzhiyun MX6SLL_PAD_KEY_ROW1 = 12,
30*4882a593Smuzhiyun MX6SLL_PAD_KEY_COL2 = 13,
31*4882a593Smuzhiyun MX6SLL_PAD_KEY_ROW2 = 14,
32*4882a593Smuzhiyun MX6SLL_PAD_KEY_COL3 = 15,
33*4882a593Smuzhiyun MX6SLL_PAD_KEY_ROW3 = 16,
34*4882a593Smuzhiyun MX6SLL_PAD_KEY_COL4 = 17,
35*4882a593Smuzhiyun MX6SLL_PAD_KEY_ROW4 = 18,
36*4882a593Smuzhiyun MX6SLL_PAD_KEY_COL5 = 19,
37*4882a593Smuzhiyun MX6SLL_PAD_KEY_ROW5 = 20,
38*4882a593Smuzhiyun MX6SLL_PAD_KEY_COL6 = 21,
39*4882a593Smuzhiyun MX6SLL_PAD_KEY_ROW6 = 22,
40*4882a593Smuzhiyun MX6SLL_PAD_KEY_COL7 = 23,
41*4882a593Smuzhiyun MX6SLL_PAD_KEY_ROW7 = 24,
42*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA00 = 25,
43*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA01 = 26,
44*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA02 = 27,
45*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA03 = 28,
46*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA04 = 29,
47*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA05 = 30,
48*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA06 = 31,
49*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA07 = 32,
50*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA08 = 33,
51*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA09 = 34,
52*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA10 = 35,
53*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA11 = 36,
54*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA12 = 37,
55*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA13 = 38,
56*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA14 = 39,
57*4882a593Smuzhiyun MX6SLL_PAD_EPDC_DATA15 = 40,
58*4882a593Smuzhiyun MX6SLL_PAD_EPDC_SDCLK = 41,
59*4882a593Smuzhiyun MX6SLL_PAD_EPDC_SDLE = 42,
60*4882a593Smuzhiyun MX6SLL_PAD_EPDC_SDOE = 43,
61*4882a593Smuzhiyun MX6SLL_PAD_EPDC_SDSHR = 44,
62*4882a593Smuzhiyun MX6SLL_PAD_EPDC_SDCE0 = 45,
63*4882a593Smuzhiyun MX6SLL_PAD_EPDC_SDCE1 = 46,
64*4882a593Smuzhiyun MX6SLL_PAD_EPDC_SDCE2 = 47,
65*4882a593Smuzhiyun MX6SLL_PAD_EPDC_SDCE3 = 48,
66*4882a593Smuzhiyun MX6SLL_PAD_EPDC_GDCLK = 49,
67*4882a593Smuzhiyun MX6SLL_PAD_EPDC_GDOE = 50,
68*4882a593Smuzhiyun MX6SLL_PAD_EPDC_GDRL = 51,
69*4882a593Smuzhiyun MX6SLL_PAD_EPDC_GDSP = 52,
70*4882a593Smuzhiyun MX6SLL_PAD_EPDC_VCOM0 = 53,
71*4882a593Smuzhiyun MX6SLL_PAD_EPDC_VCOM1 = 54,
72*4882a593Smuzhiyun MX6SLL_PAD_EPDC_BDR0 = 55,
73*4882a593Smuzhiyun MX6SLL_PAD_EPDC_BDR1 = 56,
74*4882a593Smuzhiyun MX6SLL_PAD_EPDC_PWR_CTRL0 = 57,
75*4882a593Smuzhiyun MX6SLL_PAD_EPDC_PWR_CTRL1 = 58,
76*4882a593Smuzhiyun MX6SLL_PAD_EPDC_PWR_CTRL2 = 59,
77*4882a593Smuzhiyun MX6SLL_PAD_EPDC_PWR_CTRL3 = 60,
78*4882a593Smuzhiyun MX6SLL_PAD_EPDC_PWR_COM = 61,
79*4882a593Smuzhiyun MX6SLL_PAD_EPDC_PWR_INT = 62,
80*4882a593Smuzhiyun MX6SLL_PAD_EPDC_PWR_STAT = 63,
81*4882a593Smuzhiyun MX6SLL_PAD_EPDC_PWR_WAKE = 64,
82*4882a593Smuzhiyun MX6SLL_PAD_LCD_CLK = 65,
83*4882a593Smuzhiyun MX6SLL_PAD_LCD_ENABLE = 66,
84*4882a593Smuzhiyun MX6SLL_PAD_LCD_HSYNC = 67,
85*4882a593Smuzhiyun MX6SLL_PAD_LCD_VSYNC = 68,
86*4882a593Smuzhiyun MX6SLL_PAD_LCD_RESET = 69,
87*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA00 = 70,
88*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA01 = 71,
89*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA02 = 72,
90*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA03 = 73,
91*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA04 = 74,
92*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA05 = 75,
93*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA06 = 76,
94*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA07 = 77,
95*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA08 = 78,
96*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA09 = 79,
97*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA10 = 80,
98*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA11 = 81,
99*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA12 = 82,
100*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA13 = 83,
101*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA14 = 84,
102*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA15 = 85,
103*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA16 = 86,
104*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA17 = 87,
105*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA18 = 88,
106*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA19 = 89,
107*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA20 = 90,
108*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA21 = 91,
109*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA22 = 92,
110*4882a593Smuzhiyun MX6SLL_PAD_LCD_DATA23 = 93,
111*4882a593Smuzhiyun MX6SLL_PAD_AUD_RXFS = 94,
112*4882a593Smuzhiyun MX6SLL_PAD_AUD_RXC = 95,
113*4882a593Smuzhiyun MX6SLL_PAD_AUD_RXD = 96,
114*4882a593Smuzhiyun MX6SLL_PAD_AUD_TXC = 97,
115*4882a593Smuzhiyun MX6SLL_PAD_AUD_TXFS = 98,
116*4882a593Smuzhiyun MX6SLL_PAD_AUD_TXD = 99,
117*4882a593Smuzhiyun MX6SLL_PAD_AUD_MCLK = 100,
118*4882a593Smuzhiyun MX6SLL_PAD_UART1_RXD = 101,
119*4882a593Smuzhiyun MX6SLL_PAD_UART1_TXD = 102,
120*4882a593Smuzhiyun MX6SLL_PAD_I2C1_SCL = 103,
121*4882a593Smuzhiyun MX6SLL_PAD_I2C1_SDA = 104,
122*4882a593Smuzhiyun MX6SLL_PAD_I2C2_SCL = 105,
123*4882a593Smuzhiyun MX6SLL_PAD_I2C2_SDA = 106,
124*4882a593Smuzhiyun MX6SLL_PAD_ECSPI1_SCLK = 107,
125*4882a593Smuzhiyun MX6SLL_PAD_ECSPI1_MOSI = 108,
126*4882a593Smuzhiyun MX6SLL_PAD_ECSPI1_MISO = 109,
127*4882a593Smuzhiyun MX6SLL_PAD_ECSPI1_SS0 = 110,
128*4882a593Smuzhiyun MX6SLL_PAD_ECSPI2_SCLK = 111,
129*4882a593Smuzhiyun MX6SLL_PAD_ECSPI2_MOSI = 112,
130*4882a593Smuzhiyun MX6SLL_PAD_ECSPI2_MISO = 113,
131*4882a593Smuzhiyun MX6SLL_PAD_ECSPI2_SS0 = 114,
132*4882a593Smuzhiyun MX6SLL_PAD_SD1_CLK = 115,
133*4882a593Smuzhiyun MX6SLL_PAD_SD1_CMD = 116,
134*4882a593Smuzhiyun MX6SLL_PAD_SD1_DATA0 = 117,
135*4882a593Smuzhiyun MX6SLL_PAD_SD1_DATA1 = 118,
136*4882a593Smuzhiyun MX6SLL_PAD_SD1_DATA2 = 119,
137*4882a593Smuzhiyun MX6SLL_PAD_SD1_DATA3 = 120,
138*4882a593Smuzhiyun MX6SLL_PAD_SD1_DATA4 = 121,
139*4882a593Smuzhiyun MX6SLL_PAD_SD1_DATA5 = 122,
140*4882a593Smuzhiyun MX6SLL_PAD_SD1_DATA6 = 123,
141*4882a593Smuzhiyun MX6SLL_PAD_SD1_DATA7 = 124,
142*4882a593Smuzhiyun MX6SLL_PAD_SD2_RESET = 125,
143*4882a593Smuzhiyun MX6SLL_PAD_SD2_CLK = 126,
144*4882a593Smuzhiyun MX6SLL_PAD_SD2_CMD = 127,
145*4882a593Smuzhiyun MX6SLL_PAD_SD2_DATA0 = 128,
146*4882a593Smuzhiyun MX6SLL_PAD_SD2_DATA1 = 129,
147*4882a593Smuzhiyun MX6SLL_PAD_SD2_DATA2 = 130,
148*4882a593Smuzhiyun MX6SLL_PAD_SD2_DATA3 = 131,
149*4882a593Smuzhiyun MX6SLL_PAD_SD2_DATA4 = 132,
150*4882a593Smuzhiyun MX6SLL_PAD_SD2_DATA5 = 133,
151*4882a593Smuzhiyun MX6SLL_PAD_SD2_DATA6 = 134,
152*4882a593Smuzhiyun MX6SLL_PAD_SD2_DATA7 = 135,
153*4882a593Smuzhiyun MX6SLL_PAD_SD3_CLK = 136,
154*4882a593Smuzhiyun MX6SLL_PAD_SD3_CMD = 137,
155*4882a593Smuzhiyun MX6SLL_PAD_SD3_DATA0 = 138,
156*4882a593Smuzhiyun MX6SLL_PAD_SD3_DATA1 = 139,
157*4882a593Smuzhiyun MX6SLL_PAD_SD3_DATA2 = 140,
158*4882a593Smuzhiyun MX6SLL_PAD_SD3_DATA3 = 141,
159*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO20 = 142,
160*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO21 = 143,
161*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO19 = 144,
162*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO25 = 145,
163*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO18 = 146,
164*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO24 = 147,
165*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO23 = 148,
166*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO17 = 149,
167*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO22 = 150,
168*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO16 = 151,
169*4882a593Smuzhiyun MX6SLL_PAD_GPIO4_IO26 = 152,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun /* Pad names for the pinmux subsystem */
173*4882a593Smuzhiyun static const struct pinctrl_pin_desc imx6sll_pinctrl_pads[] = {
174*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE0),
175*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE1),
176*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE2),
177*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE3),
178*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_RESERVE4),
179*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_WDOG_B),
180*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_24M),
181*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_REF_CLK_32K),
182*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_PWM1),
183*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL0),
184*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW0),
185*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL1),
186*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW1),
187*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL2),
188*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW2),
189*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL3),
190*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW3),
191*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL4),
192*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW4),
193*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL5),
194*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW5),
195*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL6),
196*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW6),
197*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_COL7),
198*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_KEY_ROW7),
199*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA00),
200*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA01),
201*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA02),
202*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA03),
203*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA04),
204*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA05),
205*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA06),
206*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA07),
207*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA08),
208*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA09),
209*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA10),
210*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA11),
211*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA12),
212*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA13),
213*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA14),
214*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_DATA15),
215*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCLK),
216*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDLE),
217*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDOE),
218*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDSHR),
219*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE0),
220*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE1),
221*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE2),
222*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_SDCE3),
223*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDCLK),
224*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDOE),
225*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDRL),
226*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_GDSP),
227*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM0),
228*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_VCOM1),
229*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR0),
230*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_BDR1),
231*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL0),
232*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL1),
233*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL2),
234*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_CTRL3),
235*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_COM),
236*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_INT),
237*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_STAT),
238*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_EPDC_PWR_WAKE),
239*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_CLK),
240*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_ENABLE),
241*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_HSYNC),
242*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_VSYNC),
243*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_RESET),
244*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA00),
245*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA01),
246*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA02),
247*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA03),
248*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA04),
249*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA05),
250*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA06),
251*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA07),
252*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA08),
253*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA09),
254*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA10),
255*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA11),
256*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA12),
257*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA13),
258*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA14),
259*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA15),
260*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA16),
261*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA17),
262*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA18),
263*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA19),
264*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA20),
265*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA21),
266*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA22),
267*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_LCD_DATA23),
268*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXFS),
269*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXC),
270*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_RXD),
271*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXC),
272*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXFS),
273*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_TXD),
274*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_AUD_MCLK),
275*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_RXD),
276*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_UART1_TXD),
277*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SCL),
278*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_I2C1_SDA),
279*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SCL),
280*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_I2C2_SDA),
281*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SCLK),
282*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MOSI),
283*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_MISO),
284*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI1_SS0),
285*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SCLK),
286*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MOSI),
287*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_MISO),
288*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_ECSPI2_SS0),
289*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CLK),
290*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_CMD),
291*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA0),
292*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA1),
293*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA2),
294*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA3),
295*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA4),
296*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA5),
297*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA6),
298*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD1_DATA7),
299*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_RESET),
300*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CLK),
301*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_CMD),
302*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA0),
303*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA1),
304*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA2),
305*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA3),
306*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA4),
307*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA5),
308*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA6),
309*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD2_DATA7),
310*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CLK),
311*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_CMD),
312*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA0),
313*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA1),
314*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA2),
315*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_SD3_DATA3),
316*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO20),
317*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO21),
318*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO19),
319*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO25),
320*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO18),
321*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO24),
322*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO23),
323*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO17),
324*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO22),
325*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO16),
326*4882a593Smuzhiyun IMX_PINCTRL_PIN(MX6SLL_PAD_GPIO4_IO26),
327*4882a593Smuzhiyun };
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun static const struct imx_pinctrl_soc_info imx6sll_pinctrl_info = {
330*4882a593Smuzhiyun .pins = imx6sll_pinctrl_pads,
331*4882a593Smuzhiyun .npins = ARRAY_SIZE(imx6sll_pinctrl_pads),
332*4882a593Smuzhiyun .gpr_compatible = "fsl,imx6sll-iomuxc-gpr",
333*4882a593Smuzhiyun };
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun static const struct of_device_id imx6sll_pinctrl_of_match[] = {
336*4882a593Smuzhiyun { .compatible = "fsl,imx6sll-iomuxc", .data = &imx6sll_pinctrl_info, },
337*4882a593Smuzhiyun { /* sentinel */ }
338*4882a593Smuzhiyun };
339*4882a593Smuzhiyun
imx6sll_pinctrl_probe(struct platform_device * pdev)340*4882a593Smuzhiyun static int imx6sll_pinctrl_probe(struct platform_device *pdev)
341*4882a593Smuzhiyun {
342*4882a593Smuzhiyun return imx_pinctrl_probe(pdev, &imx6sll_pinctrl_info);
343*4882a593Smuzhiyun }
344*4882a593Smuzhiyun
345*4882a593Smuzhiyun static struct platform_driver imx6sll_pinctrl_driver = {
346*4882a593Smuzhiyun .driver = {
347*4882a593Smuzhiyun .name = "imx6sll-pinctrl",
348*4882a593Smuzhiyun .of_match_table = of_match_ptr(imx6sll_pinctrl_of_match),
349*4882a593Smuzhiyun .suppress_bind_attrs = true,
350*4882a593Smuzhiyun },
351*4882a593Smuzhiyun .probe = imx6sll_pinctrl_probe,
352*4882a593Smuzhiyun };
353*4882a593Smuzhiyun
imx6sll_pinctrl_init(void)354*4882a593Smuzhiyun static int __init imx6sll_pinctrl_init(void)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun return platform_driver_register(&imx6sll_pinctrl_driver);
357*4882a593Smuzhiyun }
358*4882a593Smuzhiyun arch_initcall(imx6sll_pinctrl_init);
359