1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * IMX pinmux core definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2012 Linaro Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Dong Aisheng <dong.aisheng@linaro.org> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __DRIVERS_PINCTRL_IMX1_H 12*4882a593Smuzhiyun #define __DRIVERS_PINCTRL_IMX1_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct platform_device; 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /** 17*4882a593Smuzhiyun * struct imx1_pin - describes an IMX1/21/27 pin. 18*4882a593Smuzhiyun * @pin_id: ID of the described pin. 19*4882a593Smuzhiyun * @mux_id: ID of the mux setup. 20*4882a593Smuzhiyun * @config: Configuration of the pin (currently only pullup-enable). 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun struct imx1_pin { 23*4882a593Smuzhiyun unsigned int pin_id; 24*4882a593Smuzhiyun unsigned int mux_id; 25*4882a593Smuzhiyun unsigned long config; 26*4882a593Smuzhiyun }; 27*4882a593Smuzhiyun 28*4882a593Smuzhiyun /** 29*4882a593Smuzhiyun * struct imx1_pin_group - describes an IMX pin group 30*4882a593Smuzhiyun * @name: the name of this specific pin group 31*4882a593Smuzhiyun * @pins: an array of imx1_pin structs used in this group 32*4882a593Smuzhiyun * @npins: the number of pins in this group array, i.e. the number of 33*4882a593Smuzhiyun * elements in .pins so we can iterate over that array 34*4882a593Smuzhiyun */ 35*4882a593Smuzhiyun struct imx1_pin_group { 36*4882a593Smuzhiyun const char *name; 37*4882a593Smuzhiyun unsigned int *pin_ids; 38*4882a593Smuzhiyun struct imx1_pin *pins; 39*4882a593Smuzhiyun unsigned npins; 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /** 43*4882a593Smuzhiyun * struct imx1_pmx_func - describes IMX pinmux functions 44*4882a593Smuzhiyun * @name: the name of this specific function 45*4882a593Smuzhiyun * @groups: corresponding pin groups 46*4882a593Smuzhiyun * @num_groups: the number of groups 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun struct imx1_pmx_func { 49*4882a593Smuzhiyun const char *name; 50*4882a593Smuzhiyun const char **groups; 51*4882a593Smuzhiyun unsigned num_groups; 52*4882a593Smuzhiyun }; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct imx1_pinctrl_soc_info { 55*4882a593Smuzhiyun struct device *dev; 56*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins; 57*4882a593Smuzhiyun unsigned int npins; 58*4882a593Smuzhiyun struct imx1_pin_group *groups; 59*4882a593Smuzhiyun unsigned int ngroups; 60*4882a593Smuzhiyun struct imx1_pmx_func *functions; 61*4882a593Smuzhiyun unsigned int nfunctions; 62*4882a593Smuzhiyun }; 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun int imx1_pinctrl_core_probe(struct platform_device *pdev, 67*4882a593Smuzhiyun struct imx1_pinctrl_soc_info *info); 68*4882a593Smuzhiyun #endif /* __DRIVERS_PINCTRL_IMX1_H */ 69