1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * IMX pinmux core definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Freescale Semiconductor, Inc. 6*4882a593Smuzhiyun * Copyright (C) 2012 Linaro Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Dong Aisheng <dong.aisheng@linaro.org> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef __DRIVERS_PINCTRL_IMX_H 12*4882a593Smuzhiyun #define __DRIVERS_PINCTRL_IMX_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <linux/pinctrl/pinconf-generic.h> 15*4882a593Smuzhiyun #include <linux/pinctrl/pinmux.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun struct platform_device; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun extern struct pinmux_ops imx_pmx_ops; 20*4882a593Smuzhiyun extern const struct dev_pm_ops imx_pinctrl_pm_ops; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /** 23*4882a593Smuzhiyun * struct imx_pin_mmio - MMIO pin configurations 24*4882a593Smuzhiyun * @mux_mode: the mux mode for this pin. 25*4882a593Smuzhiyun * @input_reg: the select input register offset for this pin if any 26*4882a593Smuzhiyun * 0 if no select input setting needed. 27*4882a593Smuzhiyun * @input_val: the select input value for this pin. 28*4882a593Smuzhiyun * @configs: the config for this pin. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun struct imx_pin_mmio { 31*4882a593Smuzhiyun unsigned int mux_mode; 32*4882a593Smuzhiyun u16 input_reg; 33*4882a593Smuzhiyun unsigned int input_val; 34*4882a593Smuzhiyun unsigned long config; 35*4882a593Smuzhiyun }; 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /** 38*4882a593Smuzhiyun * struct imx_pin_scu - SCU pin configurations 39*4882a593Smuzhiyun * @mux: the mux mode for this pin. 40*4882a593Smuzhiyun * @configs: the config for this pin. 41*4882a593Smuzhiyun */ 42*4882a593Smuzhiyun struct imx_pin_scu { 43*4882a593Smuzhiyun unsigned int mux_mode; 44*4882a593Smuzhiyun unsigned long config; 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /** 48*4882a593Smuzhiyun * struct imx_pin - describes a single i.MX pin 49*4882a593Smuzhiyun * @pin: the pin_id of this pin 50*4882a593Smuzhiyun * @conf: config type of this pin, either mmio or scu 51*4882a593Smuzhiyun */ 52*4882a593Smuzhiyun struct imx_pin { 53*4882a593Smuzhiyun unsigned int pin; 54*4882a593Smuzhiyun union { 55*4882a593Smuzhiyun struct imx_pin_mmio mmio; 56*4882a593Smuzhiyun struct imx_pin_scu scu; 57*4882a593Smuzhiyun } conf; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /** 61*4882a593Smuzhiyun * struct imx_pin_reg - describe a pin reg map 62*4882a593Smuzhiyun * @mux_reg: mux register offset 63*4882a593Smuzhiyun * @conf_reg: config register offset 64*4882a593Smuzhiyun */ 65*4882a593Smuzhiyun struct imx_pin_reg { 66*4882a593Smuzhiyun s16 mux_reg; 67*4882a593Smuzhiyun s16 conf_reg; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* decode a generic config into raw register value */ 71*4882a593Smuzhiyun struct imx_cfg_params_decode { 72*4882a593Smuzhiyun enum pin_config_param param; 73*4882a593Smuzhiyun u32 mask; 74*4882a593Smuzhiyun u8 shift; 75*4882a593Smuzhiyun bool invert; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun /** 79*4882a593Smuzhiyun * @dev: a pointer back to containing device 80*4882a593Smuzhiyun * @base: the offset to the controller in virtual memory 81*4882a593Smuzhiyun */ 82*4882a593Smuzhiyun struct imx_pinctrl { 83*4882a593Smuzhiyun struct device *dev; 84*4882a593Smuzhiyun struct pinctrl_dev *pctl; 85*4882a593Smuzhiyun void __iomem *base; 86*4882a593Smuzhiyun void __iomem *input_sel_base; 87*4882a593Smuzhiyun const struct imx_pinctrl_soc_info *info; 88*4882a593Smuzhiyun struct imx_pin_reg *pin_regs; 89*4882a593Smuzhiyun unsigned int group_index; 90*4882a593Smuzhiyun struct mutex mutex; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct imx_pinctrl_soc_info { 94*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins; 95*4882a593Smuzhiyun unsigned int npins; 96*4882a593Smuzhiyun unsigned int flags; 97*4882a593Smuzhiyun const char *gpr_compatible; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */ 100*4882a593Smuzhiyun unsigned int mux_mask; 101*4882a593Smuzhiyun u8 mux_shift; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* generic pinconf */ 104*4882a593Smuzhiyun bool generic_pinconf; 105*4882a593Smuzhiyun const struct pinconf_generic_params *custom_params; 106*4882a593Smuzhiyun unsigned int num_custom_params; 107*4882a593Smuzhiyun const struct imx_cfg_params_decode *decodes; 108*4882a593Smuzhiyun unsigned int num_decodes; 109*4882a593Smuzhiyun void (*fixup)(unsigned long *configs, unsigned int num_configs, 110*4882a593Smuzhiyun u32 *raw_config); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun int (*gpio_set_direction)(struct pinctrl_dev *pctldev, 113*4882a593Smuzhiyun struct pinctrl_gpio_range *range, 114*4882a593Smuzhiyun unsigned offset, 115*4882a593Smuzhiyun bool input); 116*4882a593Smuzhiyun int (*imx_pinconf_get)(struct pinctrl_dev *pctldev, unsigned int pin_id, 117*4882a593Smuzhiyun unsigned long *config); 118*4882a593Smuzhiyun int (*imx_pinconf_set)(struct pinctrl_dev *pctldev, unsigned int pin_id, 119*4882a593Smuzhiyun unsigned long *configs, unsigned int num_configs); 120*4882a593Smuzhiyun void (*imx_pinctrl_parse_pin)(struct imx_pinctrl *ipctl, 121*4882a593Smuzhiyun unsigned int *pin_id, struct imx_pin *pin, 122*4882a593Smuzhiyun const __be32 **list_p); 123*4882a593Smuzhiyun }; 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun #define IMX_CFG_PARAMS_DECODE(p, m, o) \ 126*4882a593Smuzhiyun { .param = p, .mask = m, .shift = o, .invert = false, } 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \ 129*4882a593Smuzhiyun { .param = p, .mask = m, .shift = o, .invert = true, } 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun #define SHARE_MUX_CONF_REG BIT(0) 132*4882a593Smuzhiyun #define ZERO_OFFSET_VALID BIT(1) 133*4882a593Smuzhiyun #define IMX_USE_SCU BIT(2) 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #define NO_MUX 0x0 136*4882a593Smuzhiyun #define NO_PAD 0x0 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define PAD_CTL_MASK(len) ((1 << len) - 1) 141*4882a593Smuzhiyun #define IMX_MUX_MASK 0x7 142*4882a593Smuzhiyun #define IOMUXC_CONFIG_SION (0x1 << 4) 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun int imx_pinctrl_probe(struct platform_device *pdev, 145*4882a593Smuzhiyun const struct imx_pinctrl_soc_info *info); 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #define BM_PAD_CTL_GP_ENABLE BIT(30) 148*4882a593Smuzhiyun #define BM_PAD_CTL_IFMUX_ENABLE BIT(31) 149*4882a593Smuzhiyun #define BP_PAD_CTL_IFMUX 27 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun int imx_pinctrl_sc_ipc_init(struct platform_device *pdev); 152*4882a593Smuzhiyun int imx_pinconf_get_scu(struct pinctrl_dev *pctldev, unsigned pin_id, 153*4882a593Smuzhiyun unsigned long *config); 154*4882a593Smuzhiyun int imx_pinconf_set_scu(struct pinctrl_dev *pctldev, unsigned pin_id, 155*4882a593Smuzhiyun unsigned long *configs, unsigned num_configs); 156*4882a593Smuzhiyun void imx_pinctrl_parse_pin_scu(struct imx_pinctrl *ipctl, 157*4882a593Smuzhiyun unsigned int *pin_id, struct imx_pin *pin, 158*4882a593Smuzhiyun const __be32 **list_p); 159*4882a593Smuzhiyun #endif /* __DRIVERS_PINCTRL_IMX_H */ 160