1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Core private header for the pin control subsystem
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2011 ST-Ericsson SA
6*4882a593Smuzhiyun * Written on behalf of Linaro for ST-Ericsson
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Author: Linus Walleij <linus.walleij@linaro.org>
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/kref.h>
12*4882a593Smuzhiyun #include <linux/mutex.h>
13*4882a593Smuzhiyun #include <linux/radix-tree.h>
14*4882a593Smuzhiyun #include <linux/pinctrl/pinconf.h>
15*4882a593Smuzhiyun #include <linux/pinctrl/machine.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun struct pinctrl_gpio_range;
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun /**
20*4882a593Smuzhiyun * struct pinctrl_dev - pin control class device
21*4882a593Smuzhiyun * @node: node to include this pin controller in the global pin controller list
22*4882a593Smuzhiyun * @desc: the pin controller descriptor supplied when initializing this pin
23*4882a593Smuzhiyun * controller
24*4882a593Smuzhiyun * @pin_desc_tree: each pin descriptor for this pin controller is stored in
25*4882a593Smuzhiyun * this radix tree
26*4882a593Smuzhiyun * @pin_group_tree: optionally each pin group can be stored in this radix tree
27*4882a593Smuzhiyun * @num_groups: optionally number of groups can be kept here
28*4882a593Smuzhiyun * @pin_function_tree: optionally each function can be stored in this radix tree
29*4882a593Smuzhiyun * @num_functions: optionally number of functions can be kept here
30*4882a593Smuzhiyun * @gpio_ranges: a list of GPIO ranges that is handled by this pin controller,
31*4882a593Smuzhiyun * ranges are added to this list at runtime
32*4882a593Smuzhiyun * @dev: the device entry for this pin controller
33*4882a593Smuzhiyun * @owner: module providing the pin controller, used for refcounting
34*4882a593Smuzhiyun * @driver_data: driver data for drivers registering to the pin controller
35*4882a593Smuzhiyun * subsystem
36*4882a593Smuzhiyun * @p: result of pinctrl_get() for this device
37*4882a593Smuzhiyun * @hog_default: default state for pins hogged by this device
38*4882a593Smuzhiyun * @hog_sleep: sleep state for pins hogged by this device
39*4882a593Smuzhiyun * @mutex: mutex taken on each pin controller specific action
40*4882a593Smuzhiyun * @device_root: debugfs root for this device
41*4882a593Smuzhiyun */
42*4882a593Smuzhiyun struct pinctrl_dev {
43*4882a593Smuzhiyun struct list_head node;
44*4882a593Smuzhiyun struct pinctrl_desc *desc;
45*4882a593Smuzhiyun struct radix_tree_root pin_desc_tree;
46*4882a593Smuzhiyun #ifdef CONFIG_GENERIC_PINCTRL_GROUPS
47*4882a593Smuzhiyun struct radix_tree_root pin_group_tree;
48*4882a593Smuzhiyun unsigned int num_groups;
49*4882a593Smuzhiyun #endif
50*4882a593Smuzhiyun #ifdef CONFIG_GENERIC_PINMUX_FUNCTIONS
51*4882a593Smuzhiyun struct radix_tree_root pin_function_tree;
52*4882a593Smuzhiyun unsigned int num_functions;
53*4882a593Smuzhiyun #endif
54*4882a593Smuzhiyun struct list_head gpio_ranges;
55*4882a593Smuzhiyun struct device *dev;
56*4882a593Smuzhiyun struct module *owner;
57*4882a593Smuzhiyun void *driver_data;
58*4882a593Smuzhiyun struct pinctrl *p;
59*4882a593Smuzhiyun struct pinctrl_state *hog_default;
60*4882a593Smuzhiyun struct pinctrl_state *hog_sleep;
61*4882a593Smuzhiyun struct mutex mutex;
62*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
63*4882a593Smuzhiyun struct dentry *device_root;
64*4882a593Smuzhiyun #endif
65*4882a593Smuzhiyun };
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun /**
68*4882a593Smuzhiyun * struct pinctrl - per-device pin control state holder
69*4882a593Smuzhiyun * @node: global list node
70*4882a593Smuzhiyun * @dev: the device using this pin control handle
71*4882a593Smuzhiyun * @states: a list of states for this device
72*4882a593Smuzhiyun * @state: the current state
73*4882a593Smuzhiyun * @dt_maps: the mapping table chunks dynamically parsed from device tree for
74*4882a593Smuzhiyun * this device, if any
75*4882a593Smuzhiyun * @users: reference count
76*4882a593Smuzhiyun */
77*4882a593Smuzhiyun struct pinctrl {
78*4882a593Smuzhiyun struct list_head node;
79*4882a593Smuzhiyun struct device *dev;
80*4882a593Smuzhiyun struct list_head states;
81*4882a593Smuzhiyun struct pinctrl_state *state;
82*4882a593Smuzhiyun struct list_head dt_maps;
83*4882a593Smuzhiyun struct kref users;
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun /**
87*4882a593Smuzhiyun * struct pinctrl_state - a pinctrl state for a device
88*4882a593Smuzhiyun * @node: list node for struct pinctrl's @states field
89*4882a593Smuzhiyun * @name: the name of this state
90*4882a593Smuzhiyun * @settings: a list of settings for this state
91*4882a593Smuzhiyun */
92*4882a593Smuzhiyun struct pinctrl_state {
93*4882a593Smuzhiyun struct list_head node;
94*4882a593Smuzhiyun const char *name;
95*4882a593Smuzhiyun struct list_head settings;
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun /**
99*4882a593Smuzhiyun * struct pinctrl_setting_mux - setting data for MAP_TYPE_MUX_GROUP
100*4882a593Smuzhiyun * @group: the group selector to program
101*4882a593Smuzhiyun * @func: the function selector to program
102*4882a593Smuzhiyun */
103*4882a593Smuzhiyun struct pinctrl_setting_mux {
104*4882a593Smuzhiyun unsigned group;
105*4882a593Smuzhiyun unsigned func;
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun /**
109*4882a593Smuzhiyun * struct pinctrl_setting_configs - setting data for MAP_TYPE_CONFIGS_*
110*4882a593Smuzhiyun * @group_or_pin: the group selector or pin ID to program
111*4882a593Smuzhiyun * @configs: a pointer to an array of config parameters/values to program into
112*4882a593Smuzhiyun * hardware. Each individual pin controller defines the format and meaning
113*4882a593Smuzhiyun * of config parameters.
114*4882a593Smuzhiyun * @num_configs: the number of entries in array @configs
115*4882a593Smuzhiyun */
116*4882a593Smuzhiyun struct pinctrl_setting_configs {
117*4882a593Smuzhiyun unsigned group_or_pin;
118*4882a593Smuzhiyun unsigned long *configs;
119*4882a593Smuzhiyun unsigned num_configs;
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun /**
123*4882a593Smuzhiyun * struct pinctrl_setting - an individual mux or config setting
124*4882a593Smuzhiyun * @node: list node for struct pinctrl_settings's @settings field
125*4882a593Smuzhiyun * @type: the type of setting
126*4882a593Smuzhiyun * @pctldev: pin control device handling to be programmed. Not used for
127*4882a593Smuzhiyun * PIN_MAP_TYPE_DUMMY_STATE.
128*4882a593Smuzhiyun * @dev_name: the name of the device using this state
129*4882a593Smuzhiyun * @data: Data specific to the setting type
130*4882a593Smuzhiyun */
131*4882a593Smuzhiyun struct pinctrl_setting {
132*4882a593Smuzhiyun struct list_head node;
133*4882a593Smuzhiyun enum pinctrl_map_type type;
134*4882a593Smuzhiyun struct pinctrl_dev *pctldev;
135*4882a593Smuzhiyun const char *dev_name;
136*4882a593Smuzhiyun union {
137*4882a593Smuzhiyun struct pinctrl_setting_mux mux;
138*4882a593Smuzhiyun struct pinctrl_setting_configs configs;
139*4882a593Smuzhiyun } data;
140*4882a593Smuzhiyun };
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun /**
143*4882a593Smuzhiyun * struct pin_desc - pin descriptor for each physical pin in the arch
144*4882a593Smuzhiyun * @pctldev: corresponding pin control device
145*4882a593Smuzhiyun * @name: a name for the pin, e.g. the name of the pin/pad/finger on a
146*4882a593Smuzhiyun * datasheet or such
147*4882a593Smuzhiyun * @dynamic_name: if the name of this pin was dynamically allocated
148*4882a593Smuzhiyun * @drv_data: driver-defined per-pin data. pinctrl core does not touch this
149*4882a593Smuzhiyun * @mux_usecount: If zero, the pin is not claimed, and @owner should be NULL.
150*4882a593Smuzhiyun * If non-zero, this pin is claimed by @owner. This field is an integer
151*4882a593Smuzhiyun * rather than a boolean, since pinctrl_get() might process multiple
152*4882a593Smuzhiyun * mapping table entries that refer to, and hence claim, the same group
153*4882a593Smuzhiyun * or pin, and each of these will increment the @usecount.
154*4882a593Smuzhiyun * @mux_owner: The name of device that called pinctrl_get().
155*4882a593Smuzhiyun * @mux_setting: The most recent selected mux setting for this pin, if any.
156*4882a593Smuzhiyun * @gpio_owner: If pinctrl_gpio_request() was called for this pin, this is
157*4882a593Smuzhiyun * the name of the GPIO that "owns" this pin.
158*4882a593Smuzhiyun */
159*4882a593Smuzhiyun struct pin_desc {
160*4882a593Smuzhiyun struct pinctrl_dev *pctldev;
161*4882a593Smuzhiyun const char *name;
162*4882a593Smuzhiyun bool dynamic_name;
163*4882a593Smuzhiyun void *drv_data;
164*4882a593Smuzhiyun /* These fields only added when supporting pinmux drivers */
165*4882a593Smuzhiyun #ifdef CONFIG_PINMUX
166*4882a593Smuzhiyun unsigned mux_usecount;
167*4882a593Smuzhiyun const char *mux_owner;
168*4882a593Smuzhiyun const struct pinctrl_setting_mux *mux_setting;
169*4882a593Smuzhiyun const char *gpio_owner;
170*4882a593Smuzhiyun #endif
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun
173*4882a593Smuzhiyun /**
174*4882a593Smuzhiyun * struct pinctrl_maps - a list item containing part of the mapping table
175*4882a593Smuzhiyun * @node: mapping table list node
176*4882a593Smuzhiyun * @maps: array of mapping table entries
177*4882a593Smuzhiyun * @num_maps: the number of entries in @maps
178*4882a593Smuzhiyun */
179*4882a593Smuzhiyun struct pinctrl_maps {
180*4882a593Smuzhiyun struct list_head node;
181*4882a593Smuzhiyun const struct pinctrl_map *maps;
182*4882a593Smuzhiyun unsigned num_maps;
183*4882a593Smuzhiyun };
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun #ifdef CONFIG_GENERIC_PINCTRL_GROUPS
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun /**
188*4882a593Smuzhiyun * struct group_desc - generic pin group descriptor
189*4882a593Smuzhiyun * @name: name of the pin group
190*4882a593Smuzhiyun * @pins: array of pins that belong to the group
191*4882a593Smuzhiyun * @num_pins: number of pins in the group
192*4882a593Smuzhiyun * @data: pin controller driver specific data
193*4882a593Smuzhiyun */
194*4882a593Smuzhiyun struct group_desc {
195*4882a593Smuzhiyun const char *name;
196*4882a593Smuzhiyun int *pins;
197*4882a593Smuzhiyun int num_pins;
198*4882a593Smuzhiyun void *data;
199*4882a593Smuzhiyun };
200*4882a593Smuzhiyun
201*4882a593Smuzhiyun int pinctrl_generic_get_group_count(struct pinctrl_dev *pctldev);
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun const char *pinctrl_generic_get_group_name(struct pinctrl_dev *pctldev,
204*4882a593Smuzhiyun unsigned int group_selector);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun int pinctrl_generic_get_group_pins(struct pinctrl_dev *pctldev,
207*4882a593Smuzhiyun unsigned int group_selector,
208*4882a593Smuzhiyun const unsigned int **pins,
209*4882a593Smuzhiyun unsigned int *npins);
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun struct group_desc *pinctrl_generic_get_group(struct pinctrl_dev *pctldev,
212*4882a593Smuzhiyun unsigned int group_selector);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun int pinctrl_generic_add_group(struct pinctrl_dev *pctldev, const char *name,
215*4882a593Smuzhiyun int *gpins, int ngpins, void *data);
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun int pinctrl_generic_remove_group(struct pinctrl_dev *pctldev,
218*4882a593Smuzhiyun unsigned int group_selector);
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun #endif /* CONFIG_GENERIC_PINCTRL_GROUPS */
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun struct pinctrl_dev *get_pinctrl_dev_from_devname(const char *dev_name);
223*4882a593Smuzhiyun struct pinctrl_dev *get_pinctrl_dev_from_of_node(struct device_node *np);
224*4882a593Smuzhiyun int pin_get_from_name(struct pinctrl_dev *pctldev, const char *name);
225*4882a593Smuzhiyun const char *pin_get_name(struct pinctrl_dev *pctldev, const unsigned pin);
226*4882a593Smuzhiyun int pinctrl_get_group_selector(struct pinctrl_dev *pctldev,
227*4882a593Smuzhiyun const char *pin_group);
228*4882a593Smuzhiyun
pin_desc_get(struct pinctrl_dev * pctldev,unsigned int pin)229*4882a593Smuzhiyun static inline struct pin_desc *pin_desc_get(struct pinctrl_dev *pctldev,
230*4882a593Smuzhiyun unsigned int pin)
231*4882a593Smuzhiyun {
232*4882a593Smuzhiyun return radix_tree_lookup(&pctldev->pin_desc_tree, pin);
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun
235*4882a593Smuzhiyun extern struct pinctrl_gpio_range *
236*4882a593Smuzhiyun pinctrl_find_gpio_range_from_pin_nolock(struct pinctrl_dev *pctldev,
237*4882a593Smuzhiyun unsigned int pin);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun extern int pinctrl_force_sleep(struct pinctrl_dev *pctldev);
240*4882a593Smuzhiyun extern int pinctrl_force_default(struct pinctrl_dev *pctldev);
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun extern struct mutex pinctrl_maps_mutex;
243*4882a593Smuzhiyun extern struct list_head pinctrl_maps;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun #define for_each_maps(_maps_node_, _i_, _map_) \
246*4882a593Smuzhiyun list_for_each_entry(_maps_node_, &pinctrl_maps, node) \
247*4882a593Smuzhiyun for (_i_ = 0, _map_ = &_maps_node_->maps[_i_]; \
248*4882a593Smuzhiyun _i_ < _maps_node_->num_maps; \
249*4882a593Smuzhiyun _i_++, _map_ = &_maps_node_->maps[_i_])
250