xref: /OK3568_Linux_fs/kernel/drivers/pinctrl/cirrus/pinctrl-madera-core.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Pinctrl for Cirrus Logic Madera codecs
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2016-2018 Cirrus Logic
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/err.h>
9*4882a593Smuzhiyun #include <linux/module.h>
10*4882a593Smuzhiyun #include <linux/platform_device.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun #include <linux/slab.h>
13*4882a593Smuzhiyun #include <linux/pinctrl/machine.h>
14*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h>
15*4882a593Smuzhiyun #include <linux/pinctrl/pinmux.h>
16*4882a593Smuzhiyun #include <linux/pinctrl/pinconf.h>
17*4882a593Smuzhiyun #include <linux/pinctrl/pinconf-generic.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include <linux/mfd/madera/core.h>
20*4882a593Smuzhiyun #include <linux/mfd/madera/registers.h>
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun #include "../pinctrl-utils.h"
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #include "pinctrl-madera.h"
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun  * Use pin GPIO names for consistency
28*4882a593Smuzhiyun  * NOTE: IDs are zero-indexed for coding convenience
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun static const struct pinctrl_pin_desc madera_pins[] = {
31*4882a593Smuzhiyun 	PINCTRL_PIN(0, "gpio1"),
32*4882a593Smuzhiyun 	PINCTRL_PIN(1, "gpio2"),
33*4882a593Smuzhiyun 	PINCTRL_PIN(2, "gpio3"),
34*4882a593Smuzhiyun 	PINCTRL_PIN(3, "gpio4"),
35*4882a593Smuzhiyun 	PINCTRL_PIN(4, "gpio5"),
36*4882a593Smuzhiyun 	PINCTRL_PIN(5, "gpio6"),
37*4882a593Smuzhiyun 	PINCTRL_PIN(6, "gpio7"),
38*4882a593Smuzhiyun 	PINCTRL_PIN(7, "gpio8"),
39*4882a593Smuzhiyun 	PINCTRL_PIN(8, "gpio9"),
40*4882a593Smuzhiyun 	PINCTRL_PIN(9, "gpio10"),
41*4882a593Smuzhiyun 	PINCTRL_PIN(10, "gpio11"),
42*4882a593Smuzhiyun 	PINCTRL_PIN(11, "gpio12"),
43*4882a593Smuzhiyun 	PINCTRL_PIN(12, "gpio13"),
44*4882a593Smuzhiyun 	PINCTRL_PIN(13, "gpio14"),
45*4882a593Smuzhiyun 	PINCTRL_PIN(14, "gpio15"),
46*4882a593Smuzhiyun 	PINCTRL_PIN(15, "gpio16"),
47*4882a593Smuzhiyun 	PINCTRL_PIN(16, "gpio17"),
48*4882a593Smuzhiyun 	PINCTRL_PIN(17, "gpio18"),
49*4882a593Smuzhiyun 	PINCTRL_PIN(18, "gpio19"),
50*4882a593Smuzhiyun 	PINCTRL_PIN(19, "gpio20"),
51*4882a593Smuzhiyun 	PINCTRL_PIN(20, "gpio21"),
52*4882a593Smuzhiyun 	PINCTRL_PIN(21, "gpio22"),
53*4882a593Smuzhiyun 	PINCTRL_PIN(22, "gpio23"),
54*4882a593Smuzhiyun 	PINCTRL_PIN(23, "gpio24"),
55*4882a593Smuzhiyun 	PINCTRL_PIN(24, "gpio25"),
56*4882a593Smuzhiyun 	PINCTRL_PIN(25, "gpio26"),
57*4882a593Smuzhiyun 	PINCTRL_PIN(26, "gpio27"),
58*4882a593Smuzhiyun 	PINCTRL_PIN(27, "gpio28"),
59*4882a593Smuzhiyun 	PINCTRL_PIN(28, "gpio29"),
60*4882a593Smuzhiyun 	PINCTRL_PIN(29, "gpio30"),
61*4882a593Smuzhiyun 	PINCTRL_PIN(30, "gpio31"),
62*4882a593Smuzhiyun 	PINCTRL_PIN(31, "gpio32"),
63*4882a593Smuzhiyun 	PINCTRL_PIN(32, "gpio33"),
64*4882a593Smuzhiyun 	PINCTRL_PIN(33, "gpio34"),
65*4882a593Smuzhiyun 	PINCTRL_PIN(34, "gpio35"),
66*4882a593Smuzhiyun 	PINCTRL_PIN(35, "gpio36"),
67*4882a593Smuzhiyun 	PINCTRL_PIN(36, "gpio37"),
68*4882a593Smuzhiyun 	PINCTRL_PIN(37, "gpio38"),
69*4882a593Smuzhiyun 	PINCTRL_PIN(38, "gpio39"),
70*4882a593Smuzhiyun 	PINCTRL_PIN(39, "gpio40"),
71*4882a593Smuzhiyun };
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun /*
74*4882a593Smuzhiyun  * All single-pin functions can be mapped to any GPIO, however pinmux applies
75*4882a593Smuzhiyun  * functions to pin groups and only those groups declared as supporting that
76*4882a593Smuzhiyun  * function. To make this work we must put each pin in its own dummy group so
77*4882a593Smuzhiyun  * that the functions can be described as applying to all pins.
78*4882a593Smuzhiyun  * Since these do not correspond to anything in the actual hardware - they are
79*4882a593Smuzhiyun  * merely an adaptation to pinctrl's view of the world - we use the same name
80*4882a593Smuzhiyun  * as the pin to avoid confusion when comparing with datasheet instructions
81*4882a593Smuzhiyun  */
82*4882a593Smuzhiyun static const char * const madera_pin_single_group_names[] = {
83*4882a593Smuzhiyun 	"gpio1",  "gpio2",  "gpio3",  "gpio4",  "gpio5",  "gpio6",  "gpio7",
84*4882a593Smuzhiyun 	"gpio8",  "gpio9",  "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
85*4882a593Smuzhiyun 	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
86*4882a593Smuzhiyun 	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
87*4882a593Smuzhiyun 	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
88*4882a593Smuzhiyun 	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40",
89*4882a593Smuzhiyun };
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun /* set of pin numbers for single-pin groups, zero-indexed */
92*4882a593Smuzhiyun static const unsigned int madera_pin_single_group_pins[] = {
93*4882a593Smuzhiyun 	  0,  1,  2,  3,  4,  5,  6,
94*4882a593Smuzhiyun 	  7,  8,  9, 10, 11, 12, 13,
95*4882a593Smuzhiyun 	 14, 15, 16, 17, 18, 19, 20,
96*4882a593Smuzhiyun 	 21, 22, 23, 24, 25, 26, 27,
97*4882a593Smuzhiyun 	 28, 29, 30, 31, 32, 33, 34,
98*4882a593Smuzhiyun 	 35, 36, 37, 38, 39,
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun static const char * const madera_aif1_group_names[] = { "aif1" };
102*4882a593Smuzhiyun static const char * const madera_aif2_group_names[] = { "aif2" };
103*4882a593Smuzhiyun static const char * const madera_aif3_group_names[] = { "aif3" };
104*4882a593Smuzhiyun static const char * const madera_aif4_group_names[] = { "aif4" };
105*4882a593Smuzhiyun static const char * const madera_mif1_group_names[] = { "mif1" };
106*4882a593Smuzhiyun static const char * const madera_mif2_group_names[] = { "mif2" };
107*4882a593Smuzhiyun static const char * const madera_mif3_group_names[] = { "mif3" };
108*4882a593Smuzhiyun static const char * const madera_dmic3_group_names[] = { "dmic3" };
109*4882a593Smuzhiyun static const char * const madera_dmic4_group_names[] = { "dmic4" };
110*4882a593Smuzhiyun static const char * const madera_dmic5_group_names[] = { "dmic5" };
111*4882a593Smuzhiyun static const char * const madera_dmic6_group_names[] = { "dmic6" };
112*4882a593Smuzhiyun static const char * const madera_spk1_group_names[] = { "pdmspk1" };
113*4882a593Smuzhiyun static const char * const madera_spk2_group_names[] = { "pdmspk2" };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun /*
116*4882a593Smuzhiyun  * alt-functions always apply to a single pin group, other functions always
117*4882a593Smuzhiyun  * apply to all pins
118*4882a593Smuzhiyun  */
119*4882a593Smuzhiyun static const struct {
120*4882a593Smuzhiyun 	const char *name;
121*4882a593Smuzhiyun 	const char * const *group_names;
122*4882a593Smuzhiyun 	u32 func;
123*4882a593Smuzhiyun } madera_mux_funcs[] = {
124*4882a593Smuzhiyun 	{
125*4882a593Smuzhiyun 		.name = "aif1",
126*4882a593Smuzhiyun 		.group_names = madera_aif1_group_names,
127*4882a593Smuzhiyun 		.func = 0x000
128*4882a593Smuzhiyun 	},
129*4882a593Smuzhiyun 	{
130*4882a593Smuzhiyun 		.name = "aif2",
131*4882a593Smuzhiyun 		.group_names = madera_aif2_group_names,
132*4882a593Smuzhiyun 		.func = 0x000
133*4882a593Smuzhiyun 	},
134*4882a593Smuzhiyun 	{
135*4882a593Smuzhiyun 		.name = "aif3",
136*4882a593Smuzhiyun 		.group_names = madera_aif3_group_names,
137*4882a593Smuzhiyun 		.func = 0x000
138*4882a593Smuzhiyun 	},
139*4882a593Smuzhiyun 	{
140*4882a593Smuzhiyun 		.name = "aif4",
141*4882a593Smuzhiyun 		.group_names = madera_aif4_group_names,
142*4882a593Smuzhiyun 		.func = 0x000
143*4882a593Smuzhiyun 	},
144*4882a593Smuzhiyun 	{
145*4882a593Smuzhiyun 		.name = "mif1",
146*4882a593Smuzhiyun 		.group_names = madera_mif1_group_names,
147*4882a593Smuzhiyun 		.func = 0x000
148*4882a593Smuzhiyun 	},
149*4882a593Smuzhiyun 	{
150*4882a593Smuzhiyun 		.name = "mif2",
151*4882a593Smuzhiyun 		.group_names = madera_mif2_group_names,
152*4882a593Smuzhiyun 		.func = 0x000
153*4882a593Smuzhiyun 	},
154*4882a593Smuzhiyun 	{
155*4882a593Smuzhiyun 		.name = "mif3",
156*4882a593Smuzhiyun 		.group_names = madera_mif3_group_names,
157*4882a593Smuzhiyun 		.func = 0x000
158*4882a593Smuzhiyun 	},
159*4882a593Smuzhiyun 	{
160*4882a593Smuzhiyun 		.name = "dmic3",
161*4882a593Smuzhiyun 		.group_names = madera_dmic3_group_names,
162*4882a593Smuzhiyun 		.func = 0x000
163*4882a593Smuzhiyun 	},
164*4882a593Smuzhiyun 	{
165*4882a593Smuzhiyun 		.name = "dmic4",
166*4882a593Smuzhiyun 		.group_names = madera_dmic4_group_names,
167*4882a593Smuzhiyun 		.func = 0x000
168*4882a593Smuzhiyun 	},
169*4882a593Smuzhiyun 	{
170*4882a593Smuzhiyun 		.name = "dmic5",
171*4882a593Smuzhiyun 		.group_names = madera_dmic5_group_names,
172*4882a593Smuzhiyun 		.func = 0x000
173*4882a593Smuzhiyun 	},
174*4882a593Smuzhiyun 	{
175*4882a593Smuzhiyun 		.name = "dmic6",
176*4882a593Smuzhiyun 		.group_names = madera_dmic6_group_names,
177*4882a593Smuzhiyun 		.func = 0x000
178*4882a593Smuzhiyun 	},
179*4882a593Smuzhiyun 	{
180*4882a593Smuzhiyun 		.name = "pdmspk1",
181*4882a593Smuzhiyun 		.group_names = madera_spk1_group_names,
182*4882a593Smuzhiyun 		.func = 0x000
183*4882a593Smuzhiyun 	},
184*4882a593Smuzhiyun 	{
185*4882a593Smuzhiyun 		.name = "pdmspk2",
186*4882a593Smuzhiyun 		.group_names = madera_spk2_group_names,
187*4882a593Smuzhiyun 		.func = 0x000
188*4882a593Smuzhiyun 	},
189*4882a593Smuzhiyun 	{
190*4882a593Smuzhiyun 		.name = "io",
191*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
192*4882a593Smuzhiyun 		.func = 0x001
193*4882a593Smuzhiyun 	},
194*4882a593Smuzhiyun 	{
195*4882a593Smuzhiyun 		.name = "dsp-gpio",
196*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
197*4882a593Smuzhiyun 		.func = 0x002
198*4882a593Smuzhiyun 	},
199*4882a593Smuzhiyun 	{
200*4882a593Smuzhiyun 		.name = "irq1",
201*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
202*4882a593Smuzhiyun 		.func = 0x003
203*4882a593Smuzhiyun 	},
204*4882a593Smuzhiyun 	{
205*4882a593Smuzhiyun 		.name = "irq2",
206*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
207*4882a593Smuzhiyun 		.func = 0x004
208*4882a593Smuzhiyun 	},
209*4882a593Smuzhiyun 	{
210*4882a593Smuzhiyun 		.name = "fll1-clk",
211*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
212*4882a593Smuzhiyun 		.func = 0x010
213*4882a593Smuzhiyun 	},
214*4882a593Smuzhiyun 	{
215*4882a593Smuzhiyun 		.name = "fll2-clk",
216*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
217*4882a593Smuzhiyun 		.func = 0x011
218*4882a593Smuzhiyun 	},
219*4882a593Smuzhiyun 	{
220*4882a593Smuzhiyun 		.name = "fll3-clk",
221*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
222*4882a593Smuzhiyun 		.func = 0x012
223*4882a593Smuzhiyun 	},
224*4882a593Smuzhiyun 	{
225*4882a593Smuzhiyun 		.name = "fllao-clk",
226*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
227*4882a593Smuzhiyun 		.func = 0x013
228*4882a593Smuzhiyun 	},
229*4882a593Smuzhiyun 	{
230*4882a593Smuzhiyun 		.name = "fll1-lock",
231*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
232*4882a593Smuzhiyun 		.func = 0x018
233*4882a593Smuzhiyun 	},
234*4882a593Smuzhiyun 	{
235*4882a593Smuzhiyun 		.name = "fll2-lock",
236*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
237*4882a593Smuzhiyun 		.func = 0x019
238*4882a593Smuzhiyun 	},
239*4882a593Smuzhiyun 	{
240*4882a593Smuzhiyun 		.name = "fll3-lock",
241*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
242*4882a593Smuzhiyun 		.func = 0x01a
243*4882a593Smuzhiyun 	},
244*4882a593Smuzhiyun 	{
245*4882a593Smuzhiyun 		.name = "fllao-lock",
246*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
247*4882a593Smuzhiyun 		.func = 0x01b
248*4882a593Smuzhiyun 	},
249*4882a593Smuzhiyun 	{
250*4882a593Smuzhiyun 		.name = "opclk",
251*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
252*4882a593Smuzhiyun 		.func = 0x040
253*4882a593Smuzhiyun 	},
254*4882a593Smuzhiyun 	{
255*4882a593Smuzhiyun 		.name = "opclk-async",
256*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
257*4882a593Smuzhiyun 		.func = 0x041
258*4882a593Smuzhiyun 	},
259*4882a593Smuzhiyun 	{
260*4882a593Smuzhiyun 		.name = "pwm1",
261*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
262*4882a593Smuzhiyun 		.func = 0x048
263*4882a593Smuzhiyun 	},
264*4882a593Smuzhiyun 	{
265*4882a593Smuzhiyun 		.name = "pwm2",
266*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
267*4882a593Smuzhiyun 		.func = 0x049
268*4882a593Smuzhiyun 	},
269*4882a593Smuzhiyun 	{
270*4882a593Smuzhiyun 		.name = "spdif",
271*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
272*4882a593Smuzhiyun 		.func = 0x04c
273*4882a593Smuzhiyun 	},
274*4882a593Smuzhiyun 	{
275*4882a593Smuzhiyun 		.name = "asrc1-in1-lock",
276*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
277*4882a593Smuzhiyun 		.func = 0x088
278*4882a593Smuzhiyun 	},
279*4882a593Smuzhiyun 	{
280*4882a593Smuzhiyun 		.name = "asrc1-in2-lock",
281*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
282*4882a593Smuzhiyun 		.func = 0x089
283*4882a593Smuzhiyun 	},
284*4882a593Smuzhiyun 	{
285*4882a593Smuzhiyun 		.name = "asrc2-in1-lock",
286*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
287*4882a593Smuzhiyun 		.func = 0x08a
288*4882a593Smuzhiyun 	},
289*4882a593Smuzhiyun 	{
290*4882a593Smuzhiyun 		.name = "asrc2-in2-lock",
291*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
292*4882a593Smuzhiyun 		.func = 0x08b
293*4882a593Smuzhiyun 	},
294*4882a593Smuzhiyun 	{
295*4882a593Smuzhiyun 		.name = "spkl-short-circuit",
296*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
297*4882a593Smuzhiyun 		.func = 0x0b6
298*4882a593Smuzhiyun 	},
299*4882a593Smuzhiyun 	{
300*4882a593Smuzhiyun 		.name = "spkr-short-circuit",
301*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
302*4882a593Smuzhiyun 		.func = 0x0b7
303*4882a593Smuzhiyun 	},
304*4882a593Smuzhiyun 	{
305*4882a593Smuzhiyun 		.name = "spk-shutdown",
306*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
307*4882a593Smuzhiyun 		.func = 0x0e0
308*4882a593Smuzhiyun 	},
309*4882a593Smuzhiyun 	{
310*4882a593Smuzhiyun 		.name = "spk-overheat-shutdown",
311*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
312*4882a593Smuzhiyun 		.func = 0x0e1
313*4882a593Smuzhiyun 	},
314*4882a593Smuzhiyun 	{
315*4882a593Smuzhiyun 		.name = "spk-overheat-warn",
316*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
317*4882a593Smuzhiyun 		.func = 0x0e2
318*4882a593Smuzhiyun 	},
319*4882a593Smuzhiyun 	{
320*4882a593Smuzhiyun 		.name = "timer1-sts",
321*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
322*4882a593Smuzhiyun 		.func = 0x140
323*4882a593Smuzhiyun 	},
324*4882a593Smuzhiyun 	{
325*4882a593Smuzhiyun 		.name = "timer2-sts",
326*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
327*4882a593Smuzhiyun 		.func = 0x141
328*4882a593Smuzhiyun 	},
329*4882a593Smuzhiyun 	{
330*4882a593Smuzhiyun 		.name = "timer3-sts",
331*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
332*4882a593Smuzhiyun 		.func = 0x142
333*4882a593Smuzhiyun 	},
334*4882a593Smuzhiyun 	{
335*4882a593Smuzhiyun 		.name = "timer4-sts",
336*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
337*4882a593Smuzhiyun 		.func = 0x143
338*4882a593Smuzhiyun 	},
339*4882a593Smuzhiyun 	{
340*4882a593Smuzhiyun 		.name = "timer5-sts",
341*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
342*4882a593Smuzhiyun 		.func = 0x144
343*4882a593Smuzhiyun 	},
344*4882a593Smuzhiyun 	{
345*4882a593Smuzhiyun 		.name = "timer6-sts",
346*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
347*4882a593Smuzhiyun 		.func = 0x145
348*4882a593Smuzhiyun 	},
349*4882a593Smuzhiyun 	{
350*4882a593Smuzhiyun 		.name = "timer7-sts",
351*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
352*4882a593Smuzhiyun 		.func = 0x146
353*4882a593Smuzhiyun 	},
354*4882a593Smuzhiyun 	{
355*4882a593Smuzhiyun 		.name = "timer8-sts",
356*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
357*4882a593Smuzhiyun 		.func = 0x147
358*4882a593Smuzhiyun 	},
359*4882a593Smuzhiyun 	{
360*4882a593Smuzhiyun 		.name = "log1-fifo-ne",
361*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
362*4882a593Smuzhiyun 		.func = 0x150
363*4882a593Smuzhiyun 	},
364*4882a593Smuzhiyun 	{
365*4882a593Smuzhiyun 		.name = "log2-fifo-ne",
366*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
367*4882a593Smuzhiyun 		.func = 0x151
368*4882a593Smuzhiyun 	},
369*4882a593Smuzhiyun 	{
370*4882a593Smuzhiyun 		.name = "log3-fifo-ne",
371*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
372*4882a593Smuzhiyun 		.func = 0x152
373*4882a593Smuzhiyun 	},
374*4882a593Smuzhiyun 	{
375*4882a593Smuzhiyun 		.name = "log4-fifo-ne",
376*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
377*4882a593Smuzhiyun 		.func = 0x153
378*4882a593Smuzhiyun 	},
379*4882a593Smuzhiyun 	{
380*4882a593Smuzhiyun 		.name = "log5-fifo-ne",
381*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
382*4882a593Smuzhiyun 		.func = 0x154
383*4882a593Smuzhiyun 	},
384*4882a593Smuzhiyun 	{
385*4882a593Smuzhiyun 		.name = "log6-fifo-ne",
386*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
387*4882a593Smuzhiyun 		.func = 0x155
388*4882a593Smuzhiyun 	},
389*4882a593Smuzhiyun 	{
390*4882a593Smuzhiyun 		.name = "log7-fifo-ne",
391*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
392*4882a593Smuzhiyun 		.func = 0x156
393*4882a593Smuzhiyun 	},
394*4882a593Smuzhiyun 	{
395*4882a593Smuzhiyun 		.name = "log8-fifo-ne",
396*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
397*4882a593Smuzhiyun 		.func = 0x157
398*4882a593Smuzhiyun 	},
399*4882a593Smuzhiyun 	{
400*4882a593Smuzhiyun 		.name = "aux-pdm-clk",
401*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
402*4882a593Smuzhiyun 		.func = 0x280
403*4882a593Smuzhiyun 	},
404*4882a593Smuzhiyun 	{
405*4882a593Smuzhiyun 		.name = "aux-pdm-dat",
406*4882a593Smuzhiyun 		.group_names = madera_pin_single_group_names,
407*4882a593Smuzhiyun 		.func = 0x281
408*4882a593Smuzhiyun 	},
409*4882a593Smuzhiyun };
410*4882a593Smuzhiyun 
madera_pin_make_drv_str(struct madera_pin_private * priv,unsigned int milliamps)411*4882a593Smuzhiyun static u16 madera_pin_make_drv_str(struct madera_pin_private *priv,
412*4882a593Smuzhiyun 				      unsigned int milliamps)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun 	switch (milliamps) {
415*4882a593Smuzhiyun 	case 4:
416*4882a593Smuzhiyun 		return 0;
417*4882a593Smuzhiyun 	case 8:
418*4882a593Smuzhiyun 		return 2 << MADERA_GP1_DRV_STR_SHIFT;
419*4882a593Smuzhiyun 	default:
420*4882a593Smuzhiyun 		break;
421*4882a593Smuzhiyun 	}
422*4882a593Smuzhiyun 
423*4882a593Smuzhiyun 	dev_warn(priv->dev, "%u mA not a valid drive strength", milliamps);
424*4882a593Smuzhiyun 
425*4882a593Smuzhiyun 	return 0;
426*4882a593Smuzhiyun }
427*4882a593Smuzhiyun 
madera_pin_unmake_drv_str(struct madera_pin_private * priv,u16 regval)428*4882a593Smuzhiyun static unsigned int madera_pin_unmake_drv_str(struct madera_pin_private *priv,
429*4882a593Smuzhiyun 					      u16 regval)
430*4882a593Smuzhiyun {
431*4882a593Smuzhiyun 	regval = (regval & MADERA_GP1_DRV_STR_MASK) >> MADERA_GP1_DRV_STR_SHIFT;
432*4882a593Smuzhiyun 
433*4882a593Smuzhiyun 	switch (regval) {
434*4882a593Smuzhiyun 	case 0:
435*4882a593Smuzhiyun 		return 4;
436*4882a593Smuzhiyun 	case 2:
437*4882a593Smuzhiyun 		return 8;
438*4882a593Smuzhiyun 	default:
439*4882a593Smuzhiyun 		return 0;
440*4882a593Smuzhiyun 	}
441*4882a593Smuzhiyun }
442*4882a593Smuzhiyun 
madera_get_groups_count(struct pinctrl_dev * pctldev)443*4882a593Smuzhiyun static int madera_get_groups_count(struct pinctrl_dev *pctldev)
444*4882a593Smuzhiyun {
445*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
446*4882a593Smuzhiyun 
447*4882a593Smuzhiyun 	/* Number of alt function groups plus number of single-pin groups */
448*4882a593Smuzhiyun 	return priv->chip->n_pin_groups + priv->chip->n_pins;
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun 
madera_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)451*4882a593Smuzhiyun static const char *madera_get_group_name(struct pinctrl_dev *pctldev,
452*4882a593Smuzhiyun 					 unsigned int selector)
453*4882a593Smuzhiyun {
454*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun 	if (selector < priv->chip->n_pin_groups)
457*4882a593Smuzhiyun 		return priv->chip->pin_groups[selector].name;
458*4882a593Smuzhiyun 
459*4882a593Smuzhiyun 	selector -= priv->chip->n_pin_groups;
460*4882a593Smuzhiyun 	return madera_pin_single_group_names[selector];
461*4882a593Smuzhiyun }
462*4882a593Smuzhiyun 
madera_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)463*4882a593Smuzhiyun static int madera_get_group_pins(struct pinctrl_dev *pctldev,
464*4882a593Smuzhiyun 				 unsigned int selector,
465*4882a593Smuzhiyun 				 const unsigned int **pins,
466*4882a593Smuzhiyun 				 unsigned int *num_pins)
467*4882a593Smuzhiyun {
468*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	if (selector < priv->chip->n_pin_groups) {
471*4882a593Smuzhiyun 		*pins = priv->chip->pin_groups[selector].pins;
472*4882a593Smuzhiyun 		*num_pins = priv->chip->pin_groups[selector].n_pins;
473*4882a593Smuzhiyun 	} else {
474*4882a593Smuzhiyun 		/* return the dummy group for a single pin */
475*4882a593Smuzhiyun 		selector -= priv->chip->n_pin_groups;
476*4882a593Smuzhiyun 		*pins = &madera_pin_single_group_pins[selector];
477*4882a593Smuzhiyun 		*num_pins = 1;
478*4882a593Smuzhiyun 	}
479*4882a593Smuzhiyun 	return 0;
480*4882a593Smuzhiyun }
481*4882a593Smuzhiyun 
madera_pin_dbg_show_fn(struct madera_pin_private * priv,struct seq_file * s,unsigned int pin,unsigned int fn)482*4882a593Smuzhiyun static void madera_pin_dbg_show_fn(struct madera_pin_private *priv,
483*4882a593Smuzhiyun 				   struct seq_file *s,
484*4882a593Smuzhiyun 				   unsigned int pin, unsigned int fn)
485*4882a593Smuzhiyun {
486*4882a593Smuzhiyun 	const struct madera_pin_chip *chip = priv->chip;
487*4882a593Smuzhiyun 	int i, g_pin;
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	if (fn != 0) {
490*4882a593Smuzhiyun 		for (i = 0; i < ARRAY_SIZE(madera_mux_funcs); ++i) {
491*4882a593Smuzhiyun 			if (madera_mux_funcs[i].func == fn) {
492*4882a593Smuzhiyun 				seq_printf(s, " FN=%s",
493*4882a593Smuzhiyun 					   madera_mux_funcs[i].name);
494*4882a593Smuzhiyun 				return;
495*4882a593Smuzhiyun 			}
496*4882a593Smuzhiyun 		}
497*4882a593Smuzhiyun 		return;	/* ignore unknown function values */
498*4882a593Smuzhiyun 	}
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	/* alt function */
501*4882a593Smuzhiyun 	for (i = 0; i < chip->n_pin_groups; ++i) {
502*4882a593Smuzhiyun 		for (g_pin = 0; g_pin < chip->pin_groups[i].n_pins; ++g_pin) {
503*4882a593Smuzhiyun 			if (chip->pin_groups[i].pins[g_pin] == pin) {
504*4882a593Smuzhiyun 				seq_printf(s, " FN=%s",
505*4882a593Smuzhiyun 					   chip->pin_groups[i].name);
506*4882a593Smuzhiyun 				return;
507*4882a593Smuzhiyun 			}
508*4882a593Smuzhiyun 		}
509*4882a593Smuzhiyun 	}
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun 
madera_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned int pin)512*4882a593Smuzhiyun static void __maybe_unused madera_pin_dbg_show(struct pinctrl_dev *pctldev,
513*4882a593Smuzhiyun 					       struct seq_file *s,
514*4882a593Smuzhiyun 					       unsigned int pin)
515*4882a593Smuzhiyun {
516*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
517*4882a593Smuzhiyun 	unsigned int conf[2];
518*4882a593Smuzhiyun 	unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin);
519*4882a593Smuzhiyun 	unsigned int fn;
520*4882a593Smuzhiyun 	int ret;
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun 	ret = regmap_read(priv->madera->regmap, reg, &conf[0]);
523*4882a593Smuzhiyun 	if (ret)
524*4882a593Smuzhiyun 		return;
525*4882a593Smuzhiyun 
526*4882a593Smuzhiyun 	ret = regmap_read(priv->madera->regmap, reg + 1, &conf[1]);
527*4882a593Smuzhiyun 	if (ret)
528*4882a593Smuzhiyun 		return;
529*4882a593Smuzhiyun 
530*4882a593Smuzhiyun 	seq_printf(s, "%04x:%04x", conf[0], conf[1]);
531*4882a593Smuzhiyun 
532*4882a593Smuzhiyun 	fn = (conf[0] & MADERA_GP1_FN_MASK) >> MADERA_GP1_FN_SHIFT;
533*4882a593Smuzhiyun 	madera_pin_dbg_show_fn(priv, s, pin, fn);
534*4882a593Smuzhiyun 
535*4882a593Smuzhiyun 	/* State of direction bit is only relevant if function==1 */
536*4882a593Smuzhiyun 	if (fn == 1) {
537*4882a593Smuzhiyun 		if (conf[1] & MADERA_GP1_DIR_MASK)
538*4882a593Smuzhiyun 			seq_puts(s, " IN");
539*4882a593Smuzhiyun 		else
540*4882a593Smuzhiyun 			seq_puts(s, " OUT");
541*4882a593Smuzhiyun 	}
542*4882a593Smuzhiyun 
543*4882a593Smuzhiyun 	if (conf[1] & MADERA_GP1_PU_MASK)
544*4882a593Smuzhiyun 		seq_puts(s, " PU");
545*4882a593Smuzhiyun 
546*4882a593Smuzhiyun 	if (conf[1] & MADERA_GP1_PD_MASK)
547*4882a593Smuzhiyun 		seq_puts(s, " PD");
548*4882a593Smuzhiyun 
549*4882a593Smuzhiyun 	if (conf[0] & MADERA_GP1_DB_MASK)
550*4882a593Smuzhiyun 		seq_puts(s, " DB");
551*4882a593Smuzhiyun 
552*4882a593Smuzhiyun 	if (conf[0] & MADERA_GP1_OP_CFG_MASK)
553*4882a593Smuzhiyun 		seq_puts(s, " OD");
554*4882a593Smuzhiyun 	else
555*4882a593Smuzhiyun 		seq_puts(s, " CMOS");
556*4882a593Smuzhiyun 
557*4882a593Smuzhiyun 	seq_printf(s, " DRV=%umA", madera_pin_unmake_drv_str(priv, conf[1]));
558*4882a593Smuzhiyun 
559*4882a593Smuzhiyun 	if (conf[0] & MADERA_GP1_IP_CFG_MASK)
560*4882a593Smuzhiyun 		seq_puts(s, " SCHMITT");
561*4882a593Smuzhiyun }
562*4882a593Smuzhiyun 
563*4882a593Smuzhiyun static const struct pinctrl_ops madera_pin_group_ops = {
564*4882a593Smuzhiyun 	.get_groups_count = madera_get_groups_count,
565*4882a593Smuzhiyun 	.get_group_name = madera_get_group_name,
566*4882a593Smuzhiyun 	.get_group_pins = madera_get_group_pins,
567*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_OF)
568*4882a593Smuzhiyun 	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
569*4882a593Smuzhiyun 	.dt_free_map = pinctrl_utils_free_map,
570*4882a593Smuzhiyun #endif
571*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_DEBUG_FS)
572*4882a593Smuzhiyun 	.pin_dbg_show = madera_pin_dbg_show,
573*4882a593Smuzhiyun #endif
574*4882a593Smuzhiyun };
575*4882a593Smuzhiyun 
madera_mux_get_funcs_count(struct pinctrl_dev * pctldev)576*4882a593Smuzhiyun static int madera_mux_get_funcs_count(struct pinctrl_dev *pctldev)
577*4882a593Smuzhiyun {
578*4882a593Smuzhiyun 	return ARRAY_SIZE(madera_mux_funcs);
579*4882a593Smuzhiyun }
580*4882a593Smuzhiyun 
madera_mux_get_func_name(struct pinctrl_dev * pctldev,unsigned int selector)581*4882a593Smuzhiyun static const char *madera_mux_get_func_name(struct pinctrl_dev *pctldev,
582*4882a593Smuzhiyun 					    unsigned int selector)
583*4882a593Smuzhiyun {
584*4882a593Smuzhiyun 	return madera_mux_funcs[selector].name;
585*4882a593Smuzhiyun }
586*4882a593Smuzhiyun 
madera_mux_get_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * const num_groups)587*4882a593Smuzhiyun static int madera_mux_get_groups(struct pinctrl_dev *pctldev,
588*4882a593Smuzhiyun 				 unsigned int selector,
589*4882a593Smuzhiyun 				 const char * const **groups,
590*4882a593Smuzhiyun 				 unsigned int * const num_groups)
591*4882a593Smuzhiyun {
592*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
593*4882a593Smuzhiyun 
594*4882a593Smuzhiyun 	*groups = madera_mux_funcs[selector].group_names;
595*4882a593Smuzhiyun 
596*4882a593Smuzhiyun 	if (madera_mux_funcs[selector].func == 0) {
597*4882a593Smuzhiyun 		/* alt func always maps to a single group */
598*4882a593Smuzhiyun 		*num_groups = 1;
599*4882a593Smuzhiyun 	} else {
600*4882a593Smuzhiyun 		/* other funcs map to all available gpio pins */
601*4882a593Smuzhiyun 		*num_groups = priv->chip->n_pins;
602*4882a593Smuzhiyun 	}
603*4882a593Smuzhiyun 
604*4882a593Smuzhiyun 	return 0;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun 
madera_mux_set_mux(struct pinctrl_dev * pctldev,unsigned int selector,unsigned int group)607*4882a593Smuzhiyun static int madera_mux_set_mux(struct pinctrl_dev *pctldev,
608*4882a593Smuzhiyun 			      unsigned int selector,
609*4882a593Smuzhiyun 			      unsigned int group)
610*4882a593Smuzhiyun {
611*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
612*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
613*4882a593Smuzhiyun 	const struct madera_pin_groups *pin_group = priv->chip->pin_groups;
614*4882a593Smuzhiyun 	unsigned int n_chip_groups = priv->chip->n_pin_groups;
615*4882a593Smuzhiyun 	const char *func_name = madera_mux_funcs[selector].name;
616*4882a593Smuzhiyun 	unsigned int reg;
617*4882a593Smuzhiyun 	int i, ret = 0;
618*4882a593Smuzhiyun 
619*4882a593Smuzhiyun 	dev_dbg(priv->dev, "%s selecting %u (%s) for group %u (%s)\n",
620*4882a593Smuzhiyun 		__func__, selector, func_name, group,
621*4882a593Smuzhiyun 		madera_get_group_name(pctldev, group));
622*4882a593Smuzhiyun 
623*4882a593Smuzhiyun 	if (madera_mux_funcs[selector].func == 0) {
624*4882a593Smuzhiyun 		/* alt func pin assignments are codec-specific */
625*4882a593Smuzhiyun 		for (i = 0; i < n_chip_groups; ++i) {
626*4882a593Smuzhiyun 			if (strcmp(func_name, pin_group->name) == 0)
627*4882a593Smuzhiyun 				break;
628*4882a593Smuzhiyun 
629*4882a593Smuzhiyun 			++pin_group;
630*4882a593Smuzhiyun 		}
631*4882a593Smuzhiyun 
632*4882a593Smuzhiyun 		if (i == n_chip_groups)
633*4882a593Smuzhiyun 			return -EINVAL;
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun 		for (i = 0; i < pin_group->n_pins; ++i) {
636*4882a593Smuzhiyun 			reg = MADERA_GPIO1_CTRL_1 + (2 * pin_group->pins[i]);
637*4882a593Smuzhiyun 
638*4882a593Smuzhiyun 			dev_dbg(priv->dev, "%s setting 0x%x func bits to 0\n",
639*4882a593Smuzhiyun 				__func__, reg);
640*4882a593Smuzhiyun 
641*4882a593Smuzhiyun 			ret = regmap_update_bits(madera->regmap, reg,
642*4882a593Smuzhiyun 						 MADERA_GP1_FN_MASK, 0);
643*4882a593Smuzhiyun 			if (ret)
644*4882a593Smuzhiyun 				break;
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 		}
647*4882a593Smuzhiyun 	} else {
648*4882a593Smuzhiyun 		/*
649*4882a593Smuzhiyun 		 * for other funcs the group will be the gpio number and will
650*4882a593Smuzhiyun 		 * be offset by the number of chip-specific functions at the
651*4882a593Smuzhiyun 		 * start of the group list
652*4882a593Smuzhiyun 		 */
653*4882a593Smuzhiyun 		group -= n_chip_groups;
654*4882a593Smuzhiyun 		reg = MADERA_GPIO1_CTRL_1 + (2 * group);
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 		dev_dbg(priv->dev, "%s setting 0x%x func bits to 0x%x\n",
657*4882a593Smuzhiyun 			__func__, reg, madera_mux_funcs[selector].func);
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 		ret = regmap_update_bits(madera->regmap,
660*4882a593Smuzhiyun 					 reg,
661*4882a593Smuzhiyun 					 MADERA_GP1_FN_MASK,
662*4882a593Smuzhiyun 					 madera_mux_funcs[selector].func);
663*4882a593Smuzhiyun 	}
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	if (ret)
666*4882a593Smuzhiyun 		dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun 	return ret;
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun 
madera_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)671*4882a593Smuzhiyun static int madera_gpio_set_direction(struct pinctrl_dev *pctldev,
672*4882a593Smuzhiyun 				     struct pinctrl_gpio_range *range,
673*4882a593Smuzhiyun 				     unsigned int offset,
674*4882a593Smuzhiyun 				     bool input)
675*4882a593Smuzhiyun {
676*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
677*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
678*4882a593Smuzhiyun 	unsigned int reg = MADERA_GPIO1_CTRL_2 + (2 * offset);
679*4882a593Smuzhiyun 	unsigned int val;
680*4882a593Smuzhiyun 	int ret;
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	if (input)
683*4882a593Smuzhiyun 		val = MADERA_GP1_DIR;
684*4882a593Smuzhiyun 	else
685*4882a593Smuzhiyun 		val = 0;
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun 	ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_DIR_MASK, val);
688*4882a593Smuzhiyun 	if (ret)
689*4882a593Smuzhiyun 		dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);
690*4882a593Smuzhiyun 
691*4882a593Smuzhiyun 	return ret;
692*4882a593Smuzhiyun }
693*4882a593Smuzhiyun 
madera_gpio_request_enable(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)694*4882a593Smuzhiyun static int madera_gpio_request_enable(struct pinctrl_dev *pctldev,
695*4882a593Smuzhiyun 				      struct pinctrl_gpio_range *range,
696*4882a593Smuzhiyun 				      unsigned int offset)
697*4882a593Smuzhiyun {
698*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
699*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
700*4882a593Smuzhiyun 	unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * offset);
701*4882a593Smuzhiyun 	int ret;
702*4882a593Smuzhiyun 
703*4882a593Smuzhiyun 	/* put the pin into GPIO mode */
704*4882a593Smuzhiyun 	ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_FN_MASK, 1);
705*4882a593Smuzhiyun 	if (ret)
706*4882a593Smuzhiyun 		dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);
707*4882a593Smuzhiyun 
708*4882a593Smuzhiyun 	return ret;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun 
madera_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned int offset)711*4882a593Smuzhiyun static void madera_gpio_disable_free(struct pinctrl_dev *pctldev,
712*4882a593Smuzhiyun 				     struct pinctrl_gpio_range *range,
713*4882a593Smuzhiyun 				     unsigned int offset)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
716*4882a593Smuzhiyun 	struct madera *madera = priv->madera;
717*4882a593Smuzhiyun 	unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * offset);
718*4882a593Smuzhiyun 	int ret;
719*4882a593Smuzhiyun 
720*4882a593Smuzhiyun 	/* disable GPIO by setting to GPIO IN */
721*4882a593Smuzhiyun 	madera_gpio_set_direction(pctldev, range, offset, true);
722*4882a593Smuzhiyun 
723*4882a593Smuzhiyun 	ret = regmap_update_bits(madera->regmap, reg, MADERA_GP1_FN_MASK, 1);
724*4882a593Smuzhiyun 	if (ret)
725*4882a593Smuzhiyun 		dev_err(priv->dev, "Failed to write to 0x%x (%d)\n", reg, ret);
726*4882a593Smuzhiyun }
727*4882a593Smuzhiyun 
728*4882a593Smuzhiyun static const struct pinmux_ops madera_pin_mux_ops = {
729*4882a593Smuzhiyun 	.get_functions_count = madera_mux_get_funcs_count,
730*4882a593Smuzhiyun 	.get_function_name = madera_mux_get_func_name,
731*4882a593Smuzhiyun 	.get_function_groups = madera_mux_get_groups,
732*4882a593Smuzhiyun 	.set_mux = madera_mux_set_mux,
733*4882a593Smuzhiyun 	.gpio_request_enable = madera_gpio_request_enable,
734*4882a593Smuzhiyun 	.gpio_disable_free = madera_gpio_disable_free,
735*4882a593Smuzhiyun 	.gpio_set_direction = madera_gpio_set_direction,
736*4882a593Smuzhiyun 	.strict = true, /* GPIO and other functions are exclusive */
737*4882a593Smuzhiyun };
738*4882a593Smuzhiyun 
madera_pin_conf_get(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * config)739*4882a593Smuzhiyun static int madera_pin_conf_get(struct pinctrl_dev *pctldev, unsigned int pin,
740*4882a593Smuzhiyun 			       unsigned long *config)
741*4882a593Smuzhiyun {
742*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
743*4882a593Smuzhiyun 	unsigned int param = pinconf_to_config_param(*config);
744*4882a593Smuzhiyun 	unsigned int result = 0;
745*4882a593Smuzhiyun 	unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin);
746*4882a593Smuzhiyun 	unsigned int conf[2];
747*4882a593Smuzhiyun 	int ret;
748*4882a593Smuzhiyun 
749*4882a593Smuzhiyun 	ret = regmap_read(priv->madera->regmap, reg, &conf[0]);
750*4882a593Smuzhiyun 	if (!ret)
751*4882a593Smuzhiyun 		ret = regmap_read(priv->madera->regmap, reg + 1, &conf[1]);
752*4882a593Smuzhiyun 
753*4882a593Smuzhiyun 	if (ret) {
754*4882a593Smuzhiyun 		dev_err(priv->dev, "Failed to read GP%d conf (%d)\n",
755*4882a593Smuzhiyun 			pin + 1, ret);
756*4882a593Smuzhiyun 		return ret;
757*4882a593Smuzhiyun 	}
758*4882a593Smuzhiyun 
759*4882a593Smuzhiyun 	switch (param) {
760*4882a593Smuzhiyun 	case PIN_CONFIG_BIAS_BUS_HOLD:
761*4882a593Smuzhiyun 		conf[1] &= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
762*4882a593Smuzhiyun 		if (conf[1] == (MADERA_GP1_PU | MADERA_GP1_PD))
763*4882a593Smuzhiyun 			result = 1;
764*4882a593Smuzhiyun 		break;
765*4882a593Smuzhiyun 	case PIN_CONFIG_BIAS_DISABLE:
766*4882a593Smuzhiyun 		conf[1] &= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
767*4882a593Smuzhiyun 		if (!conf[1])
768*4882a593Smuzhiyun 			result = 1;
769*4882a593Smuzhiyun 		break;
770*4882a593Smuzhiyun 	case PIN_CONFIG_BIAS_PULL_DOWN:
771*4882a593Smuzhiyun 		conf[1] &= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
772*4882a593Smuzhiyun 		if (conf[1] == MADERA_GP1_PD_MASK)
773*4882a593Smuzhiyun 			result = 1;
774*4882a593Smuzhiyun 		break;
775*4882a593Smuzhiyun 	case PIN_CONFIG_BIAS_PULL_UP:
776*4882a593Smuzhiyun 		conf[1] &= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
777*4882a593Smuzhiyun 		if (conf[1] == MADERA_GP1_PU_MASK)
778*4882a593Smuzhiyun 			result = 1;
779*4882a593Smuzhiyun 		break;
780*4882a593Smuzhiyun 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
781*4882a593Smuzhiyun 		if (conf[0] & MADERA_GP1_OP_CFG_MASK)
782*4882a593Smuzhiyun 			result = 1;
783*4882a593Smuzhiyun 		break;
784*4882a593Smuzhiyun 	case PIN_CONFIG_DRIVE_PUSH_PULL:
785*4882a593Smuzhiyun 		if (!(conf[0] & MADERA_GP1_OP_CFG_MASK))
786*4882a593Smuzhiyun 			result = 1;
787*4882a593Smuzhiyun 		break;
788*4882a593Smuzhiyun 	case PIN_CONFIG_DRIVE_STRENGTH:
789*4882a593Smuzhiyun 		result = madera_pin_unmake_drv_str(priv, conf[1]);
790*4882a593Smuzhiyun 		break;
791*4882a593Smuzhiyun 	case PIN_CONFIG_INPUT_DEBOUNCE:
792*4882a593Smuzhiyun 		if (conf[0] & MADERA_GP1_DB_MASK)
793*4882a593Smuzhiyun 			result = 1;
794*4882a593Smuzhiyun 		break;
795*4882a593Smuzhiyun 	case PIN_CONFIG_INPUT_ENABLE:
796*4882a593Smuzhiyun 		if (conf[0] & MADERA_GP1_DIR_MASK)
797*4882a593Smuzhiyun 			result = 1;
798*4882a593Smuzhiyun 		break;
799*4882a593Smuzhiyun 	case PIN_CONFIG_INPUT_SCHMITT:
800*4882a593Smuzhiyun 	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
801*4882a593Smuzhiyun 		if (conf[0] & MADERA_GP1_IP_CFG_MASK)
802*4882a593Smuzhiyun 			result = 1;
803*4882a593Smuzhiyun 		break;
804*4882a593Smuzhiyun 	case PIN_CONFIG_OUTPUT:
805*4882a593Smuzhiyun 		if ((conf[1] & MADERA_GP1_DIR_MASK) &&
806*4882a593Smuzhiyun 		    (conf[0] & MADERA_GP1_LVL_MASK))
807*4882a593Smuzhiyun 			result = 1;
808*4882a593Smuzhiyun 		break;
809*4882a593Smuzhiyun 	default:
810*4882a593Smuzhiyun 		return -ENOTSUPP;
811*4882a593Smuzhiyun 	}
812*4882a593Smuzhiyun 
813*4882a593Smuzhiyun 	*config = pinconf_to_config_packed(param, result);
814*4882a593Smuzhiyun 
815*4882a593Smuzhiyun 	return 0;
816*4882a593Smuzhiyun }
817*4882a593Smuzhiyun 
madera_pin_conf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)818*4882a593Smuzhiyun static int madera_pin_conf_set(struct pinctrl_dev *pctldev, unsigned int pin,
819*4882a593Smuzhiyun 			       unsigned long *configs, unsigned int num_configs)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
822*4882a593Smuzhiyun 	u16 conf[2] = {0, 0};
823*4882a593Smuzhiyun 	u16 mask[2] = {0, 0};
824*4882a593Smuzhiyun 	unsigned int reg = MADERA_GPIO1_CTRL_1 + (2 * pin);
825*4882a593Smuzhiyun 	unsigned int val;
826*4882a593Smuzhiyun 	int ret;
827*4882a593Smuzhiyun 
828*4882a593Smuzhiyun 	while (num_configs) {
829*4882a593Smuzhiyun 		dev_dbg(priv->dev, "%s config 0x%lx\n", __func__, *configs);
830*4882a593Smuzhiyun 
831*4882a593Smuzhiyun 		switch (pinconf_to_config_param(*configs)) {
832*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_BUS_HOLD:
833*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
834*4882a593Smuzhiyun 			conf[1] |= MADERA_GP1_PU | MADERA_GP1_PD;
835*4882a593Smuzhiyun 			break;
836*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_DISABLE:
837*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
838*4882a593Smuzhiyun 			conf[1] &= ~(MADERA_GP1_PU | MADERA_GP1_PD);
839*4882a593Smuzhiyun 			break;
840*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_PULL_DOWN:
841*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
842*4882a593Smuzhiyun 			conf[1] |= MADERA_GP1_PD;
843*4882a593Smuzhiyun 			conf[1] &= ~MADERA_GP1_PU;
844*4882a593Smuzhiyun 			break;
845*4882a593Smuzhiyun 		case PIN_CONFIG_BIAS_PULL_UP:
846*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_PU_MASK | MADERA_GP1_PD_MASK;
847*4882a593Smuzhiyun 			conf[1] |= MADERA_GP1_PU;
848*4882a593Smuzhiyun 			conf[1] &= ~MADERA_GP1_PD;
849*4882a593Smuzhiyun 			break;
850*4882a593Smuzhiyun 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
851*4882a593Smuzhiyun 			mask[0] |= MADERA_GP1_OP_CFG_MASK;
852*4882a593Smuzhiyun 			conf[0] |= MADERA_GP1_OP_CFG;
853*4882a593Smuzhiyun 			break;
854*4882a593Smuzhiyun 		case PIN_CONFIG_DRIVE_PUSH_PULL:
855*4882a593Smuzhiyun 			mask[0] |= MADERA_GP1_OP_CFG_MASK;
856*4882a593Smuzhiyun 			conf[0] &= ~MADERA_GP1_OP_CFG;
857*4882a593Smuzhiyun 			break;
858*4882a593Smuzhiyun 		case PIN_CONFIG_DRIVE_STRENGTH:
859*4882a593Smuzhiyun 			val = pinconf_to_config_argument(*configs);
860*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_DRV_STR_MASK;
861*4882a593Smuzhiyun 			conf[1] &= ~MADERA_GP1_DRV_STR_MASK;
862*4882a593Smuzhiyun 			conf[1] |= madera_pin_make_drv_str(priv, val);
863*4882a593Smuzhiyun 			break;
864*4882a593Smuzhiyun 		case PIN_CONFIG_INPUT_DEBOUNCE:
865*4882a593Smuzhiyun 			mask[0] |= MADERA_GP1_DB_MASK;
866*4882a593Smuzhiyun 
867*4882a593Smuzhiyun 			/*
868*4882a593Smuzhiyun 			 * we can't configure debounce time per-pin so value
869*4882a593Smuzhiyun 			 * is just a flag
870*4882a593Smuzhiyun 			 */
871*4882a593Smuzhiyun 			val = pinconf_to_config_argument(*configs);
872*4882a593Smuzhiyun 			if (val)
873*4882a593Smuzhiyun 				conf[0] |= MADERA_GP1_DB;
874*4882a593Smuzhiyun 			else
875*4882a593Smuzhiyun 				conf[0] &= ~MADERA_GP1_DB;
876*4882a593Smuzhiyun 			break;
877*4882a593Smuzhiyun 		case PIN_CONFIG_INPUT_ENABLE:
878*4882a593Smuzhiyun 			val = pinconf_to_config_argument(*configs);
879*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_DIR_MASK;
880*4882a593Smuzhiyun 			if (val)
881*4882a593Smuzhiyun 				conf[1] |= MADERA_GP1_DIR;
882*4882a593Smuzhiyun 			else
883*4882a593Smuzhiyun 				conf[1] &= ~MADERA_GP1_DIR;
884*4882a593Smuzhiyun 			break;
885*4882a593Smuzhiyun 		case PIN_CONFIG_INPUT_SCHMITT:
886*4882a593Smuzhiyun 			val = pinconf_to_config_argument(*configs);
887*4882a593Smuzhiyun 			mask[0] |= MADERA_GP1_IP_CFG;
888*4882a593Smuzhiyun 			if (val)
889*4882a593Smuzhiyun 				conf[0] |= MADERA_GP1_IP_CFG;
890*4882a593Smuzhiyun 			else
891*4882a593Smuzhiyun 				conf[0] &= ~MADERA_GP1_IP_CFG;
892*4882a593Smuzhiyun 
893*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_DIR_MASK;
894*4882a593Smuzhiyun 			conf[1] |= MADERA_GP1_DIR;
895*4882a593Smuzhiyun 			break;
896*4882a593Smuzhiyun 		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
897*4882a593Smuzhiyun 			mask[0] |= MADERA_GP1_IP_CFG;
898*4882a593Smuzhiyun 			conf[0] |= MADERA_GP1_IP_CFG;
899*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_DIR_MASK;
900*4882a593Smuzhiyun 			conf[1] |= MADERA_GP1_DIR;
901*4882a593Smuzhiyun 			break;
902*4882a593Smuzhiyun 		case PIN_CONFIG_OUTPUT:
903*4882a593Smuzhiyun 			val = pinconf_to_config_argument(*configs);
904*4882a593Smuzhiyun 			mask[0] |= MADERA_GP1_LVL_MASK;
905*4882a593Smuzhiyun 			if (val)
906*4882a593Smuzhiyun 				conf[0] |= MADERA_GP1_LVL;
907*4882a593Smuzhiyun 			else
908*4882a593Smuzhiyun 				conf[0] &= ~MADERA_GP1_LVL;
909*4882a593Smuzhiyun 
910*4882a593Smuzhiyun 			mask[1] |= MADERA_GP1_DIR_MASK;
911*4882a593Smuzhiyun 			conf[1] &= ~MADERA_GP1_DIR;
912*4882a593Smuzhiyun 			break;
913*4882a593Smuzhiyun 		default:
914*4882a593Smuzhiyun 			return -ENOTSUPP;
915*4882a593Smuzhiyun 		}
916*4882a593Smuzhiyun 
917*4882a593Smuzhiyun 		++configs;
918*4882a593Smuzhiyun 		--num_configs;
919*4882a593Smuzhiyun 	}
920*4882a593Smuzhiyun 
921*4882a593Smuzhiyun 	dev_dbg(priv->dev,
922*4882a593Smuzhiyun 		"%s gpio%d 0x%x:0x%x 0x%x:0x%x\n",
923*4882a593Smuzhiyun 		__func__, pin + 1, reg, conf[0], reg + 1, conf[1]);
924*4882a593Smuzhiyun 
925*4882a593Smuzhiyun 	ret = regmap_update_bits(priv->madera->regmap, reg, mask[0], conf[0]);
926*4882a593Smuzhiyun 	if (ret)
927*4882a593Smuzhiyun 		goto err;
928*4882a593Smuzhiyun 
929*4882a593Smuzhiyun 	++reg;
930*4882a593Smuzhiyun 	ret = regmap_update_bits(priv->madera->regmap, reg, mask[1], conf[1]);
931*4882a593Smuzhiyun 	if (ret)
932*4882a593Smuzhiyun 		goto err;
933*4882a593Smuzhiyun 
934*4882a593Smuzhiyun 	return 0;
935*4882a593Smuzhiyun 
936*4882a593Smuzhiyun err:
937*4882a593Smuzhiyun 	dev_err(priv->dev,
938*4882a593Smuzhiyun 		"Failed to write GPIO%d conf (%d) reg 0x%x\n",
939*4882a593Smuzhiyun 		pin + 1, ret, reg);
940*4882a593Smuzhiyun 
941*4882a593Smuzhiyun 	return ret;
942*4882a593Smuzhiyun }
943*4882a593Smuzhiyun 
madera_pin_conf_group_set(struct pinctrl_dev * pctldev,unsigned int selector,unsigned long * configs,unsigned int num_configs)944*4882a593Smuzhiyun static int madera_pin_conf_group_set(struct pinctrl_dev *pctldev,
945*4882a593Smuzhiyun 				     unsigned int selector,
946*4882a593Smuzhiyun 				     unsigned long *configs,
947*4882a593Smuzhiyun 				     unsigned int num_configs)
948*4882a593Smuzhiyun {
949*4882a593Smuzhiyun 	struct madera_pin_private *priv = pinctrl_dev_get_drvdata(pctldev);
950*4882a593Smuzhiyun 	const struct madera_pin_groups *pin_group;
951*4882a593Smuzhiyun 	unsigned int n_groups = priv->chip->n_pin_groups;
952*4882a593Smuzhiyun 	int i, ret;
953*4882a593Smuzhiyun 
954*4882a593Smuzhiyun 	dev_dbg(priv->dev, "%s setting group %s\n", __func__,
955*4882a593Smuzhiyun 		madera_get_group_name(pctldev, selector));
956*4882a593Smuzhiyun 
957*4882a593Smuzhiyun 	if (selector >= n_groups) {
958*4882a593Smuzhiyun 		/* group is a single pin, convert to pin number and set */
959*4882a593Smuzhiyun 		return madera_pin_conf_set(pctldev,
960*4882a593Smuzhiyun 					   selector - n_groups,
961*4882a593Smuzhiyun 					   configs,
962*4882a593Smuzhiyun 					   num_configs);
963*4882a593Smuzhiyun 	} else {
964*4882a593Smuzhiyun 		pin_group = &priv->chip->pin_groups[selector];
965*4882a593Smuzhiyun 
966*4882a593Smuzhiyun 		for (i = 0; i < pin_group->n_pins; ++i) {
967*4882a593Smuzhiyun 			ret = madera_pin_conf_set(pctldev,
968*4882a593Smuzhiyun 						  pin_group->pins[i],
969*4882a593Smuzhiyun 						  configs,
970*4882a593Smuzhiyun 						  num_configs);
971*4882a593Smuzhiyun 			if (ret)
972*4882a593Smuzhiyun 				return ret;
973*4882a593Smuzhiyun 		}
974*4882a593Smuzhiyun 	}
975*4882a593Smuzhiyun 
976*4882a593Smuzhiyun 	return 0;
977*4882a593Smuzhiyun }
978*4882a593Smuzhiyun 
979*4882a593Smuzhiyun static const struct pinconf_ops madera_pin_conf_ops = {
980*4882a593Smuzhiyun 	.is_generic = true,
981*4882a593Smuzhiyun 	.pin_config_get = madera_pin_conf_get,
982*4882a593Smuzhiyun 	.pin_config_set = madera_pin_conf_set,
983*4882a593Smuzhiyun 	.pin_config_group_set = madera_pin_conf_group_set,
984*4882a593Smuzhiyun };
985*4882a593Smuzhiyun 
986*4882a593Smuzhiyun static struct pinctrl_desc madera_pin_desc = {
987*4882a593Smuzhiyun 	.name = "madera-pinctrl",
988*4882a593Smuzhiyun 	.pins = madera_pins,
989*4882a593Smuzhiyun 	.pctlops = &madera_pin_group_ops,
990*4882a593Smuzhiyun 	.pmxops = &madera_pin_mux_ops,
991*4882a593Smuzhiyun 	.confops = &madera_pin_conf_ops,
992*4882a593Smuzhiyun 	.owner = THIS_MODULE,
993*4882a593Smuzhiyun };
994*4882a593Smuzhiyun 
madera_pin_probe(struct platform_device * pdev)995*4882a593Smuzhiyun static int madera_pin_probe(struct platform_device *pdev)
996*4882a593Smuzhiyun {
997*4882a593Smuzhiyun 	struct madera *madera = dev_get_drvdata(pdev->dev.parent);
998*4882a593Smuzhiyun 	const struct madera_pdata *pdata = &madera->pdata;
999*4882a593Smuzhiyun 	struct madera_pin_private *priv;
1000*4882a593Smuzhiyun 	int ret;
1001*4882a593Smuzhiyun 
1002*4882a593Smuzhiyun 	BUILD_BUG_ON(ARRAY_SIZE(madera_pin_single_group_names) !=
1003*4882a593Smuzhiyun 		     ARRAY_SIZE(madera_pin_single_group_pins));
1004*4882a593Smuzhiyun 
1005*4882a593Smuzhiyun 	dev_dbg(&pdev->dev, "%s\n", __func__);
1006*4882a593Smuzhiyun 
1007*4882a593Smuzhiyun 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1008*4882a593Smuzhiyun 	if (!priv)
1009*4882a593Smuzhiyun 		return -ENOMEM;
1010*4882a593Smuzhiyun 
1011*4882a593Smuzhiyun 	priv->dev = &pdev->dev;
1012*4882a593Smuzhiyun 	priv->madera = madera;
1013*4882a593Smuzhiyun 	pdev->dev.of_node = madera->dev->of_node;
1014*4882a593Smuzhiyun 
1015*4882a593Smuzhiyun 	switch (madera->type) {
1016*4882a593Smuzhiyun 	case CS47L15:
1017*4882a593Smuzhiyun 		if (IS_ENABLED(CONFIG_PINCTRL_CS47L15))
1018*4882a593Smuzhiyun 			priv->chip = &cs47l15_pin_chip;
1019*4882a593Smuzhiyun 		break;
1020*4882a593Smuzhiyun 	case CS47L35:
1021*4882a593Smuzhiyun 		if (IS_ENABLED(CONFIG_PINCTRL_CS47L35))
1022*4882a593Smuzhiyun 			priv->chip = &cs47l35_pin_chip;
1023*4882a593Smuzhiyun 		break;
1024*4882a593Smuzhiyun 	case CS47L85:
1025*4882a593Smuzhiyun 	case WM1840:
1026*4882a593Smuzhiyun 		if (IS_ENABLED(CONFIG_PINCTRL_CS47L85))
1027*4882a593Smuzhiyun 			priv->chip = &cs47l85_pin_chip;
1028*4882a593Smuzhiyun 		break;
1029*4882a593Smuzhiyun 	case CS47L90:
1030*4882a593Smuzhiyun 	case CS47L91:
1031*4882a593Smuzhiyun 		if (IS_ENABLED(CONFIG_PINCTRL_CS47L90))
1032*4882a593Smuzhiyun 			priv->chip = &cs47l90_pin_chip;
1033*4882a593Smuzhiyun 		break;
1034*4882a593Smuzhiyun 	case CS42L92:
1035*4882a593Smuzhiyun 	case CS47L92:
1036*4882a593Smuzhiyun 	case CS47L93:
1037*4882a593Smuzhiyun 		if (IS_ENABLED(CONFIG_PINCTRL_CS47L92))
1038*4882a593Smuzhiyun 			priv->chip = &cs47l92_pin_chip;
1039*4882a593Smuzhiyun 		break;
1040*4882a593Smuzhiyun 	default:
1041*4882a593Smuzhiyun 		break;
1042*4882a593Smuzhiyun 	}
1043*4882a593Smuzhiyun 
1044*4882a593Smuzhiyun 	if (!priv->chip)
1045*4882a593Smuzhiyun 		return -ENODEV;
1046*4882a593Smuzhiyun 
1047*4882a593Smuzhiyun 	madera_pin_desc.npins = priv->chip->n_pins;
1048*4882a593Smuzhiyun 
1049*4882a593Smuzhiyun 	ret = devm_pinctrl_register_and_init(&pdev->dev,
1050*4882a593Smuzhiyun 					     &madera_pin_desc,
1051*4882a593Smuzhiyun 					     priv,
1052*4882a593Smuzhiyun 					     &priv->pctl);
1053*4882a593Smuzhiyun 	if (ret) {
1054*4882a593Smuzhiyun 		dev_err(priv->dev, "Failed pinctrl register (%d)\n", ret);
1055*4882a593Smuzhiyun 		return ret;
1056*4882a593Smuzhiyun 	}
1057*4882a593Smuzhiyun 
1058*4882a593Smuzhiyun 	/* if the configuration is provided through pdata, apply it */
1059*4882a593Smuzhiyun 	if (pdata->gpio_configs) {
1060*4882a593Smuzhiyun 		ret = pinctrl_register_mappings(pdata->gpio_configs,
1061*4882a593Smuzhiyun 						pdata->n_gpio_configs);
1062*4882a593Smuzhiyun 		if (ret) {
1063*4882a593Smuzhiyun 			dev_err(priv->dev,
1064*4882a593Smuzhiyun 				"Failed to register pdata mappings (%d)\n",
1065*4882a593Smuzhiyun 				ret);
1066*4882a593Smuzhiyun 			return ret;
1067*4882a593Smuzhiyun 		}
1068*4882a593Smuzhiyun 	}
1069*4882a593Smuzhiyun 
1070*4882a593Smuzhiyun 	ret = pinctrl_enable(priv->pctl);
1071*4882a593Smuzhiyun 	if (ret) {
1072*4882a593Smuzhiyun 		dev_err(priv->dev, "Failed to enable pinctrl (%d)\n", ret);
1073*4882a593Smuzhiyun 		return ret;
1074*4882a593Smuzhiyun 	}
1075*4882a593Smuzhiyun 
1076*4882a593Smuzhiyun 	platform_set_drvdata(pdev, priv);
1077*4882a593Smuzhiyun 
1078*4882a593Smuzhiyun 	dev_dbg(priv->dev, "pinctrl probed ok\n");
1079*4882a593Smuzhiyun 
1080*4882a593Smuzhiyun 	return 0;
1081*4882a593Smuzhiyun }
1082*4882a593Smuzhiyun 
madera_pin_remove(struct platform_device * pdev)1083*4882a593Smuzhiyun static int madera_pin_remove(struct platform_device *pdev)
1084*4882a593Smuzhiyun {
1085*4882a593Smuzhiyun 	struct madera_pin_private *priv = platform_get_drvdata(pdev);
1086*4882a593Smuzhiyun 
1087*4882a593Smuzhiyun 	if (priv->madera->pdata.gpio_configs)
1088*4882a593Smuzhiyun 		pinctrl_unregister_mappings(priv->madera->pdata.gpio_configs);
1089*4882a593Smuzhiyun 
1090*4882a593Smuzhiyun 	return 0;
1091*4882a593Smuzhiyun }
1092*4882a593Smuzhiyun 
1093*4882a593Smuzhiyun static struct platform_driver madera_pin_driver = {
1094*4882a593Smuzhiyun 	.probe = madera_pin_probe,
1095*4882a593Smuzhiyun 	.remove = madera_pin_remove,
1096*4882a593Smuzhiyun 	.driver = {
1097*4882a593Smuzhiyun 		.name = "madera-pinctrl",
1098*4882a593Smuzhiyun 	},
1099*4882a593Smuzhiyun };
1100*4882a593Smuzhiyun 
1101*4882a593Smuzhiyun module_platform_driver(madera_pin_driver);
1102*4882a593Smuzhiyun 
1103*4882a593Smuzhiyun MODULE_DESCRIPTION("Madera pinctrl driver");
1104*4882a593Smuzhiyun MODULE_AUTHOR("Richard Fitzgerald <rf@opensource.cirrus.com>");
1105*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
1106