1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Pinctrl for Cirrus Logic CS47L85 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016-2017 Cirrus Logic 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/err.h> 9*4882a593Smuzhiyun #include <linux/mfd/madera/core.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "pinctrl-madera.h" 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* 14*4882a593Smuzhiyun * The alt func groups are the most commonly used functions we place these at 15*4882a593Smuzhiyun * the lower function indexes for convenience, and the less commonly used gpio 16*4882a593Smuzhiyun * functions at higher indexes. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * To stay consistent with the datasheet the function names are the same as 19*4882a593Smuzhiyun * the group names for that function's pins 20*4882a593Smuzhiyun * 21*4882a593Smuzhiyun * Note - all 1 less than in datasheet because these are zero-indexed 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun static const unsigned int cs47l85_mif1_pins[] = { 8, 9 }; 24*4882a593Smuzhiyun static const unsigned int cs47l85_mif2_pins[] = { 10, 11 }; 25*4882a593Smuzhiyun static const unsigned int cs47l85_mif3_pins[] = { 12, 13 }; 26*4882a593Smuzhiyun static const unsigned int cs47l85_aif1_pins[] = { 14, 15, 16, 17 }; 27*4882a593Smuzhiyun static const unsigned int cs47l85_aif2_pins[] = { 18, 19, 20, 21 }; 28*4882a593Smuzhiyun static const unsigned int cs47l85_aif3_pins[] = { 22, 23, 24, 25 }; 29*4882a593Smuzhiyun static const unsigned int cs47l85_aif4_pins[] = { 26, 27, 28, 29 }; 30*4882a593Smuzhiyun static const unsigned int cs47l85_dmic4_pins[] = { 30, 31 }; 31*4882a593Smuzhiyun static const unsigned int cs47l85_dmic5_pins[] = { 32, 33 }; 32*4882a593Smuzhiyun static const unsigned int cs47l85_dmic6_pins[] = { 34, 35 }; 33*4882a593Smuzhiyun static const unsigned int cs47l85_spk1_pins[] = { 36, 38 }; 34*4882a593Smuzhiyun static const unsigned int cs47l85_spk2_pins[] = { 37, 39 }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun static const struct madera_pin_groups cs47l85_pin_groups[] = { 37*4882a593Smuzhiyun { "aif1", cs47l85_aif1_pins, ARRAY_SIZE(cs47l85_aif1_pins) }, 38*4882a593Smuzhiyun { "aif2", cs47l85_aif2_pins, ARRAY_SIZE(cs47l85_aif2_pins) }, 39*4882a593Smuzhiyun { "aif3", cs47l85_aif3_pins, ARRAY_SIZE(cs47l85_aif3_pins) }, 40*4882a593Smuzhiyun { "aif4", cs47l85_aif4_pins, ARRAY_SIZE(cs47l85_aif4_pins) }, 41*4882a593Smuzhiyun { "mif1", cs47l85_mif1_pins, ARRAY_SIZE(cs47l85_mif1_pins) }, 42*4882a593Smuzhiyun { "mif2", cs47l85_mif2_pins, ARRAY_SIZE(cs47l85_mif2_pins) }, 43*4882a593Smuzhiyun { "mif3", cs47l85_mif3_pins, ARRAY_SIZE(cs47l85_mif3_pins) }, 44*4882a593Smuzhiyun { "dmic4", cs47l85_dmic4_pins, ARRAY_SIZE(cs47l85_dmic4_pins) }, 45*4882a593Smuzhiyun { "dmic5", cs47l85_dmic5_pins, ARRAY_SIZE(cs47l85_dmic5_pins) }, 46*4882a593Smuzhiyun { "dmic6", cs47l85_dmic6_pins, ARRAY_SIZE(cs47l85_dmic6_pins) }, 47*4882a593Smuzhiyun { "pdmspk1", cs47l85_spk1_pins, ARRAY_SIZE(cs47l85_spk1_pins) }, 48*4882a593Smuzhiyun { "pdmspk2", cs47l85_spk2_pins, ARRAY_SIZE(cs47l85_spk2_pins) }, 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun const struct madera_pin_chip cs47l85_pin_chip = { 52*4882a593Smuzhiyun .n_pins = CS47L85_NUM_GPIOS, 53*4882a593Smuzhiyun .pin_groups = cs47l85_pin_groups, 54*4882a593Smuzhiyun .n_pin_groups = ARRAY_SIZE(cs47l85_pin_groups), 55*4882a593Smuzhiyun }; 56