1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 IBM Corp. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef PINCTRL_ASPEED 7*4882a593Smuzhiyun #define PINCTRL_ASPEED 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <linux/pinctrl/pinctrl.h> 10*4882a593Smuzhiyun #include <linux/pinctrl/pinmux.h> 11*4882a593Smuzhiyun #include <linux/pinctrl/pinconf.h> 12*4882a593Smuzhiyun #include <linux/pinctrl/pinconf-generic.h> 13*4882a593Smuzhiyun #include <linux/regmap.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #include "pinmux-aspeed.h" 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /** 18*4882a593Smuzhiyun * @param The pinconf parameter type 19*4882a593Smuzhiyun * @pins The pin range this config struct covers, [low, high] 20*4882a593Smuzhiyun * @reg The register housing the configuration bits 21*4882a593Smuzhiyun * @mask The mask to select the bits of interest in @reg 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun struct aspeed_pin_config { 24*4882a593Smuzhiyun enum pin_config_param param; 25*4882a593Smuzhiyun unsigned int pins[2]; 26*4882a593Smuzhiyun unsigned int reg; 27*4882a593Smuzhiyun u32 mask; 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define ASPEED_PINCTRL_PIN(name_) \ 31*4882a593Smuzhiyun [name_] = { \ 32*4882a593Smuzhiyun .number = name_, \ 33*4882a593Smuzhiyun .name = #name_, \ 34*4882a593Smuzhiyun .drv_data = (void *) &(PIN_SYM(name_)) \ 35*4882a593Smuzhiyun } 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \ 38*4882a593Smuzhiyun .param = param_, \ 39*4882a593Smuzhiyun .pins = {pin0_, pin1_}, \ 40*4882a593Smuzhiyun .reg = reg_, \ 41*4882a593Smuzhiyun .mask = BIT_MASK(bit_) \ 42*4882a593Smuzhiyun } 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \ 45*4882a593Smuzhiyun ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \ 46*4882a593Smuzhiyun ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \ 49*4882a593Smuzhiyun ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \ 50*4882a593Smuzhiyun ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Aspeed pin configuration description. 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * @param: pinconf configuration parameter 55*4882a593Smuzhiyun * @arg: The supported argument for @param, or -1 if any value is supported 56*4882a593Smuzhiyun * @val: The register value to write to configure @arg for @param 57*4882a593Smuzhiyun * @mask: The bitfield mask for @val 58*4882a593Smuzhiyun * 59*4882a593Smuzhiyun * The map is to be used in conjunction with the configuration array supplied 60*4882a593Smuzhiyun * by the driver implementation. 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun struct aspeed_pin_config_map { 63*4882a593Smuzhiyun enum pin_config_param param; 64*4882a593Smuzhiyun s32 arg; 65*4882a593Smuzhiyun u32 val; 66*4882a593Smuzhiyun u32 mask; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun struct aspeed_pinctrl_data { 70*4882a593Smuzhiyun struct regmap *scu; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun const struct pinctrl_pin_desc *pins; 73*4882a593Smuzhiyun const unsigned int npins; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun const struct aspeed_pin_config *configs; 76*4882a593Smuzhiyun const unsigned int nconfigs; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct aspeed_pinmux_data pinmux; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun const struct aspeed_pin_config_map *confmaps; 81*4882a593Smuzhiyun const unsigned int nconfmaps; 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Aspeed pinctrl helpers */ 85*4882a593Smuzhiyun int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev); 86*4882a593Smuzhiyun const char *aspeed_pinctrl_get_group_name(struct pinctrl_dev *pctldev, 87*4882a593Smuzhiyun unsigned int group); 88*4882a593Smuzhiyun int aspeed_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, 89*4882a593Smuzhiyun unsigned int group, const unsigned int **pins, 90*4882a593Smuzhiyun unsigned int *npins); 91*4882a593Smuzhiyun void aspeed_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, 92*4882a593Smuzhiyun struct seq_file *s, unsigned int offset); 93*4882a593Smuzhiyun int aspeed_pinmux_get_fn_count(struct pinctrl_dev *pctldev); 94*4882a593Smuzhiyun const char *aspeed_pinmux_get_fn_name(struct pinctrl_dev *pctldev, 95*4882a593Smuzhiyun unsigned int function); 96*4882a593Smuzhiyun int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev, 97*4882a593Smuzhiyun unsigned int function, const char * const **groups, 98*4882a593Smuzhiyun unsigned int * const num_groups); 99*4882a593Smuzhiyun int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function, 100*4882a593Smuzhiyun unsigned int group); 101*4882a593Smuzhiyun int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev, 102*4882a593Smuzhiyun struct pinctrl_gpio_range *range, 103*4882a593Smuzhiyun unsigned int offset); 104*4882a593Smuzhiyun int aspeed_pinctrl_probe(struct platform_device *pdev, 105*4882a593Smuzhiyun struct pinctrl_desc *pdesc, 106*4882a593Smuzhiyun struct aspeed_pinctrl_data *pdata); 107*4882a593Smuzhiyun int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, 108*4882a593Smuzhiyun unsigned long *config); 109*4882a593Smuzhiyun int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, 110*4882a593Smuzhiyun unsigned long *configs, unsigned int num_configs); 111*4882a593Smuzhiyun int aspeed_pin_config_group_get(struct pinctrl_dev *pctldev, 112*4882a593Smuzhiyun unsigned int selector, 113*4882a593Smuzhiyun unsigned long *config); 114*4882a593Smuzhiyun int aspeed_pin_config_group_set(struct pinctrl_dev *pctldev, 115*4882a593Smuzhiyun unsigned int selector, 116*4882a593Smuzhiyun unsigned long *configs, 117*4882a593Smuzhiyun unsigned int num_configs); 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun #endif /* PINCTRL_ASPEED */ 120