1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0-only 2*4882a593Smuzhiyunconfig PINCTRL_ASPEED 3*4882a593Smuzhiyun bool 4*4882a593Smuzhiyun depends on (ARCH_ASPEED || COMPILE_TEST) && OF 5*4882a593Smuzhiyun depends on MFD_SYSCON 6*4882a593Smuzhiyun select PINMUX 7*4882a593Smuzhiyun select PINCONF 8*4882a593Smuzhiyun select GENERIC_PINCONF 9*4882a593Smuzhiyun select REGMAP_MMIO 10*4882a593Smuzhiyun 11*4882a593Smuzhiyunconfig PINCTRL_ASPEED_G4 12*4882a593Smuzhiyun bool "Aspeed G4 SoC pin control" 13*4882a593Smuzhiyun depends on (MACH_ASPEED_G4 || COMPILE_TEST) && OF 14*4882a593Smuzhiyun select PINCTRL_ASPEED 15*4882a593Smuzhiyun help 16*4882a593Smuzhiyun Say Y here to enable pin controller support for Aspeed's 4th 17*4882a593Smuzhiyun generation SoCs. GPIO is provided by a separate GPIO driver. 18*4882a593Smuzhiyun 19*4882a593Smuzhiyunconfig PINCTRL_ASPEED_G5 20*4882a593Smuzhiyun bool "Aspeed G5 SoC pin control" 21*4882a593Smuzhiyun depends on (MACH_ASPEED_G5 || COMPILE_TEST) && OF 22*4882a593Smuzhiyun select PINCTRL_ASPEED 23*4882a593Smuzhiyun help 24*4882a593Smuzhiyun Say Y here to enable pin controller support for Aspeed's 5th 25*4882a593Smuzhiyun generation SoCs. GPIO is provided by a separate GPIO driver. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunconfig PINCTRL_ASPEED_G6 28*4882a593Smuzhiyun bool "Aspeed G6 SoC pin control" 29*4882a593Smuzhiyun depends on (MACH_ASPEED_G6 || COMPILE_TEST) && OF 30*4882a593Smuzhiyun select PINCTRL_ASPEED 31*4882a593Smuzhiyun help 32*4882a593Smuzhiyun Say Y here to enable pin controller support for Aspeed's 6th 33*4882a593Smuzhiyun generation SoCs. GPIO is provided by a separate GPIO driver. 34