1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * P2U (PIPE to UPHY) driver for Tegra T194 SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2019 NVIDIA Corporation.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Vidya Sagar <vidyas@nvidia.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of.h>
14*4882a593Smuzhiyun #include <linux/of_platform.h>
15*4882a593Smuzhiyun #include <linux/phy/phy.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
18*4882a593Smuzhiyun #define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
19*4882a593Smuzhiyun #define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
20*4882a593Smuzhiyun #define P2U_PERIODIC_EQ_CTRL_GEN4 0xc4
21*4882a593Smuzhiyun #define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1)
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #define P2U_RX_DEBOUNCE_TIME 0xa4
24*4882a593Smuzhiyun #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0xffff
25*4882a593Smuzhiyun #define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL 160
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun struct tegra_p2u {
28*4882a593Smuzhiyun void __iomem *base;
29*4882a593Smuzhiyun };
30*4882a593Smuzhiyun
p2u_writel(struct tegra_p2u * phy,const u32 value,const u32 reg)31*4882a593Smuzhiyun static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,
32*4882a593Smuzhiyun const u32 reg)
33*4882a593Smuzhiyun {
34*4882a593Smuzhiyun writel_relaxed(value, phy->base + reg);
35*4882a593Smuzhiyun }
36*4882a593Smuzhiyun
p2u_readl(struct tegra_p2u * phy,const u32 reg)37*4882a593Smuzhiyun static inline u32 p2u_readl(struct tegra_p2u *phy, const u32 reg)
38*4882a593Smuzhiyun {
39*4882a593Smuzhiyun return readl_relaxed(phy->base + reg);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
tegra_p2u_power_on(struct phy * x)42*4882a593Smuzhiyun static int tegra_p2u_power_on(struct phy *x)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun struct tegra_p2u *phy = phy_get_drvdata(x);
45*4882a593Smuzhiyun u32 val;
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
48*4882a593Smuzhiyun val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
49*4882a593Smuzhiyun val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
50*4882a593Smuzhiyun p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3);
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4);
53*4882a593Smuzhiyun val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN;
54*4882a593Smuzhiyun p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN4);
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun val = p2u_readl(phy, P2U_RX_DEBOUNCE_TIME);
57*4882a593Smuzhiyun val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK;
58*4882a593Smuzhiyun val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
59*4882a593Smuzhiyun p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun return 0;
62*4882a593Smuzhiyun }
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun static const struct phy_ops ops = {
65*4882a593Smuzhiyun .power_on = tegra_p2u_power_on,
66*4882a593Smuzhiyun .owner = THIS_MODULE,
67*4882a593Smuzhiyun };
68*4882a593Smuzhiyun
tegra_p2u_probe(struct platform_device * pdev)69*4882a593Smuzhiyun static int tegra_p2u_probe(struct platform_device *pdev)
70*4882a593Smuzhiyun {
71*4882a593Smuzhiyun struct phy_provider *phy_provider;
72*4882a593Smuzhiyun struct device *dev = &pdev->dev;
73*4882a593Smuzhiyun struct phy *generic_phy;
74*4882a593Smuzhiyun struct tegra_p2u *phy;
75*4882a593Smuzhiyun struct resource *res;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
78*4882a593Smuzhiyun if (!phy)
79*4882a593Smuzhiyun return -ENOMEM;
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ctl");
82*4882a593Smuzhiyun phy->base = devm_ioremap_resource(dev, res);
83*4882a593Smuzhiyun if (IS_ERR(phy->base))
84*4882a593Smuzhiyun return PTR_ERR(phy->base);
85*4882a593Smuzhiyun
86*4882a593Smuzhiyun platform_set_drvdata(pdev, phy);
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun generic_phy = devm_phy_create(dev, NULL, &ops);
89*4882a593Smuzhiyun if (IS_ERR(generic_phy))
90*4882a593Smuzhiyun return PTR_ERR(generic_phy);
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun phy_set_drvdata(generic_phy, phy);
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
95*4882a593Smuzhiyun if (IS_ERR(phy_provider))
96*4882a593Smuzhiyun return PTR_ERR(phy_provider);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun return 0;
99*4882a593Smuzhiyun }
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const struct of_device_id tegra_p2u_id_table[] = {
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun .compatible = "nvidia,tegra194-p2u",
104*4882a593Smuzhiyun },
105*4882a593Smuzhiyun {}
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, tegra_p2u_id_table);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun static struct platform_driver tegra_p2u_driver = {
110*4882a593Smuzhiyun .probe = tegra_p2u_probe,
111*4882a593Smuzhiyun .driver = {
112*4882a593Smuzhiyun .name = "tegra194-p2u",
113*4882a593Smuzhiyun .of_match_table = tegra_p2u_id_table,
114*4882a593Smuzhiyun },
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun module_platform_driver(tegra_p2u_driver);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun MODULE_AUTHOR("Vidya Sagar <vidyas@nvidia.com>");
119*4882a593Smuzhiyun MODULE_DESCRIPTION("NVIDIA Tegra194 PIPE2UPHY PHY driver");
120*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
121