1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * UFS PHY driver for Samsung EXYNOS SoC
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2020 Samsung Electronics Co., Ltd.
6*4882a593Smuzhiyun * Author: Seungwon Jeon <essuuj@gmail.com>
7*4882a593Smuzhiyun * Author: Alim Akhtar <alim.akhtar@samsung.com>
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun #ifndef _PHY_SAMSUNG_UFS_
11*4882a593Smuzhiyun #define _PHY_SAMSUNG_UFS_
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #define PHY_COMN_BLK 1
14*4882a593Smuzhiyun #define PHY_TRSV_BLK 2
15*4882a593Smuzhiyun #define END_UFS_PHY_CFG { 0 }
16*4882a593Smuzhiyun #define PHY_TRSV_CH_OFFSET 0x30
17*4882a593Smuzhiyun #define PHY_APB_ADDR(off) ((off) << 2)
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #define PHY_COMN_REG_CFG(o, v, d) { \
20*4882a593Smuzhiyun .off_0 = PHY_APB_ADDR((o)), \
21*4882a593Smuzhiyun .off_1 = 0, \
22*4882a593Smuzhiyun .val = (v), \
23*4882a593Smuzhiyun .desc = (d), \
24*4882a593Smuzhiyun .id = PHY_COMN_BLK, \
25*4882a593Smuzhiyun }
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #define PHY_TRSV_REG_CFG(o, v, d) { \
28*4882a593Smuzhiyun .off_0 = PHY_APB_ADDR((o)), \
29*4882a593Smuzhiyun .off_1 = PHY_APB_ADDR((o) + PHY_TRSV_CH_OFFSET), \
30*4882a593Smuzhiyun .val = (v), \
31*4882a593Smuzhiyun .desc = (d), \
32*4882a593Smuzhiyun .id = PHY_TRSV_BLK, \
33*4882a593Smuzhiyun }
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* UFS PHY registers */
36*4882a593Smuzhiyun #define PHY_PLL_LOCK_STATUS 0x1e
37*4882a593Smuzhiyun #define PHY_CDR_LOCK_STATUS 0x5e
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun #define PHY_PLL_LOCK_BIT BIT(5)
40*4882a593Smuzhiyun #define PHY_CDR_LOCK_BIT BIT(4)
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* description for PHY calibration */
43*4882a593Smuzhiyun enum {
44*4882a593Smuzhiyun /* applicable to any */
45*4882a593Smuzhiyun PWR_DESC_ANY = 0,
46*4882a593Smuzhiyun /* mode */
47*4882a593Smuzhiyun PWR_DESC_PWM = 1,
48*4882a593Smuzhiyun PWR_DESC_HS = 2,
49*4882a593Smuzhiyun /* series */
50*4882a593Smuzhiyun PWR_DESC_SER_A = 1,
51*4882a593Smuzhiyun PWR_DESC_SER_B = 2,
52*4882a593Smuzhiyun /* gear */
53*4882a593Smuzhiyun PWR_DESC_G1 = 1,
54*4882a593Smuzhiyun PWR_DESC_G2 = 2,
55*4882a593Smuzhiyun PWR_DESC_G3 = 3,
56*4882a593Smuzhiyun /* field mask */
57*4882a593Smuzhiyun MD_MASK = 0x3,
58*4882a593Smuzhiyun SR_MASK = 0x3,
59*4882a593Smuzhiyun GR_MASK = 0x7,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun #define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
63*4882a593Smuzhiyun #define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
64*4882a593Smuzhiyun #define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
65*4882a593Smuzhiyun #define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
66*4882a593Smuzhiyun #define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
67*4882a593Smuzhiyun #define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
68*4882a593Smuzhiyun #define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
69*4882a593Smuzhiyun #define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
70*4882a593Smuzhiyun #define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
71*4882a593Smuzhiyun #define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
72*4882a593Smuzhiyun (((s) & SR_MASK) << 2) | ((m) & MD_MASK))
73*4882a593Smuzhiyun #define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
74*4882a593Smuzhiyun PWR_DESC_ANY, PWR_DESC_PWM)
75*4882a593Smuzhiyun #define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
76*4882a593Smuzhiyun (((s) & SR_MASK) << 2) | PWR_DESC_HS)
77*4882a593Smuzhiyun #define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
78*4882a593Smuzhiyun PWR_DESC_ANY, PWR_DESC_HS)
79*4882a593Smuzhiyun #define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
80*4882a593Smuzhiyun PWR_DESC_ANY, PWR_DESC_ANY)
81*4882a593Smuzhiyun /* PHY calibration point/state */
82*4882a593Smuzhiyun enum {
83*4882a593Smuzhiyun CFG_PRE_INIT,
84*4882a593Smuzhiyun CFG_POST_INIT,
85*4882a593Smuzhiyun CFG_PRE_PWR_HS,
86*4882a593Smuzhiyun CFG_POST_PWR_HS,
87*4882a593Smuzhiyun CFG_TAG_MAX,
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct samsung_ufs_phy_cfg {
91*4882a593Smuzhiyun u32 off_0;
92*4882a593Smuzhiyun u32 off_1;
93*4882a593Smuzhiyun u32 val;
94*4882a593Smuzhiyun u8 desc;
95*4882a593Smuzhiyun u8 id;
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun struct samsung_ufs_phy_drvdata {
99*4882a593Smuzhiyun const struct samsung_ufs_phy_cfg **cfg;
100*4882a593Smuzhiyun struct pmu_isol {
101*4882a593Smuzhiyun u32 offset;
102*4882a593Smuzhiyun u32 mask;
103*4882a593Smuzhiyun u32 en;
104*4882a593Smuzhiyun } isol;
105*4882a593Smuzhiyun bool has_symbol_clk;
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun struct samsung_ufs_phy {
109*4882a593Smuzhiyun struct device *dev;
110*4882a593Smuzhiyun void __iomem *reg_pma;
111*4882a593Smuzhiyun struct regmap *reg_pmu;
112*4882a593Smuzhiyun struct clk *ref_clk;
113*4882a593Smuzhiyun struct clk *ref_clk_parent;
114*4882a593Smuzhiyun struct clk *tx0_symbol_clk;
115*4882a593Smuzhiyun struct clk *rx0_symbol_clk;
116*4882a593Smuzhiyun struct clk *rx1_symbol_clk;
117*4882a593Smuzhiyun const struct samsung_ufs_phy_drvdata *drvdata;
118*4882a593Smuzhiyun struct samsung_ufs_phy_cfg **cfg;
119*4882a593Smuzhiyun const struct pmu_isol *isol;
120*4882a593Smuzhiyun u8 lane_cnt;
121*4882a593Smuzhiyun int ufs_phy_state;
122*4882a593Smuzhiyun enum phy_mode mode;
123*4882a593Smuzhiyun };
124*4882a593Smuzhiyun
get_samsung_ufs_phy(struct phy * phy)125*4882a593Smuzhiyun static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
126*4882a593Smuzhiyun {
127*4882a593Smuzhiyun return (struct samsung_ufs_phy *)phy_get_drvdata(phy);
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
samsung_ufs_phy_ctrl_isol(struct samsung_ufs_phy * phy,u32 isol)130*4882a593Smuzhiyun static inline void samsung_ufs_phy_ctrl_isol(
131*4882a593Smuzhiyun struct samsung_ufs_phy *phy, u32 isol)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun regmap_update_bits(phy->reg_pmu, phy->isol->offset,
134*4882a593Smuzhiyun phy->isol->mask, isol ? 0 : phy->isol->en);
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun #include "phy-exynos7-ufs.h"
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun #endif /* _PHY_SAMSUNG_UFS_ */
140