1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * UFS PHY driver data for Samsung EXYNOS7 SoC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Samsung Electronics Co., Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef _PHY_EXYNOS7_UFS_H_ 8*4882a593Smuzhiyun #define _PHY_EXYNOS7_UFS_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include "phy-samsung-ufs.h" 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL 0x720 13*4882a593Smuzhiyun #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK 0x1 14*4882a593Smuzhiyun #define EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN BIT(0) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Calibration for phy initialization */ 17*4882a593Smuzhiyun static const struct samsung_ufs_phy_cfg exynos7_pre_init_cfg[] = { 18*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_ANY), 19*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_ANY), 20*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_ANY), 21*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x017, 0x84, PWR_MODE_ANY), 22*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x035, 0x58, PWR_MODE_ANY), 23*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_ANY), 24*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x037, 0x40, PWR_MODE_ANY), 25*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x03b, 0x83, PWR_MODE_ANY), 26*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_ANY), 27*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_ANY), 28*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_ANY), 29*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x04c, 0x5b, PWR_MODE_ANY), 30*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_ANY), 31*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x05c, 0x14, PWR_MODE_ANY), 32*4882a593Smuzhiyun END_UFS_PHY_CFG 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Calibration for HS mode series A/B */ 36*4882a593Smuzhiyun static const struct samsung_ufs_phy_cfg exynos7_pre_pwr_hs_cfg[] = { 37*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x00f, 0xfa, PWR_MODE_HS_ANY), 38*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x010, 0x82, PWR_MODE_HS_ANY), 39*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x011, 0x1e, PWR_MODE_HS_ANY), 40*4882a593Smuzhiyun /* Setting order: 1st(0x16, 2nd(0x15) */ 41*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x016, 0xff, PWR_MODE_HS_ANY), 42*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x015, 0x80, PWR_MODE_HS_ANY), 43*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x017, 0x94, PWR_MODE_HS_ANY), 44*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x036, 0x32, PWR_MODE_HS_ANY), 45*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x037, 0x43, PWR_MODE_HS_ANY), 46*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x038, 0x3f, PWR_MODE_HS_ANY), 47*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x042, 0x88, PWR_MODE_HS_G2_SER_A), 48*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x042, 0xbb, PWR_MODE_HS_G2_SER_B), 49*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x043, 0xa6, PWR_MODE_HS_ANY), 50*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x048, 0x74, PWR_MODE_HS_ANY), 51*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x034, 0x35, PWR_MODE_HS_G2_SER_A), 52*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x034, 0x36, PWR_MODE_HS_G2_SER_B), 53*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x035, 0x5b, PWR_MODE_HS_G2_SER_A), 54*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x035, 0x5c, PWR_MODE_HS_G2_SER_B), 55*4882a593Smuzhiyun END_UFS_PHY_CFG 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Calibration for HS mode series A/B atfer PMC */ 59*4882a593Smuzhiyun static const struct samsung_ufs_phy_cfg exynos7_post_pwr_hs_cfg[] = { 60*4882a593Smuzhiyun PHY_COMN_REG_CFG(0x015, 0x00, PWR_MODE_HS_ANY), 61*4882a593Smuzhiyun PHY_TRSV_REG_CFG(0x04d, 0x83, PWR_MODE_HS_ANY), 62*4882a593Smuzhiyun END_UFS_PHY_CFG 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun static const struct samsung_ufs_phy_cfg *exynos7_ufs_phy_cfgs[CFG_TAG_MAX] = { 66*4882a593Smuzhiyun [CFG_PRE_INIT] = exynos7_pre_init_cfg, 67*4882a593Smuzhiyun [CFG_PRE_PWR_HS] = exynos7_pre_pwr_hs_cfg, 68*4882a593Smuzhiyun [CFG_POST_PWR_HS] = exynos7_post_pwr_hs_cfg, 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun static struct samsung_ufs_phy_drvdata exynos7_ufs_phy = { 72*4882a593Smuzhiyun .cfg = exynos7_ufs_phy_cfgs, 73*4882a593Smuzhiyun .isol = { 74*4882a593Smuzhiyun .offset = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL, 75*4882a593Smuzhiyun .mask = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_MASK, 76*4882a593Smuzhiyun .en = EXYNOS7_EMBEDDED_COMBO_PHY_CTRL_EN, 77*4882a593Smuzhiyun }, 78*4882a593Smuzhiyun .has_symbol_clk = 1, 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* _PHY_EXYNOS7_UFS_H_ */ 82