1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip Samsung mipi dcphy driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Rockchip Electronics Co., Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _PHY_ROCKCHIP_SAMSUNG_DCPHY_H_ 9*4882a593Smuzhiyun #define _PHY_ROCKCHIP_SAMSUNG_DCPHY_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define MAX_NUM_CSI2_DPHY (0x2) 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun struct samsung_mipi_dcphy { 14*4882a593Smuzhiyun struct device *dev; 15*4882a593Smuzhiyun struct clk *ref_clk; 16*4882a593Smuzhiyun struct clk *pclk; 17*4882a593Smuzhiyun struct regmap *regmap; 18*4882a593Smuzhiyun struct regmap *grf_regmap; 19*4882a593Smuzhiyun struct reset_control *m_phy_rst; 20*4882a593Smuzhiyun struct reset_control *s_phy_rst; 21*4882a593Smuzhiyun struct reset_control *apb_rst; 22*4882a593Smuzhiyun struct reset_control *grf_apb_rst; 23*4882a593Smuzhiyun struct mutex mutex; 24*4882a593Smuzhiyun struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY]; 25*4882a593Smuzhiyun atomic_t stream_cnt; 26*4882a593Smuzhiyun int dphy_dev_num; 27*4882a593Smuzhiyun bool c_option; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun unsigned int lanes; 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun struct { 32*4882a593Smuzhiyun unsigned long long rate; 33*4882a593Smuzhiyun u8 prediv; 34*4882a593Smuzhiyun u16 fbdiv; 35*4882a593Smuzhiyun long dsm; 36*4882a593Smuzhiyun u8 scaler; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun bool ssc_en; 39*4882a593Smuzhiyun u8 mfr; 40*4882a593Smuzhiyun u8 mrr; 41*4882a593Smuzhiyun } pll; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 44*4882a593Smuzhiyun int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 45*4882a593Smuzhiyun }; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #endif 48