1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Rockchip Samsung mipi dcphy driver 4 * 5 * Copyright (C) 2020 Rockchip Electronics Co., Ltd. 6 */ 7 8 #ifndef _PHY_ROCKCHIP_SAMSUNG_DCPHY_H_ 9 #define _PHY_ROCKCHIP_SAMSUNG_DCPHY_H_ 10 11 #define MAX_NUM_CSI2_DPHY (0x2) 12 13 struct samsung_mipi_dcphy { 14 struct device *dev; 15 struct clk *ref_clk; 16 struct clk *pclk; 17 struct regmap *regmap; 18 struct regmap *grf_regmap; 19 struct reset_control *m_phy_rst; 20 struct reset_control *s_phy_rst; 21 struct reset_control *apb_rst; 22 struct reset_control *grf_apb_rst; 23 struct mutex mutex; 24 struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY]; 25 atomic_t stream_cnt; 26 int dphy_dev_num; 27 bool c_option; 28 29 unsigned int lanes; 30 31 struct { 32 unsigned long long rate; 33 u8 prediv; 34 u16 fbdiv; 35 long dsm; 36 u8 scaler; 37 38 bool ssc_en; 39 u8 mfr; 40 u8 mrr; 41 } pll; 42 43 int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 44 int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 45 }; 46 47 #endif 48