1 /*
2 * Rockchip MIPI RX Synopsys/Innosilicon DPHY driver
3 *
4 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <linux/clk.h>
36 #include <linux/delay.h>
37 #include <linux/io.h>
38 #include <linux/module.h>
39 #include <linux/of.h>
40 #include <linux/of_graph.h>
41 #include <linux/of_platform.h>
42 #include <linux/platform_device.h>
43 #include <linux/pm_runtime.h>
44 #include <linux/regmap.h>
45 #include <linux/mfd/syscon.h>
46 #include <media/media-entity.h>
47 #include <media/v4l2-ctrls.h>
48 #include <media/v4l2-fwnode.h>
49 #include <media/v4l2-subdev.h>
50 #include <media/v4l2-device.h>
51 #include <linux/rockchip/cpu.h>
52
53 /* GRF */
54 #define RK1808_GRF_PD_VI_CON_OFFSET 0x0430
55
56 #define RK3288_GRF_SOC_CON6 0x025c
57 #define RK3288_GRF_SOC_CON8 0x0264
58 #define RK3288_GRF_SOC_CON9 0x0268
59 #define RK3288_GRF_SOC_CON10 0x026c
60 #define RK3288_GRF_SOC_CON14 0x027c
61 #define RK3288_GRF_SOC_STATUS21 0x02d4
62 #define RK3288_GRF_IO_VSEL 0x0380
63 #define RK3288_GRF_SOC_CON15 0x03a4
64
65 #define RK3326_GRF_IO_VSEL_OFFSET 0x0180
66 #define RK3326_GRF_PD_VI_CON_OFFSET 0x0430
67
68 #define RK3368_GRF_SOC_CON6_OFFSET 0x0418
69 #define RK3368_GRF_IO_VSEL_OFFSET 0x0900
70
71 #define RK3399_GRF_SOC_CON9 0x6224
72 #define RK3399_GRF_SOC_CON21 0x6254
73 #define RK3399_GRF_SOC_CON22 0x6258
74 #define RK3399_GRF_SOC_CON23 0x625c
75 #define RK3399_GRF_SOC_CON24 0x6260
76 #define RK3399_GRF_SOC_CON25 0x6264
77 #define RK3399_GRF_SOC_STATUS1 0xe2a4
78 #define RK3399_GRF_IO_VSEL 0x0900
79
80 #define RV1126_GRF_CSIPHY0_CON 0x10200
81 #define RV1126_GRF_CSIPHY1_CON 0x10210
82 #define RV1126_GRF_IOFUNC_CON3 0x1026c
83 #define RV1126_GRF_PHY1_SEL_CIFLITE BIT(2)
84 #define RV1126_GRF_PHY1_SEL_ISP BIT(1)
85 #define RV1126_GRF_PHY1_SEL_CIF BIT(0)
86
87 /* PHY */
88 #define RK3288_PHY_TEST_CTRL0 0x30
89 #define RK3288_PHY_TEST_CTRL1 0x34
90 #define RK3288_PHY_SHUTDOWNZ 0x08
91 #define RK3288_PHY_RSTZ 0x0c
92
93 #define RK3399_PHY_TEST_CTRL0 0xb4
94 #define RK3399_PHY_TEST_CTRL1 0xb8
95 #define RK3399_PHY_SHUTDOWNZ 0xa0
96 #define RK3399_PHY_RSTZ 0xa0
97
98 #define CLOCK_LANE_HS_RX_CONTROL 0x34
99 #define LANE0_HS_RX_CONTROL 0x44
100 #define LANE1_HS_RX_CONTROL 0x54
101 #define LANE2_HS_RX_CONTROL 0x84
102 #define LANE3_HS_RX_CONTROL 0x94
103 #define HS_RX_DATA_LANES_THS_SETTLE_CONTROL 0x75
104
105 /* LOW POWER MODE SET */
106 #define MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 0xFFFF
107
108 #define RK1808_CSI_DPHY_CTRL_LANE_ENABLE 0x00
109 #define RK1808_CSI_DPHY_CTRL_PWRCTL \
110 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
111 #define RK1808_CSI_DPHY_CTRL_DIG_RST 0x80
112
113 #define RK3326_CSI_DPHY_CTRL_LANE_ENABLE 0x00
114 #define RK3326_CSI_DPHY_CTRL_PWRCTL 0x04
115 #define RK3326_CSI_DPHY_CTRL_DIG_RST 0x80
116
117 #define RK3368_CSI_DPHY_CTRL_LANE_ENABLE 0x00
118 #define RK3368_CSI_DPHY_CTRL_PWRCTL 0x04
119 #define RK3368_CSI_DPHY_CTRL_DIG_RST 0x80
120
121 #define RV1126_CSI_DPHY_CTRL_LANE_ENABLE 0x00
122 #define RV1126_CSI_DPHY_CTRL_PWRCTL \
123 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
124 #define RV1126_CSI_DPHY_CTRL_DIG_RST 0x80
125
126 #define MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2
127 #define MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6
128
129 /* Configure the count time of the THS-SETTLE by protocol. */
130 #define RK1808_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
131 #define RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE \
132 (RK1808_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
133 #define RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE \
134 (RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
135 #define RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE \
136 (RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
137 #define RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE \
138 (RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
139
140 #define RK3326_CSI_DPHY_CLK_WR_THS_SETTLE 0x100
141 #define RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE \
142 (RK3326_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
143 #define RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE \
144 (RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
145 #define RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE \
146 (RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
147 #define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE \
148 (RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
149
150 #define RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
151 #define RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE \
152 (RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
153 #define RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE \
154 (RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
155 #define RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE \
156 (RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
157 #define RK3326S_CSI_DPHY_LANE3_WR_THS_SETTLE \
158 (RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
159 #define RK3326S_CSI_DPHY_CLK_MODE 0x128
160
161 #define RK3368_CSI_DPHY_CLK_WR_THS_SETTLE 0x100
162 #define RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE \
163 (RK3368_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80)
164 #define RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE \
165 (RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80)
166 #define RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE \
167 (RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80)
168 #define RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE \
169 (RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80)
170
171 #define RV1126_CSI_DPHY_CLK_WR_THS_SETTLE 0x160
172 #define RV1126_CSI_DPHY_LANE0_WR_THS_SETTLE 0x1e0
173 #define RV1126_CSI_DPHY_LANE1_WR_THS_SETTLE 0x260
174 #define RV1126_CSI_DPHY_LANE2_WR_THS_SETTLE 0x2e0
175 #define RV1126_CSI_DPHY_LANE3_WR_THS_SETTLE 0x360
176
177 /* Calibration reception enable */
178 #define RK1808_CSI_DPHY_CLK_CALIB_EN 0x168
179 #define RK1808_CSI_DPHY_LANE0_CALIB_EN 0x1e8
180 #define RK1808_CSI_DPHY_LANE1_CALIB_EN 0x268
181 #define RK1808_CSI_DPHY_LANE2_CALIB_EN 0x2e8
182 #define RK1808_CSI_DPHY_LANE3_CALIB_EN 0x368
183
184 #define RK3326_CSI_DPHY_CLK_CALIB_EN \
185 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
186 #define RK3326_CSI_DPHY_LANE0_CALIB_EN \
187 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
188 #define RK3326_CSI_DPHY_LANE1_CALIB_EN \
189 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
190 #define RK3326_CSI_DPHY_LANE2_CALIB_EN \
191 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
192 #define RK3326_CSI_DPHY_LANE3_CALIB_EN \
193 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
194
195 #define RK3368_CSI_DPHY_CLK_CALIB_EN \
196 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
197 #define RK3368_CSI_DPHY_LANE0_CALIB_EN \
198 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
199 #define RK3368_CSI_DPHY_LANE1_CALIB_EN \
200 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
201 #define RK3368_CSI_DPHY_LANE2_CALIB_EN \
202 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
203 #define RK3368_CSI_DPHY_LANE3_CALIB_EN \
204 MIPI_CSI_DPHY_CTRL_INVALID_OFFSET
205
206 #define RV1126_CSI_DPHY_CLK_CALIB_EN 0x168
207 #define RV1126_CSI_DPHY_LANE0_CALIB_EN 0x1e8
208 #define RV1126_CSI_DPHY_LANE1_CALIB_EN 0x268
209 #define RV1126_CSI_DPHY_LANE2_CALIB_EN 0x2e8
210 #define RV1126_CSI_DPHY_LANE3_CALIB_EN 0x368
211
212 #define RV1126_CSI_DPHY_MIPI_LVDS_MODEL 0x2cc
213 #define RV1126_CSI_DPHY_LVDS_MODE 0x300
214 /*
215 * CSI HOST
216 */
217 #define PHY_TESTEN_ADDR (0x1 << 16)
218 #define PHY_TESTEN_DATA (0x0 << 16)
219 #define PHY_TESTCLK (0x1 << 1)
220 #define PHY_TESTCLR (0x1 << 0)
221 #define THS_SETTLE_COUNTER_THRESHOLD 0x04
222
223 #define HIWORD_UPDATE(val, mask, shift) \
224 ((val) << (shift) | (mask) << ((shift) + 16))
225
226 enum mipi_dphy_chip_id {
227 CHIP_ID_RK1808 = 0,
228 CHIP_ID_RK3288,
229 CHIP_ID_RK3326,
230 CHIP_ID_RK3368,
231 CHIP_ID_RK3399,
232 CHIP_ID_RK1126,
233 CHIP_ID_RK3326S,
234 };
235
236 enum mipi_dphy_rx_pads {
237 MIPI_DPHY_RX_PAD_SINK = 0,
238 MIPI_DPHY_RX_PAD_SOURCE,
239 MIPI_DPHY_RX_PADS_NUM,
240 };
241
242 enum dphy_reg_id {
243 GRF_DPHY_RX0_TURNDISABLE = 0,
244 GRF_DPHY_RX0_FORCERXMODE,
245 GRF_DPHY_RX0_FORCETXSTOPMODE,
246 GRF_DPHY_RX0_ENABLE,
247 GRF_DPHY_RX0_TESTCLR,
248 GRF_DPHY_RX0_TESTCLK,
249 GRF_DPHY_RX0_TESTEN,
250 GRF_DPHY_RX0_TESTDIN,
251 GRF_DPHY_RX0_TURNREQUEST,
252 GRF_DPHY_RX0_TESTDOUT,
253 GRF_DPHY_TX0_TURNDISABLE,
254 GRF_DPHY_TX0_FORCERXMODE,
255 GRF_DPHY_TX0_FORCETXSTOPMODE,
256 GRF_DPHY_TX0_TURNREQUEST,
257 GRF_DPHY_TX1RX1_TURNDISABLE,
258 GRF_DPHY_TX1RX1_FORCERXMODE,
259 GRF_DPHY_TX1RX1_FORCETXSTOPMODE,
260 GRF_DPHY_TX1RX1_ENABLE,
261 GRF_DPHY_TX1RX1_MASTERSLAVEZ,
262 GRF_DPHY_TX1RX1_BASEDIR,
263 GRF_DPHY_TX1RX1_ENABLECLK,
264 GRF_DPHY_TX1RX1_TURNREQUEST,
265 GRF_DPHY_RX1_SRC_SEL,
266 /* rk3288 only */
267 GRF_CON_DISABLE_ISP,
268 GRF_CON_ISP_DPHY_SEL,
269 GRF_DSI_CSI_TESTBUS_SEL,
270 GRF_DVP_V18SEL,
271 /* rk1808 & rk3326 & rv1126 */
272 GRF_DPHY_CSIPHY_FORCERXMODE,
273 GRF_DPHY_CSIPHY_CLKLANE_EN,
274 GRF_DPHY_CSIPHY_DATALANE_EN,
275 /* rv1126 only */
276 GRF_DPHY_CLK_INV_SEL,
277 GRF_DPHY_SEL,
278 /* rk3368 only */
279 GRF_ISP_MIPI_CSI_HOST_SEL,
280 /* below is for rk3399 only */
281 GRF_DPHY_RX0_CLK_INV_SEL,
282 GRF_DPHY_RX1_CLK_INV_SEL,
283 GRF_DPHY_TX1RX1_SRC_SEL,
284 };
285
286 enum csiphy_reg_id {
287 CSIPHY_CTRL_LANE_ENABLE = 0,
288 CSIPHY_CTRL_PWRCTL,
289 CSIPHY_CTRL_DIG_RST,
290 CSIPHY_CLK_THS_SETTLE,
291 CSIPHY_LANE0_THS_SETTLE,
292 CSIPHY_LANE1_THS_SETTLE,
293 CSIPHY_LANE2_THS_SETTLE,
294 CSIPHY_LANE3_THS_SETTLE,
295 CSIPHY_CLK_CALIB_ENABLE,
296 CSIPHY_LANE0_CALIB_ENABLE,
297 CSIPHY_LANE1_CALIB_ENABLE,
298 CSIPHY_LANE2_CALIB_ENABLE,
299 CSIPHY_LANE3_CALIB_ENABLE,
300 //rv1126 only
301 CSIPHY_MIPI_LVDS_MODEL,
302 CSIPHY_LVDS_MODE,
303 CSIPHY_CLK_MODE,
304 };
305
306 enum mipi_dphy_ctl_type {
307 MIPI_DPHY_CTL_GRF_ONLY = 0,
308 MIPI_DPHY_CTL_CSI_HOST
309 };
310
311 enum mipi_dphy_lane {
312 MIPI_DPHY_LANE_CLOCK = 0,
313 MIPI_DPHY_LANE_DATA0,
314 MIPI_DPHY_LANE_DATA1,
315 MIPI_DPHY_LANE_DATA2,
316 MIPI_DPHY_LANE_DATA3
317 };
318
319 enum txrx_reg_id {
320 TXRX_PHY_TEST_CTRL0 = 0,
321 TXRX_PHY_TEST_CTRL1,
322 TXRX_PHY_SHUTDOWNZ,
323 TXRX_PHY_RSTZ,
324 };
325
326 struct dphy_reg {
327 u32 offset;
328 u32 mask;
329 u32 shift;
330 };
331
332 struct txrx_reg {
333 u32 offset;
334 };
335
336 struct csiphy_reg {
337 u32 offset;
338 };
339
340 #define PHY_REG(_offset, _width, _shift) \
341 { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, }
342
343 #define TXRX_REG(_offset) \
344 { .offset = _offset, }
345
346 #define CSIPHY_REG(_offset) \
347 { .offset = _offset, }
348
349 static const struct dphy_reg rk1808_grf_dphy_regs[] = {
350 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0),
351 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8),
352 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4),
353 };
354
355 static const struct dphy_reg rk3288_grf_dphy_regs[] = {
356 [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0),
357 [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1),
358 [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14),
359 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0),
360 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4),
361 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8),
362 [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 0),
363 [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 4),
364 [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 8),
365 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 12),
366 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 0),
367 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 4),
368 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 8),
369 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 12),
370 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 0),
371 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 1),
372 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 2),
373 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3288_GRF_SOC_CON14, 8, 3),
374 [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 12),
375 [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 13),
376 [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 14),
377 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 15),
378 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 0),
379 [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 4),
380 [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 3, 8),
381 [GRF_DVP_V18SEL] = PHY_REG(RK3288_GRF_IO_VSEL, 1, 1),
382 [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3288_GRF_SOC_STATUS21, 8, 0),
383 };
384
385 static const struct dphy_reg rk3326_grf_dphy_regs[] = {
386 [GRF_DVP_V18SEL] = PHY_REG(RK3326_GRF_IO_VSEL_OFFSET, 1, 4),
387 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0),
388 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8),
389 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4),
390 };
391
392 static const struct dphy_reg rk3368_grf_dphy_regs[] = {
393 [GRF_DVP_V18SEL] = PHY_REG(RK3368_GRF_IO_VSEL_OFFSET, 1, 1),
394 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8),
395 [GRF_ISP_MIPI_CSI_HOST_SEL] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 1),
396 [GRF_CON_DISABLE_ISP] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 0),
397 };
398
399 static const struct dphy_reg rk3399_grf_dphy_regs[] = {
400 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
401 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
402 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
403 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
404 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
405 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
406 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
407 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
408 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
409 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8),
410 [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12),
411 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0),
412 [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4),
413 [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8),
414 [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12),
415 [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0),
416 [GRF_DPHY_TX1RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4),
417 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5),
418 [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6),
419 [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7),
420 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0),
421 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8),
422 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9),
423 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10),
424 [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0),
425 [GRF_DVP_V18SEL] = PHY_REG(RK3399_GRF_IO_VSEL, 1, 1),
426 };
427
428 static const struct dphy_reg rv1126_grf_dphy0_regs[] = {
429 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 4, 0),
430 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 4, 4),
431 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 1, 8),
432 [GRF_DPHY_CLK_INV_SEL] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 1, 9),
433 [GRF_DPHY_SEL] = PHY_REG(RV1126_GRF_IOFUNC_CON3, 3, 9),
434 };
435
436 static const struct dphy_reg rv1126_grf_dphy1_regs[] = {
437 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 4, 0),
438 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 4, 4),
439 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 1, 8),
440 [GRF_DPHY_CLK_INV_SEL] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 1, 9),
441 [GRF_DPHY_SEL] = PHY_REG(RV1126_GRF_IOFUNC_CON3, 3, 9),
442 };
443
444 static const struct txrx_reg rk3288_txrx_regs[] = {
445 [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3288_PHY_TEST_CTRL0),
446 [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3288_PHY_TEST_CTRL1),
447 [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3288_PHY_SHUTDOWNZ),
448 [TXRX_PHY_RSTZ] = TXRX_REG(RK3288_PHY_RSTZ),
449 };
450
451 static const struct txrx_reg rk3399_txrx_regs[] = {
452 [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3399_PHY_TEST_CTRL0),
453 [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3399_PHY_TEST_CTRL1),
454 [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3399_PHY_SHUTDOWNZ),
455 [TXRX_PHY_RSTZ] = TXRX_REG(RK3399_PHY_RSTZ),
456 };
457
458 static const struct csiphy_reg rk1808_csiphy_regs[] = {
459 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_LANE_ENABLE),
460 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_PWRCTL),
461 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_DIG_RST),
462 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_WR_THS_SETTLE),
463 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE),
464 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE),
465 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE),
466 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE),
467 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_CALIB_EN),
468 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_CALIB_EN),
469 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_CALIB_EN),
470 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_CALIB_EN),
471 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_CALIB_EN),
472 };
473
474 static const struct csiphy_reg rk3326_csiphy_regs[] = {
475 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_LANE_ENABLE),
476 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_PWRCTL),
477 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_DIG_RST),
478 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_WR_THS_SETTLE),
479 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE),
480 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE),
481 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE),
482 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE),
483 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_CALIB_EN),
484 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_CALIB_EN),
485 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_CALIB_EN),
486 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_CALIB_EN),
487 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN),
488 };
489
490 static const struct csiphy_reg rk3326s_csiphy_regs[] = {
491 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_LANE_ENABLE),
492 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_PWRCTL),
493 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_DIG_RST),
494 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_CLK_WR_THS_SETTLE),
495 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE0_WR_THS_SETTLE),
496 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE1_WR_THS_SETTLE),
497 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE2_WR_THS_SETTLE),
498 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3326S_CSI_DPHY_LANE3_WR_THS_SETTLE),
499 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_CALIB_EN),
500 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_CALIB_EN),
501 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_CALIB_EN),
502 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_CALIB_EN),
503 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN),
504 [CSIPHY_CLK_MODE] = CSIPHY_REG(RK3326S_CSI_DPHY_CLK_MODE),
505 };
506
507 static const struct csiphy_reg rk3368_csiphy_regs[] = {
508 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_LANE_ENABLE),
509 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_PWRCTL),
510 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_DIG_RST),
511 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE),
512 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE),
513 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE),
514 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE),
515 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE),
516 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_CALIB_EN),
517 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_CALIB_EN),
518 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_CALIB_EN),
519 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_CALIB_EN),
520 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_CALIB_EN),
521 };
522
523 static const struct csiphy_reg rv1126_csiphy_regs[] = {
524 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_LANE_ENABLE),
525 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_PWRCTL),
526 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_DIG_RST),
527 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_CLK_WR_THS_SETTLE),
528 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE0_WR_THS_SETTLE),
529 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE1_WR_THS_SETTLE),
530 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE2_WR_THS_SETTLE),
531 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE3_WR_THS_SETTLE),
532 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_CLK_CALIB_EN),
533 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE0_CALIB_EN),
534 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE1_CALIB_EN),
535 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE2_CALIB_EN),
536 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE3_CALIB_EN),
537 [CSIPHY_MIPI_LVDS_MODEL] = CSIPHY_REG(RV1126_CSI_DPHY_MIPI_LVDS_MODEL),
538 [CSIPHY_LVDS_MODE] = CSIPHY_REG(RV1126_CSI_DPHY_LVDS_MODE),
539 };
540
541 struct hsfreq_range {
542 u32 range_h;
543 u8 cfg_bit;
544 };
545
546 struct mipidphy_priv;
547
548 struct dphy_drv_data {
549 const char * const *clks;
550 int num_clks;
551 const struct hsfreq_range *hsfreq_ranges;
552 int num_hsfreq_ranges;
553 const struct dphy_reg *grf_regs;
554 const struct txrx_reg *txrx_regs;
555 const struct csiphy_reg *csiphy_regs;
556 enum mipi_dphy_ctl_type ctl_type;
557 void (*individual_init)(struct mipidphy_priv *priv);
558 enum mipi_dphy_chip_id chip_id;
559 };
560
561 struct sensor_async_subdev {
562 struct v4l2_async_subdev asd;
563 struct v4l2_mbus_config mbus;
564 int lanes;
565 };
566
567 #define MAX_DPHY_CLK 8
568 #define MAX_DPHY_SENSORS 2
569
570 struct mipidphy_sensor {
571 struct v4l2_subdev *sd;
572 struct v4l2_mbus_config mbus;
573 struct v4l2_mbus_framefmt format;
574 int lanes;
575 };
576
577 struct mipidphy_priv {
578 struct device *dev;
579 struct regmap *regmap_grf;
580 const struct dphy_reg *grf_regs;
581 const struct txrx_reg *txrx_regs;
582 const struct csiphy_reg *csiphy_regs;
583 void __iomem *csihost_base_addr;
584 struct clk *clks[MAX_DPHY_CLK];
585 const struct dphy_drv_data *drv_data;
586 u64 data_rate_mbps;
587 struct v4l2_async_notifier notifier;
588 struct v4l2_subdev sd;
589 struct mutex mutex; /* lock for updating protection */
590 struct media_pad pads[MIPI_DPHY_RX_PADS_NUM];
591 struct mipidphy_sensor sensors[MAX_DPHY_SENSORS];
592 int num_sensors;
593 int phy_index;
594 bool is_streaming;
595 void __iomem *txrx_base_addr;
596 int (*stream_on)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
597 int (*stream_off)(struct mipidphy_priv *priv, struct v4l2_subdev *sd);
598 };
599
to_dphy_priv(struct v4l2_subdev * subdev)600 static inline struct mipidphy_priv *to_dphy_priv(struct v4l2_subdev *subdev)
601 {
602 return container_of(subdev, struct mipidphy_priv, sd);
603 }
604
write_grf_reg(struct mipidphy_priv * priv,int index,u8 value)605 static inline void write_grf_reg(struct mipidphy_priv *priv,
606 int index, u8 value)
607 {
608 const struct dphy_reg *reg = &priv->grf_regs[index];
609 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift);
610
611 if (reg->offset)
612 regmap_write(priv->regmap_grf, reg->offset, val);
613 }
614
read_grf_reg(struct mipidphy_priv * priv,int index)615 static inline u32 read_grf_reg(struct mipidphy_priv *priv, int index)
616 {
617 const struct dphy_reg *reg = &priv->grf_regs[index];
618 unsigned int val = 0;
619
620 if (reg->offset) {
621 regmap_read(priv->regmap_grf, reg->offset, &val);
622 val = (val >> reg->shift) & reg->mask;
623 }
624 return val;
625 }
626
write_txrx_reg(struct mipidphy_priv * priv,int index,u32 value)627 static inline void write_txrx_reg(struct mipidphy_priv *priv,
628 int index, u32 value)
629 {
630 const struct txrx_reg *reg = &priv->txrx_regs[index];
631
632 if (reg->offset)
633 writel(value, priv->txrx_base_addr + reg->offset);
634 }
635
mipidphy0_wr_reg(struct mipidphy_priv * priv,u8 test_code,u8 test_data)636 static void mipidphy0_wr_reg(struct mipidphy_priv *priv,
637 u8 test_code, u8 test_data)
638 {
639 /*
640 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content
641 * is latched internally as the current test code. Test data is
642 * programmed internally by rising edge on TESTCLK.
643 */
644 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
645 write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code);
646 write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 1);
647 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 0);
648 write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 0);
649 write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data);
650 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
651 }
652
mipidphy1_wr_reg(struct mipidphy_priv * priv,unsigned char addr,unsigned char data)653 static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr,
654 unsigned char data)
655 {
656 /*
657 * TESTEN =1,TESTDIN=addr
658 * TESTCLK=0
659 * TESTEN =0,TESTDIN=data
660 * TESTCLK=1
661 */
662 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_ADDR | addr);
663 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x00);
664 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_DATA | data);
665 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x02);
666 }
667
write_csiphy_reg(struct mipidphy_priv * priv,int index,u32 value)668 static inline void write_csiphy_reg(struct mipidphy_priv *priv,
669 int index, u32 value)
670 {
671 const struct csiphy_reg *reg = &priv->csiphy_regs[index];
672
673 if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET)
674 writel(value, priv->csihost_base_addr + reg->offset);
675 }
676
read_csiphy_reg(struct mipidphy_priv * priv,int index,u32 * value)677 static inline void read_csiphy_reg(struct mipidphy_priv *priv,
678 int index, u32 *value)
679 {
680 const struct csiphy_reg *reg = &priv->csiphy_regs[index];
681
682 if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET)
683 *value = readl(priv->csihost_base_addr + reg->offset);
684 }
685
csi_mipidphy_wr_ths_settle(struct mipidphy_priv * priv,int hsfreq,enum mipi_dphy_lane lane)686 static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq,
687 enum mipi_dphy_lane lane)
688 {
689 unsigned int val = 0;
690 unsigned int offset;
691
692 switch (lane) {
693 case MIPI_DPHY_LANE_CLOCK:
694 offset = CSIPHY_CLK_THS_SETTLE;
695 break;
696 case MIPI_DPHY_LANE_DATA0:
697 offset = CSIPHY_LANE0_THS_SETTLE;
698 break;
699 case MIPI_DPHY_LANE_DATA1:
700 offset = CSIPHY_LANE1_THS_SETTLE;
701 break;
702 case MIPI_DPHY_LANE_DATA2:
703 offset = CSIPHY_LANE2_THS_SETTLE;
704 break;
705 case MIPI_DPHY_LANE_DATA3:
706 offset = CSIPHY_LANE3_THS_SETTLE;
707 break;
708 default:
709 return;
710 }
711
712 read_csiphy_reg(priv, offset, &val);
713 val = (val & ~0x7f) | hsfreq;
714 write_csiphy_reg(priv, offset, val);
715 }
716
get_remote_sensor(struct v4l2_subdev * sd)717 static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd)
718 {
719 struct media_pad *local, *remote;
720 struct media_entity *sensor_me;
721
722 local = &sd->entity.pads[MIPI_DPHY_RX_PAD_SINK];
723 remote = media_entity_remote_pad(local);
724 if (!remote) {
725 v4l2_warn(sd, "No link between dphy and sensor\n");
726 return NULL;
727 }
728
729 sensor_me = media_entity_remote_pad(local)->entity;
730 return media_entity_to_v4l2_subdev(sensor_me);
731 }
732
sd_to_sensor(struct mipidphy_priv * priv,struct v4l2_subdev * sd)733 static struct mipidphy_sensor *sd_to_sensor(struct mipidphy_priv *priv,
734 struct v4l2_subdev *sd)
735 {
736 int i;
737
738 for (i = 0; i < priv->num_sensors; ++i)
739 if (priv->sensors[i].sd == sd)
740 return &priv->sensors[i];
741
742 return NULL;
743 }
744
mipidphy_get_sensor_data_rate(struct v4l2_subdev * sd)745 static int mipidphy_get_sensor_data_rate(struct v4l2_subdev *sd)
746 {
747 struct mipidphy_priv *priv = to_dphy_priv(sd);
748 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
749 struct v4l2_ctrl *link_freq;
750 struct v4l2_querymenu qm = { .id = V4L2_CID_LINK_FREQ, };
751 int ret;
752
753 if (!sensor_sd)
754 return -ENODEV;
755
756 link_freq = v4l2_ctrl_find(sensor_sd->ctrl_handler, V4L2_CID_LINK_FREQ);
757 if (!link_freq) {
758 v4l2_warn(sd, "No pixel rate control in subdev\n");
759 return -EPIPE;
760 }
761
762 qm.index = v4l2_ctrl_g_ctrl(link_freq);
763 ret = v4l2_querymenu(sensor_sd->ctrl_handler, &qm);
764 if (ret < 0) {
765 v4l2_err(sd, "Failed to get menu item\n");
766 return ret;
767 }
768
769 if (!qm.value) {
770 v4l2_err(sd, "Invalid link_freq\n");
771 return -EINVAL;
772 }
773 priv->data_rate_mbps = qm.value * 2;
774 do_div(priv->data_rate_mbps, 1000 * 1000);
775 v4l2_info(sd, "data_rate_mbps %lld\n", priv->data_rate_mbps);
776 return 0;
777 }
778
mipidphy_update_sensor_mbus(struct v4l2_subdev * sd)779 static int mipidphy_update_sensor_mbus(struct v4l2_subdev *sd)
780 {
781 struct mipidphy_priv *priv = to_dphy_priv(sd);
782 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
783 struct mipidphy_sensor *sensor;
784 struct v4l2_mbus_config mbus;
785 int ret;
786
787 if (!sensor_sd)
788 return -ENODEV;
789 sensor = sd_to_sensor(priv, sensor_sd);
790 if (!sensor)
791 return -ENODEV;
792 ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, &mbus);
793 if (ret)
794 return ret;
795
796 sensor->mbus = mbus;
797 switch (mbus.flags & V4L2_MBUS_CSI2_LANES) {
798 case V4L2_MBUS_CSI2_1_LANE:
799 sensor->lanes = 1;
800 break;
801 case V4L2_MBUS_CSI2_2_LANE:
802 sensor->lanes = 2;
803 break;
804 case V4L2_MBUS_CSI2_3_LANE:
805 sensor->lanes = 3;
806 break;
807 case V4L2_MBUS_CSI2_4_LANE:
808 sensor->lanes = 4;
809 break;
810 default:
811 return -EINVAL;
812 }
813
814 return 0;
815 }
816
rk1126_mipidphy_dphy_sel(struct v4l2_subdev * sd)817 static void rk1126_mipidphy_dphy_sel(struct v4l2_subdev *sd)
818 {
819 struct mipidphy_priv *priv = to_dphy_priv(sd);
820 char *model;
821 u8 oldval, newval;
822
823 model = sd->v4l2_dev->mdev->model;
824 oldval = read_grf_reg(priv, GRF_DPHY_SEL);
825 newval = oldval;
826 if (!strncmp(model, "rkcif_lite_mipi_lvds", sizeof("rkcif_lite_mipi_lvds") - 1)) {
827 if (priv->phy_index == 0)
828 newval &= ~RV1126_GRF_PHY1_SEL_CIFLITE;
829 else
830 newval |= RV1126_GRF_PHY1_SEL_CIFLITE;
831 } else if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1)) {
832 if (priv->phy_index == 0)
833 newval &= ~RV1126_GRF_PHY1_SEL_CIF;
834 else
835 newval |= RV1126_GRF_PHY1_SEL_CIF;
836 } else {
837 if (priv->phy_index == 0)
838 newval &= ~RV1126_GRF_PHY1_SEL_ISP;
839 else
840 newval |= RV1126_GRF_PHY1_SEL_ISP;
841 }
842
843 if (newval != oldval)
844 write_grf_reg(priv, GRF_DPHY_SEL, newval);
845 }
846
mipidphy_s_stream_start(struct v4l2_subdev * sd)847 static int mipidphy_s_stream_start(struct v4l2_subdev *sd)
848 {
849 struct mipidphy_priv *priv = to_dphy_priv(sd);
850 int ret = 0;
851
852 if (priv->is_streaming)
853 return 0;
854
855 ret = mipidphy_get_sensor_data_rate(sd);
856 if (ret < 0)
857 return ret;
858
859 if (priv->drv_data->chip_id == CHIP_ID_RK1126)
860 rk1126_mipidphy_dphy_sel(sd);
861
862 mipidphy_update_sensor_mbus(sd);
863 priv->stream_on(priv, sd);
864
865 priv->is_streaming = true;
866
867 return 0;
868 }
869
mipidphy_s_stream_stop(struct v4l2_subdev * sd)870 static int mipidphy_s_stream_stop(struct v4l2_subdev *sd)
871 {
872 struct mipidphy_priv *priv = to_dphy_priv(sd);
873
874 if (!priv->is_streaming)
875 return 0;
876
877 if (priv->stream_off)
878 priv->stream_off(priv, sd);
879 priv->is_streaming = false;
880
881 return 0;
882 }
883
mipidphy_s_stream(struct v4l2_subdev * sd,int on)884 static int mipidphy_s_stream(struct v4l2_subdev *sd, int on)
885 {
886 int ret = 0;
887 struct mipidphy_priv *priv = to_dphy_priv(sd);
888
889 dev_info(priv->dev, "stream on:%d\n", on);
890 mutex_lock(&priv->mutex);
891 if (on)
892 ret = mipidphy_s_stream_start(sd);
893 else
894 ret = mipidphy_s_stream_stop(sd);
895 mutex_unlock(&priv->mutex);
896 return ret;
897 }
898
mipidphy_g_frame_interval(struct v4l2_subdev * sd,struct v4l2_subdev_frame_interval * fi)899 static int mipidphy_g_frame_interval(struct v4l2_subdev *sd,
900 struct v4l2_subdev_frame_interval *fi)
901 {
902 struct v4l2_subdev *sensor = get_remote_sensor(sd);
903
904 if (sensor)
905 return v4l2_subdev_call(sensor, video, g_frame_interval, fi);
906
907 return -EINVAL;
908 }
909
mipidphy_g_mbus_config(struct v4l2_subdev * sd,unsigned int pad_id,struct v4l2_mbus_config * config)910 static int mipidphy_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
911 struct v4l2_mbus_config *config)
912 {
913 struct mipidphy_priv *priv = to_dphy_priv(sd);
914 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
915 struct mipidphy_sensor *sensor;
916
917 if (!sensor_sd)
918 return -ENODEV;
919 sensor = sd_to_sensor(priv, sensor_sd);
920 if (!sensor)
921 return -ENODEV;
922 mipidphy_update_sensor_mbus(sd);
923 *config = sensor->mbus;
924
925 return 0;
926 }
927
mipidphy_s_power(struct v4l2_subdev * sd,int on)928 static int mipidphy_s_power(struct v4l2_subdev *sd, int on)
929 {
930 struct mipidphy_priv *priv = to_dphy_priv(sd);
931
932 if (on)
933 return pm_runtime_get_sync(priv->dev);
934 else
935 return pm_runtime_put(priv->dev);
936 }
937
mipidphy_runtime_suspend(struct device * dev)938 static int __maybe_unused mipidphy_runtime_suspend(struct device *dev)
939 {
940 struct media_entity *me = dev_get_drvdata(dev);
941 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
942 struct mipidphy_priv *priv = to_dphy_priv(sd);
943 int i, num_clks;
944
945 num_clks = priv->drv_data->num_clks;
946 for (i = num_clks - 1; i >= 0; i--)
947 if (!IS_ERR(priv->clks[i]))
948 clk_disable_unprepare(priv->clks[i]);
949
950 return 0;
951 }
952
mipidphy_runtime_resume(struct device * dev)953 static int __maybe_unused mipidphy_runtime_resume(struct device *dev)
954 {
955 struct media_entity *me = dev_get_drvdata(dev);
956 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
957 struct mipidphy_priv *priv = to_dphy_priv(sd);
958 int i, num_clks, ret;
959
960 num_clks = priv->drv_data->num_clks;
961 for (i = 0; i < num_clks; i++) {
962 if (!IS_ERR(priv->clks[i])) {
963 ret = clk_prepare_enable(priv->clks[i]);
964 if (ret < 0)
965 goto err;
966 }
967 }
968
969 return 0;
970 err:
971 while (--i >= 0)
972 clk_disable_unprepare(priv->clks[i]);
973 return ret;
974 }
975
976 /* dphy accepts all fmt/size from sensor */
mipidphy_get_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_format * fmt)977 static int mipidphy_get_set_fmt(struct v4l2_subdev *sd,
978 struct v4l2_subdev_pad_config *cfg,
979 struct v4l2_subdev_format *fmt)
980 {
981 struct mipidphy_priv *priv = to_dphy_priv(sd);
982 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
983 struct mipidphy_sensor *sensor;
984 int ret;
985 /*
986 * Do not allow format changes and just relay whatever
987 * set currently in the sensor.
988 */
989 if (!sensor_sd)
990 return -ENODEV;
991 sensor = sd_to_sensor(priv, sensor_sd);
992 if (!sensor)
993 return -ENODEV;
994 ret = v4l2_subdev_call(sensor_sd, pad, get_fmt, NULL, fmt);
995 if (!ret && fmt->pad == 0)
996 sensor->format = fmt->format;
997 return ret;
998 }
999
mipidphy_get_selection(struct v4l2_subdev * sd,struct v4l2_subdev_pad_config * cfg,struct v4l2_subdev_selection * sel)1000 static int mipidphy_get_selection(struct v4l2_subdev *sd,
1001 struct v4l2_subdev_pad_config *cfg,
1002 struct v4l2_subdev_selection *sel)
1003 {
1004 struct v4l2_subdev *sensor = get_remote_sensor(sd);
1005
1006 return v4l2_subdev_call(sensor, pad, get_selection, NULL, sel);
1007 }
1008
1009 static const struct v4l2_subdev_pad_ops mipidphy_subdev_pad_ops = {
1010 .set_fmt = mipidphy_get_set_fmt,
1011 .get_fmt = mipidphy_get_set_fmt,
1012 .get_selection = mipidphy_get_selection,
1013 .get_mbus_config = mipidphy_g_mbus_config,
1014 };
1015
1016 static const struct v4l2_subdev_core_ops mipidphy_core_ops = {
1017 .s_power = mipidphy_s_power,
1018 };
1019
1020 static const struct v4l2_subdev_video_ops mipidphy_video_ops = {
1021 .g_frame_interval = mipidphy_g_frame_interval,
1022 .s_stream = mipidphy_s_stream,
1023 };
1024
1025 static const struct v4l2_subdev_ops mipidphy_subdev_ops = {
1026 .core = &mipidphy_core_ops,
1027 .video = &mipidphy_video_ops,
1028 .pad = &mipidphy_subdev_pad_ops,
1029 };
1030
1031 /* These tables must be sorted by .range_h ascending. */
1032 static const struct hsfreq_range rk1808_rv1126_mipidphy_hsfreq_ranges[] = {
1033 { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
1034 { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
1035 { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
1036 {1399, 0x23}, {1599, 0x2d}, {1799, 0x32}, {1999, 0x37},
1037 {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}
1038 };
1039
1040 static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = {
1041 { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
1042 { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
1043 { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
1044 { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
1045 { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
1046 { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
1047 { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
1048 { 999, 0x1a}
1049 };
1050
1051 static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = {
1052 { 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
1053 { 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
1054 { 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
1055 {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
1056 };
1057
1058 static const struct hsfreq_range rk3326s_mipidphy_hsfreq_ranges[] = {
1059 { 109, 0x02}, { 149, 0x03}, { 199, 0x06}, { 249, 0x06},
1060 { 299, 0x06}, { 399, 0x08}, { 499, 0x0b}, { 599, 0x0e},
1061 { 699, 0x10}, { 799, 0x12}, { 999, 0x16}, {1199, 0x1e},
1062 };
1063
1064 static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = {
1065 { 109, 0x00}, { 149, 0x01}, { 199, 0x02}, { 249, 0x03},
1066 { 299, 0x04}, { 399, 0x05}, { 499, 0x06}, { 599, 0x07},
1067 { 699, 0x08}, { 799, 0x09}, { 899, 0x0a}, {1099, 0x0b},
1068 {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}
1069 };
1070
1071 static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = {
1072 { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01},
1073 { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12},
1074 { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23},
1075 { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15},
1076 { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07},
1077 { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09},
1078 { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a},
1079 { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b},
1080 {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c},
1081 {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c}
1082 };
1083
1084 static const char * const rk1808_mipidphy_clks[] = {
1085 "pclk",
1086 };
1087
1088 static const char * const rk3288_mipidphy_clks[] = {
1089 "dphy-ref",
1090 "pclk",
1091 };
1092
1093 static const char * const rk3326_mipidphy_clks[] = {
1094 "dphy-ref",
1095 };
1096
1097 static const char * const rk3368_mipidphy_clks[] = {
1098 "pclk_dphyrx",
1099 };
1100
1101 static const char * const rk3399_mipidphy_clks[] = {
1102 "dphy-ref",
1103 "dphy-cfg",
1104 "grf",
1105 "pclk_mipi_dsi",
1106 };
1107
1108 static const char * const rv1126_mipidphy_clks[] = {
1109 "pclk",
1110 };
1111
default_mipidphy_individual_init(struct mipidphy_priv * priv)1112 static void default_mipidphy_individual_init(struct mipidphy_priv *priv)
1113 {
1114 }
1115
rk3368_mipidphy_individual_init(struct mipidphy_priv * priv)1116 static void rk3368_mipidphy_individual_init(struct mipidphy_priv *priv)
1117 {
1118 /* isp select */
1119 write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1);
1120 }
1121
rk3399_mipidphy_individual_init(struct mipidphy_priv * priv)1122 static void rk3399_mipidphy_individual_init(struct mipidphy_priv *priv)
1123 {
1124 /*
1125 * According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi
1126 * will affect txrx dphy in default state of grf_soc_con24.
1127 */
1128 write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);
1129 write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
1130 write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 0);
1131
1132 write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
1133 }
1134
rv1126_mipidphy_individual_init(struct mipidphy_priv * priv)1135 static void rv1126_mipidphy_individual_init(struct mipidphy_priv *priv)
1136 {
1137 struct device *dev = priv->dev;
1138 struct device_node *parent = dev->of_node;
1139 struct device_node *remote = NULL;
1140 u8 val, sel;
1141
1142 priv->grf_regs = priv->phy_index ?
1143 rv1126_grf_dphy1_regs : rv1126_grf_dphy0_regs;
1144 val = read_grf_reg(priv, GRF_DPHY_SEL);
1145 /* get port1 remote endpoint info */
1146 remote = of_graph_get_remote_node(parent, 1, 0);
1147 if (remote) {
1148 if (strstr(remote->name, "isp"))
1149 sel = !priv->phy_index ? 0 : RV1126_GRF_PHY1_SEL_ISP;
1150 else
1151 sel = !priv->phy_index ? 0 :
1152 RV1126_GRF_PHY1_SEL_CIF | RV1126_GRF_PHY1_SEL_CIFLITE;
1153 of_node_put(remote);
1154 write_grf_reg(priv, GRF_DPHY_SEL, val | sel);
1155 }
1156 }
1157
mipidphy_rx_stream_on(struct mipidphy_priv * priv,struct v4l2_subdev * sd)1158 static int mipidphy_rx_stream_on(struct mipidphy_priv *priv,
1159 struct v4l2_subdev *sd)
1160 {
1161 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
1162 struct mipidphy_sensor *sensor;
1163 const struct dphy_drv_data *drv_data = priv->drv_data;
1164 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
1165 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
1166 int i, hsfreq = 0;
1167
1168 if (!sensor_sd)
1169 return -ENODEV;
1170 sensor = sd_to_sensor(priv, sensor_sd);
1171 if (!sensor)
1172 return -ENODEV;
1173
1174 for (i = 0; i < num_hsfreq_ranges; i++) {
1175 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1176 hsfreq = hsfreq_ranges[i].cfg_bit;
1177 break;
1178 }
1179 }
1180
1181 if (i == num_hsfreq_ranges) {
1182 i = num_hsfreq_ranges - 1;
1183 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
1184 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
1185 hsfreq = hsfreq_ranges[i].cfg_bit;
1186 }
1187
1188 /* RK3288 isp connected to phy0-rx */
1189 write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 0);
1190
1191 /* Belowed is the sequence of mipi configuration */
1192 /* Step1: set RSTZ = 1'b0, phy0 controlled by isp0 */
1193
1194 /* Step2: set SHUTDOWNZ = 1'b0, controlled by isp0 */
1195
1196 /* Step3: set TESTCLEAR = 1'b1 */
1197 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1);
1198 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 1);
1199 usleep_range(100, 150);
1200
1201 /* Step4: apply REFCLK signal with the appropriate frequency */
1202
1203 /* Step5: apply CFG_CLK signal with the appropriate frequency */
1204
1205 /* Step6: set MASTERSLAVEZ = 1'b0 (for SLAVE), phy0 default is slave */
1206
1207 /* Step7: set BASEDIR_N = 1’b1 (for SLAVE), phy0 default is slave */
1208
1209 /*
1210 * Step8: set all REQUEST inputs to zero, need to wait 15ns:
1211 * step8.1:set lan turndisab as 1
1212 * step8.2:set lan turnrequest as 0
1213 */
1214 write_grf_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf);
1215 write_grf_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0);
1216 write_grf_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0);
1217 usleep_range(100, 150);
1218
1219 /* Step9: set TESTCLR to low, need to wait 15ns */
1220 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 0);
1221 usleep_range(100, 150);
1222
1223 /*
1224 * Step10: configure Test Code 0x44 hsfreqrange according to values
1225 * step10.1:set clock lane
1226 * step10.2:set hsfreqrange by lane0(test code 0x44)
1227 */
1228 hsfreq <<= 1;
1229 mipidphy0_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
1230 mipidphy0_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq);
1231 mipidphy0_wr_reg(priv, LANE1_HS_RX_CONTROL, hsfreq);
1232 mipidphy0_wr_reg(priv, LANE2_HS_RX_CONTROL, hsfreq);
1233 mipidphy0_wr_reg(priv, LANE3_HS_RX_CONTROL, hsfreq);
1234
1235 /* Step11: Configure analog references: of Test Code 0x22 */
1236
1237 /* Step12: Set ENABLE_N=1'b1, need to wait 5ns */
1238 /* set lane num */
1239 write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0));
1240
1241 /* Step13: Set SHUTDOWNZ=1'b1, controlled by isp need to wait 5ns */
1242
1243 /* Step14: Set RSTZ=1'b1, controlled by isp */
1244
1245 /*
1246 * Step15: Wait until STOPSTATEDATA_N & STOPSTATECLK
1247 * outputs are asserted
1248 */
1249
1250 usleep_range(100, 150);
1251
1252 return 0;
1253 }
1254
mipidphy_txrx_stream_on(struct mipidphy_priv * priv,struct v4l2_subdev * sd)1255 static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv,
1256 struct v4l2_subdev *sd)
1257 {
1258 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
1259 struct mipidphy_sensor *sensor;
1260 const struct dphy_drv_data *drv_data = priv->drv_data;
1261 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
1262 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
1263 int i, hsfreq = 0;
1264
1265 if (!sensor_sd)
1266 return -ENODEV;
1267 sensor = sd_to_sensor(priv, sensor_sd);
1268 if (!sensor)
1269 return -ENODEV;
1270
1271 for (i = 0; i < num_hsfreq_ranges; i++) {
1272 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1273 hsfreq = hsfreq_ranges[i].cfg_bit;
1274 break;
1275 }
1276 }
1277
1278 if (i == num_hsfreq_ranges) {
1279 i = num_hsfreq_ranges - 1;
1280 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
1281 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
1282 hsfreq = hsfreq_ranges[i].cfg_bit;
1283 }
1284
1285 /*
1286 *Config rk3288:
1287 *step1:rk3288 isp connected to phy1-rx
1288 *step2:rk3288 phy1-rx test bus connected to csi host
1289 *step3:rk3288 phy1-rx source selected as: isp = 1'b1,csi-host = 1'b0
1290 */
1291 write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1);
1292 write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1);
1293 write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1);
1294
1295 /*
1296 * Config rk3399：
1297 * step1:rk3399 phy1-rx source selected as:1'b0=isp1,1'b1=isp0
1298 */
1299 write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0);
1300
1301 /* Belowed is the sequence of mipi configuration */
1302 /* Step1: set RSTZ = 1'b0, phy1-rx controlled by isp */
1303
1304 /* Step2: set SHUTDOWNZ = 1'b0, phy1-rx controlled by isp */
1305
1306 /* Step3: set TESTCLR= 1'b1,TESTCLK=1'b1 */
1307 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLR | PHY_TESTCLK);
1308 usleep_range(100, 150);
1309
1310 /* Step4: apply REFCLK signal with the appropriate frequency */
1311
1312 /* Step5: apply CFG_CLK signal with the appropriate frequency */
1313
1314 /*
1315 * Step6: set MASTERSLAVEZ = 1'b0 (for SLAVE),
1316 * phy1 is set as slave,controlled by isp
1317 */
1318 write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0);
1319
1320 /*
1321 * Step7: set BASEDIR_N = 1’b1 (for SLAVE),
1322 * phy1 is set as slave,controlled by isp
1323 */
1324 write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1);
1325
1326 /* Step8: set all REQUEST inputs to zero, need to wait 15ns */
1327 write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0);
1328 write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0);
1329 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0);
1330 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf);
1331 usleep_range(100, 150);
1332
1333 /* Step9: set TESTCLR=1'b0,TESTCLK=1'b1 need to wait 15ns */
1334 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLK);
1335 usleep_range(100, 150);
1336
1337 /*
1338 * Step10: configure Test Code 0x44 hsfreqrange according to values
1339 * step10.1:set clock lane
1340 * step10.2:set hsfreqrange by lane0(test code 0x44)
1341 */
1342 hsfreq <<= 1;
1343 mipidphy1_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0);
1344 mipidphy1_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq);
1345 mipidphy1_wr_reg(priv, LANE1_HS_RX_CONTROL, 0);
1346 mipidphy1_wr_reg(priv, LANE2_HS_RX_CONTROL, 0);
1347 mipidphy1_wr_reg(priv, LANE3_HS_RX_CONTROL, 0);
1348
1349 /* Step11: Configure analog references: of Test Code 0x22 */
1350
1351 /*
1352 * Step12: Set ENABLE_N=1'b1, need to wait 5ns
1353 * Set lane num:
1354 * for 3288,controlled by isp,enable lanes actually
1355 * is set by grf_soc_con9[12:15];
1356 * for 3399,controlled by isp1,enable lanes actually
1357 * is set by isp1,
1358 * if run 3399 here operates grf_soc_con23[0:3]
1359 */
1360 write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE,
1361 GENMASK(sensor->lanes - 1, 0));
1362
1363 /*
1364 * Step13:Set SHUTDOWNZ=1'b1, phy1-rx controlled by isp,
1365 * need to wait 5ns
1366 */
1367
1368 /* Step14:Set RSTZ=1'b1, phy1-rx controlled by isp*/
1369
1370 /*
1371 * Step15:Wait until STOPSTATEDATA_N & STOPSTATECLK
1372 * outputs are asserted
1373 */
1374
1375 usleep_range(100, 150);
1376
1377 return 0;
1378 }
1379
csi_mipidphy_stream_on(struct mipidphy_priv * priv,struct v4l2_subdev * sd)1380 static int csi_mipidphy_stream_on(struct mipidphy_priv *priv,
1381 struct v4l2_subdev *sd)
1382 {
1383 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd);
1384 struct mipidphy_sensor *sensor;
1385 const struct dphy_drv_data *drv_data = priv->drv_data;
1386 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges;
1387 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges;
1388 int i, hsfreq = 0;
1389 u32 val = 0;
1390 u32 clk_mode = 0x03;
1391
1392 if (!sensor_sd)
1393 return -ENODEV;
1394 sensor = sd_to_sensor(priv, sensor_sd);
1395 if (!sensor)
1396 return -ENODEV;
1397
1398 write_grf_reg(priv, GRF_DVP_V18SEL, 0x1);
1399
1400 /* phy start */
1401 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe4);
1402
1403 /* set data lane num and enable clock lane */
1404 write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE,
1405 ((GENMASK(sensor->lanes - 1, 0) << MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) |
1406 (0x1 << MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT) | 0x1));
1407
1408 /* Reset dphy analog part */
1409 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe0);
1410 usleep_range(500, 1000);
1411
1412 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) {
1413 /* Reset dphy digital part */
1414 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1e);
1415 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1f);
1416 if (drv_data->chip_id == CHIP_ID_RK3326S) {
1417 if (sensor->mbus.flags & V4L2_MBUS_CSI2_CONTINUOUS_CLOCK)
1418 clk_mode = 0x03;
1419 else if (sensor->mbus.flags & V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK)
1420 clk_mode = 0;
1421 write_csiphy_reg(priv, CSIPHY_CLK_MODE, clk_mode);
1422 }
1423 } else {
1424 /* Disable MIPI internal logical and switch to LVDS bank */
1425 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x3e);
1426 /* Enable LVDS mode */
1427 write_csiphy_reg(priv, CSIPHY_MIPI_LVDS_MODEL, 0x4);
1428 switch (sensor->format.code) {
1429 case MEDIA_BUS_FMT_Y12_1X12:
1430 case MEDIA_BUS_FMT_SRGGB12_1X12:
1431 case MEDIA_BUS_FMT_SBGGR12_1X12:
1432 case MEDIA_BUS_FMT_SGBRG12_1X12:
1433 case MEDIA_BUS_FMT_SGRBG12_1X12:
1434 val = 0x1f; //12bit
1435 break;
1436 case MEDIA_BUS_FMT_Y10_1X10:
1437 case MEDIA_BUS_FMT_SBGGR10_1X10:
1438 case MEDIA_BUS_FMT_SRGGB10_1X10:
1439 case MEDIA_BUS_FMT_SGBRG10_1X10:
1440 case MEDIA_BUS_FMT_SGRBG10_1X10:
1441 val = 0xf; //10bit
1442 break;
1443 default:
1444 val = 0x2f; //8bit
1445 }
1446 /* Enable LVDS internal logical and select bit mode */
1447 write_csiphy_reg(priv, CSIPHY_LVDS_MODE, val);
1448 }
1449
1450 /* not into receive mode/wait stopstate */
1451 write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0);
1452
1453 /* enable calibration */
1454 if (priv->data_rate_mbps > 1500) {
1455 write_csiphy_reg(priv, CSIPHY_CLK_CALIB_ENABLE, 0x80);
1456 if (sensor->lanes > 0x00)
1457 write_csiphy_reg(priv, CSIPHY_LANE0_CALIB_ENABLE, 0x80);
1458 if (sensor->lanes > 0x01)
1459 write_csiphy_reg(priv, CSIPHY_LANE1_CALIB_ENABLE, 0x80);
1460 if (sensor->lanes > 0x02)
1461 write_csiphy_reg(priv, CSIPHY_LANE2_CALIB_ENABLE, 0x80);
1462 if (sensor->lanes > 0x03)
1463 write_csiphy_reg(priv, CSIPHY_LANE3_CALIB_ENABLE, 0x80);
1464 }
1465
1466 /* set clock lane and data lane */
1467 for (i = 0; i < num_hsfreq_ranges; i++) {
1468 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) {
1469 hsfreq = hsfreq_ranges[i].cfg_bit;
1470 break;
1471 }
1472 }
1473
1474 if (i == num_hsfreq_ranges) {
1475 i = num_hsfreq_ranges - 1;
1476 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps",
1477 priv->data_rate_mbps, hsfreq_ranges[i].range_h + 1);
1478 hsfreq = hsfreq_ranges[i].cfg_bit;
1479 }
1480
1481 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_CLOCK);
1482 if (sensor->lanes > 0x00)
1483 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA0);
1484 if (sensor->lanes > 0x01)
1485 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA1);
1486 if (sensor->lanes > 0x02)
1487 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA2);
1488 if (sensor->lanes > 0x03)
1489 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA3);
1490
1491 write_grf_reg(priv, GRF_DPHY_CLK_INV_SEL, 0x1);
1492 write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1);
1493 write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN,
1494 GENMASK(sensor->lanes - 1, 0));
1495 return 0;
1496 }
1497
csi_mipidphy_stream_off(struct mipidphy_priv * priv,struct v4l2_subdev * sd)1498 static int csi_mipidphy_stream_off(struct mipidphy_priv *priv,
1499 struct v4l2_subdev *sd)
1500 {
1501 /* disable all lanes */
1502 write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE, 0x01);
1503 /* disable pll and ldo */
1504 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe3);
1505 usleep_range(500, 1000);
1506
1507 return 0;
1508 }
1509
1510 static const struct dphy_drv_data rk1808_mipidphy_drv_data = {
1511 .clks = rk1808_mipidphy_clks,
1512 .num_clks = ARRAY_SIZE(rk1808_mipidphy_clks),
1513 .hsfreq_ranges = rk1808_rv1126_mipidphy_hsfreq_ranges,
1514 .num_hsfreq_ranges = ARRAY_SIZE(rk1808_rv1126_mipidphy_hsfreq_ranges),
1515 .grf_regs = rk1808_grf_dphy_regs,
1516 .csiphy_regs = rk1808_csiphy_regs,
1517 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1518 .individual_init = default_mipidphy_individual_init,
1519 .chip_id = CHIP_ID_RK1808,
1520 };
1521
1522 static const struct dphy_drv_data rk3288_mipidphy_drv_data = {
1523 .clks = rk3288_mipidphy_clks,
1524 .num_clks = ARRAY_SIZE(rk3288_mipidphy_clks),
1525 .hsfreq_ranges = rk3288_mipidphy_hsfreq_ranges,
1526 .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges),
1527 .grf_regs = rk3288_grf_dphy_regs,
1528 .txrx_regs = rk3288_txrx_regs,
1529 .ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
1530 .individual_init = default_mipidphy_individual_init,
1531 .chip_id = CHIP_ID_RK3288,
1532 };
1533
1534 static const struct dphy_drv_data rk3326_mipidphy_drv_data = {
1535 .clks = rk3326_mipidphy_clks,
1536 .num_clks = ARRAY_SIZE(rk3326_mipidphy_clks),
1537 .hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges,
1538 .num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges),
1539 .grf_regs = rk3326_grf_dphy_regs,
1540 .csiphy_regs = rk3326_csiphy_regs,
1541 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1542 .individual_init = default_mipidphy_individual_init,
1543 .chip_id = CHIP_ID_RK3326,
1544 };
1545
1546 static const struct dphy_drv_data rk3326s_mipidphy_drv_data = {
1547 .clks = rk3326_mipidphy_clks,
1548 .num_clks = ARRAY_SIZE(rk3326_mipidphy_clks),
1549 .hsfreq_ranges = rk3326s_mipidphy_hsfreq_ranges,
1550 .num_hsfreq_ranges = ARRAY_SIZE(rk3326s_mipidphy_hsfreq_ranges),
1551 .grf_regs = rk3326_grf_dphy_regs,
1552 .csiphy_regs = rk3326s_csiphy_regs,
1553 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1554 .individual_init = default_mipidphy_individual_init,
1555 .chip_id = CHIP_ID_RK3326S,
1556 };
1557
1558 static const struct dphy_drv_data rk3368_mipidphy_drv_data = {
1559 .clks = rk3368_mipidphy_clks,
1560 .num_clks = ARRAY_SIZE(rk3368_mipidphy_clks),
1561 .hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges,
1562 .num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges),
1563 .grf_regs = rk3368_grf_dphy_regs,
1564 .csiphy_regs = rk3368_csiphy_regs,
1565 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1566 .individual_init = rk3368_mipidphy_individual_init,
1567 .chip_id = CHIP_ID_RK3368,
1568 };
1569
1570 static const struct dphy_drv_data rk3399_mipidphy_drv_data = {
1571 .clks = rk3399_mipidphy_clks,
1572 .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks),
1573 .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges,
1574 .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges),
1575 .grf_regs = rk3399_grf_dphy_regs,
1576 .txrx_regs = rk3399_txrx_regs,
1577 .ctl_type = MIPI_DPHY_CTL_GRF_ONLY,
1578 .individual_init = rk3399_mipidphy_individual_init,
1579 .chip_id = CHIP_ID_RK3399,
1580 };
1581
1582 static const struct dphy_drv_data rv1126_mipidphy_drv_data = {
1583 .clks = rv1126_mipidphy_clks,
1584 .num_clks = ARRAY_SIZE(rv1126_mipidphy_clks),
1585 .hsfreq_ranges = rk1808_rv1126_mipidphy_hsfreq_ranges,
1586 .num_hsfreq_ranges = ARRAY_SIZE(rk1808_rv1126_mipidphy_hsfreq_ranges),
1587 .csiphy_regs = rv1126_csiphy_regs,
1588 .ctl_type = MIPI_DPHY_CTL_CSI_HOST,
1589 .individual_init = rv1126_mipidphy_individual_init,
1590 .chip_id = CHIP_ID_RK1126,
1591 };
1592
1593 static const struct of_device_id rockchip_mipidphy_match_id[] = {
1594 {
1595 .compatible = "rockchip,rk1808-mipi-dphy-rx",
1596 .data = &rk1808_mipidphy_drv_data,
1597 },
1598 {
1599 .compatible = "rockchip,rk3288-mipi-dphy",
1600 .data = &rk3288_mipidphy_drv_data,
1601 },
1602 {
1603 .compatible = "rockchip,rk3326-mipi-dphy",
1604 .data = &rk3326_mipidphy_drv_data,
1605 },
1606 {
1607 .compatible = "rockchip,rk3326s-mipi-dphy",
1608 .data = &rk3326s_mipidphy_drv_data,
1609 },
1610 {
1611 .compatible = "rockchip,rk3368-mipi-dphy",
1612 .data = &rk3368_mipidphy_drv_data,
1613 },
1614 {
1615 .compatible = "rockchip,rk3399-mipi-dphy",
1616 .data = &rk3399_mipidphy_drv_data,
1617 },
1618 {
1619 .compatible = "rockchip,rv1126-csi-dphy",
1620 .data = &rv1126_mipidphy_drv_data,
1621 },
1622 {}
1623 };
1624 MODULE_DEVICE_TABLE(of, rockchip_mipidphy_match_id);
1625
1626 /* The .bound() notifier callback when a match is found */
1627 static int
rockchip_mipidphy_notifier_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)1628 rockchip_mipidphy_notifier_bound(struct v4l2_async_notifier *notifier,
1629 struct v4l2_subdev *sd,
1630 struct v4l2_async_subdev *asd)
1631 {
1632 struct mipidphy_priv *priv = container_of(notifier,
1633 struct mipidphy_priv,
1634 notifier);
1635 struct sensor_async_subdev *s_asd = container_of(asd,
1636 struct sensor_async_subdev, asd);
1637 struct mipidphy_sensor *sensor;
1638 unsigned int pad, ret;
1639
1640 if (priv->num_sensors == ARRAY_SIZE(priv->sensors))
1641 return -EBUSY;
1642
1643 sensor = &priv->sensors[priv->num_sensors++];
1644 sensor->lanes = s_asd->lanes;
1645 sensor->mbus = s_asd->mbus;
1646 sensor->sd = sd;
1647 dev_info(priv->dev, "match %s:bus type %d\n", sd->name, s_asd->mbus.type);
1648
1649 for (pad = 0; pad < sensor->sd->entity.num_pads; pad++)
1650 if (sensor->sd->entity.pads[pad].flags & MEDIA_PAD_FL_SOURCE)
1651 break;
1652
1653 if (pad == sensor->sd->entity.num_pads) {
1654 dev_err(priv->dev,
1655 "failed to find src pad for %s\n",
1656 sensor->sd->name);
1657
1658 return -ENXIO;
1659 }
1660
1661 ret = media_create_pad_link(
1662 &sensor->sd->entity, pad,
1663 &priv->sd.entity, MIPI_DPHY_RX_PAD_SINK,
1664 priv->num_sensors != 1 ? 0 : MEDIA_LNK_FL_ENABLED);
1665 if (ret) {
1666 dev_err(priv->dev,
1667 "failed to create link for %s\n",
1668 sensor->sd->name);
1669 return ret;
1670 }
1671
1672 return 0;
1673 }
1674
1675 /* The .unbind callback */
1676 static void
rockchip_mipidphy_notifier_unbind(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_subdev * asd)1677 rockchip_mipidphy_notifier_unbind(struct v4l2_async_notifier *notifier,
1678 struct v4l2_subdev *sd,
1679 struct v4l2_async_subdev *asd)
1680 {
1681 struct mipidphy_priv *priv = container_of(notifier,
1682 struct mipidphy_priv,
1683 notifier);
1684 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sd);
1685
1686 if (sensor)
1687 sensor->sd = NULL;
1688 }
1689
1690 static const struct
1691 v4l2_async_notifier_operations rockchip_mipidphy_async_ops = {
1692 .bound = rockchip_mipidphy_notifier_bound,
1693 .unbind = rockchip_mipidphy_notifier_unbind,
1694 };
1695
rockchip_mipidphy_fwnode_parse(struct device * dev,struct v4l2_fwnode_endpoint * vep,struct v4l2_async_subdev * asd)1696 static int rockchip_mipidphy_fwnode_parse(struct device *dev,
1697 struct v4l2_fwnode_endpoint *vep,
1698 struct v4l2_async_subdev *asd)
1699 {
1700 struct sensor_async_subdev *s_asd =
1701 container_of(asd, struct sensor_async_subdev, asd);
1702 struct v4l2_mbus_config *config = &s_asd->mbus;
1703
1704 if (vep->base.port != 0) {
1705 dev_err(dev, "The PHY has only port 0\n");
1706 return -EINVAL;
1707 }
1708
1709 if (vep->bus_type == V4L2_MBUS_CSI2_DPHY) {
1710 config->type = V4L2_MBUS_CSI2_DPHY;
1711 config->flags = vep->bus.mipi_csi2.flags;
1712 s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes;
1713 } else if (vep->bus_type == V4L2_MBUS_CCP2) {
1714 /* V4L2_MBUS_CCP2 for lvds */
1715 config->type = V4L2_MBUS_CCP2;
1716 s_asd->lanes = vep->bus.mipi_csi1.data_lane;
1717 } else {
1718 dev_err(dev, "Only CSI2 and CCP2 bus type is currently supported\n");
1719 return -EINVAL;
1720 }
1721
1722 switch (s_asd->lanes) {
1723 case 1:
1724 config->flags |= V4L2_MBUS_CSI2_1_LANE;
1725 break;
1726 case 2:
1727 config->flags |= V4L2_MBUS_CSI2_2_LANE;
1728 break;
1729 case 3:
1730 config->flags |= V4L2_MBUS_CSI2_3_LANE;
1731 break;
1732 case 4:
1733 config->flags |= V4L2_MBUS_CSI2_4_LANE;
1734 break;
1735 default:
1736 return -EINVAL;
1737 }
1738
1739 return 0;
1740 }
1741
rockchip_mipidphy_media_init(struct mipidphy_priv * priv)1742 static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv)
1743 {
1744 int ret;
1745
1746 priv->pads[MIPI_DPHY_RX_PAD_SOURCE].flags =
1747 MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT;
1748 priv->pads[MIPI_DPHY_RX_PAD_SINK].flags =
1749 MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT;
1750 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1751 ret = media_entity_pads_init(&priv->sd.entity,
1752 MIPI_DPHY_RX_PADS_NUM, priv->pads);
1753 if (ret < 0)
1754 return ret;
1755
1756 v4l2_async_notifier_init(&priv->notifier);
1757
1758 ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port(
1759 priv->dev, &priv->notifier,
1760 sizeof(struct sensor_async_subdev), 0,
1761 rockchip_mipidphy_fwnode_parse);
1762 if (ret < 0)
1763 return ret;
1764
1765 priv->sd.subdev_notifier = &priv->notifier;
1766 priv->notifier.ops = &rockchip_mipidphy_async_ops;
1767 ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier);
1768 if (ret) {
1769 dev_err(priv->dev,
1770 "failed to register async notifier : %d\n", ret);
1771 v4l2_async_notifier_cleanup(&priv->notifier);
1772 return ret;
1773 }
1774
1775 return v4l2_async_register_subdev(&priv->sd);
1776 }
1777
rockchip_mipidphy_probe(struct platform_device * pdev)1778 static int rockchip_mipidphy_probe(struct platform_device *pdev)
1779 {
1780 struct device *dev = &pdev->dev;
1781 struct v4l2_subdev *sd;
1782 struct mipidphy_priv *priv;
1783 struct regmap *grf;
1784 struct resource *res;
1785 const struct of_device_id *of_id;
1786 const struct dphy_drv_data *drv_data;
1787 int i, ret;
1788
1789 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1790 if (!priv)
1791 return -ENOMEM;
1792 priv->dev = dev;
1793
1794 of_id = of_match_device(rockchip_mipidphy_match_id, dev);
1795 if (!of_id)
1796 return -EINVAL;
1797
1798 grf = syscon_node_to_regmap(dev->parent->of_node);
1799 if (IS_ERR(grf)) {
1800 grf = syscon_regmap_lookup_by_phandle(dev->of_node,
1801 "rockchip,grf");
1802 if (IS_ERR(grf)) {
1803 dev_err(dev, "Can't find GRF syscon\n");
1804 return -ENODEV;
1805 }
1806 }
1807 priv->regmap_grf = grf;
1808
1809 priv->phy_index = of_alias_get_id(dev->of_node, "dphy");
1810 if (priv->phy_index < 0)
1811 priv->phy_index = 0;
1812
1813 drv_data = of_id->data;
1814 if (soc_is_px30s())
1815 drv_data = &rk3326s_mipidphy_drv_data;
1816
1817 for (i = 0; i < drv_data->num_clks; i++) {
1818 priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]);
1819
1820 if (IS_ERR(priv->clks[i]))
1821 dev_dbg(dev, "Failed to get %s\n", drv_data->clks[i]);
1822 }
1823
1824 priv->grf_regs = drv_data->grf_regs;
1825 priv->txrx_regs = drv_data->txrx_regs;
1826 priv->csiphy_regs = drv_data->csiphy_regs;
1827 priv->drv_data = drv_data;
1828 if (drv_data->ctl_type == MIPI_DPHY_CTL_CSI_HOST) {
1829 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1830 priv->csihost_base_addr = devm_ioremap_resource(dev, res);
1831 priv->stream_on = csi_mipidphy_stream_on;
1832 priv->stream_off = csi_mipidphy_stream_off;
1833 } else {
1834 priv->stream_on = mipidphy_txrx_stream_on;
1835 priv->txrx_base_addr = NULL;
1836 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1837 priv->txrx_base_addr = devm_ioremap_resource(dev, res);
1838 if (IS_ERR(priv->txrx_base_addr))
1839 priv->stream_on = mipidphy_rx_stream_on;
1840 priv->stream_off = NULL;
1841 }
1842
1843 sd = &priv->sd;
1844 mutex_init(&priv->mutex);
1845 v4l2_subdev_init(sd, &mipidphy_subdev_ops);
1846 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1847 snprintf(sd->name, sizeof(sd->name), "rockchip-mipi-dphy-rx");
1848 sd->dev = dev;
1849
1850 platform_set_drvdata(pdev, &sd->entity);
1851
1852 ret = rockchip_mipidphy_media_init(priv);
1853 if (ret < 0)
1854 goto destroy_mutex;
1855
1856 pm_runtime_enable(&pdev->dev);
1857 drv_data->individual_init(priv);
1858 return 0;
1859
1860 destroy_mutex:
1861 mutex_destroy(&priv->mutex);
1862 return 0;
1863 }
1864
rockchip_mipidphy_remove(struct platform_device * pdev)1865 static int rockchip_mipidphy_remove(struct platform_device *pdev)
1866 {
1867 struct media_entity *me = platform_get_drvdata(pdev);
1868 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me);
1869 struct mipidphy_priv *priv = platform_get_drvdata(pdev);
1870
1871 media_entity_cleanup(&sd->entity);
1872
1873 pm_runtime_disable(&pdev->dev);
1874 mutex_destroy(&priv->mutex);
1875 return 0;
1876 }
1877
1878 static const struct dev_pm_ops rockchip_mipidphy_pm_ops = {
1879 SET_RUNTIME_PM_OPS(mipidphy_runtime_suspend,
1880 mipidphy_runtime_resume, NULL)
1881 };
1882
1883 static struct platform_driver rockchip_isp_mipidphy_driver = {
1884 .probe = rockchip_mipidphy_probe,
1885 .remove = rockchip_mipidphy_remove,
1886 .driver = {
1887 .name = "rockchip-mipi-dphy-rx",
1888 .pm = &rockchip_mipidphy_pm_ops,
1889 .of_match_table = rockchip_mipidphy_match_id,
1890 },
1891 };
1892
1893 module_platform_driver(rockchip_isp_mipidphy_driver);
1894 MODULE_AUTHOR("Rockchip Camera/ISP team");
1895 MODULE_DESCRIPTION("Rockchip MIPI RX DPHY driver");
1896 MODULE_LICENSE("Dual BSD/GPL");
1897