xref: /OK3568_Linux_fs/kernel/drivers/phy/rockchip/phy-rockchip-inno-video-phy.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/clk.h>
10*4882a593Smuzhiyun #include <linux/delay.h>
11*4882a593Smuzhiyun #include <linux/init.h>
12*4882a593Smuzhiyun #include <linux/module.h>
13*4882a593Smuzhiyun #include <linux/of_device.h>
14*4882a593Smuzhiyun #include <linux/platform_device.h>
15*4882a593Smuzhiyun #include <linux/regmap.h>
16*4882a593Smuzhiyun #include <linux/reset.h>
17*4882a593Smuzhiyun #include <linux/phy/phy.h>
18*4882a593Smuzhiyun #include <linux/pm_runtime.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun /* 0x0030 */
21*4882a593Smuzhiyun #define DISABLE_PLL	BIT(3)
22*4882a593Smuzhiyun /* 0x003c */
23*4882a593Smuzhiyun #define PLL_LOCK	BIT(1)
24*4882a593Smuzhiyun /* 0x0084 */
25*4882a593Smuzhiyun #define ENABLE_TX	BIT(7)
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun struct inno_video_phy {
28*4882a593Smuzhiyun 	struct device *dev;
29*4882a593Smuzhiyun 	struct clk *pclk;
30*4882a593Smuzhiyun 	struct regmap *regmap;
31*4882a593Smuzhiyun 	struct reset_control *rst;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun static const struct reg_sequence ttl_mode[] = {
35*4882a593Smuzhiyun 	{ 0x0000, 0x7f },
36*4882a593Smuzhiyun 	{ 0x0004, 0x3f },
37*4882a593Smuzhiyun 	{ 0x0008, 0x80 },
38*4882a593Smuzhiyun 	{ 0x0010, 0x3f },
39*4882a593Smuzhiyun 	{ 0x0014, 0x3f },
40*4882a593Smuzhiyun 	{ 0x0080, 0x44 },
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun 	{ 0x0100, 0x7f },
43*4882a593Smuzhiyun 	{ 0x0104, 0x3f },
44*4882a593Smuzhiyun 	{ 0x0108, 0x80 },
45*4882a593Smuzhiyun 	{ 0x0110, 0x3f },
46*4882a593Smuzhiyun 	{ 0x0114, 0x3f },
47*4882a593Smuzhiyun 	{ 0x0180, 0x44 },
48*4882a593Smuzhiyun };
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun static const struct reg_sequence lvds_mode_single_channel[] = {
51*4882a593Smuzhiyun 	{ 0x0000, 0xbf },
52*4882a593Smuzhiyun 	{ 0x0004, 0x3f },
53*4882a593Smuzhiyun 	{ 0x0008, 0xfe },
54*4882a593Smuzhiyun 	{ 0x0010, 0x00 },
55*4882a593Smuzhiyun 	{ 0x0014, 0x00 },
56*4882a593Smuzhiyun 	{ 0x0080, 0x44 },
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun 	{ 0x0100, 0x00 },
59*4882a593Smuzhiyun 	{ 0x0104, 0x00 },
60*4882a593Smuzhiyun 	{ 0x0108, 0x00 },
61*4882a593Smuzhiyun 	{ 0x0110, 0x00 },
62*4882a593Smuzhiyun 	{ 0x0114, 0x00 },
63*4882a593Smuzhiyun 	{ 0x0180, 0x44 },
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun static const struct reg_sequence lvds_mode_dual_channel[] = {
67*4882a593Smuzhiyun 	{ 0x0000, 0xbf },
68*4882a593Smuzhiyun 	{ 0x0004, 0x3f },
69*4882a593Smuzhiyun 	{ 0x0008, 0xfe },
70*4882a593Smuzhiyun 	{ 0x0010, 0x00 },
71*4882a593Smuzhiyun 	{ 0x0014, 0x00 },
72*4882a593Smuzhiyun 	{ 0x0080, 0x44 },
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun 	{ 0x0100, 0xbf },
75*4882a593Smuzhiyun 	{ 0x0104, 0x3f },
76*4882a593Smuzhiyun 	{ 0x0108, 0xfe },
77*4882a593Smuzhiyun 	{ 0x0110, 0x00 },
78*4882a593Smuzhiyun 	{ 0x0114, 0x00 },
79*4882a593Smuzhiyun 	{ 0x0180, 0x44 },
80*4882a593Smuzhiyun };
81*4882a593Smuzhiyun 
inno_video_phy_power_on(struct phy * phy)82*4882a593Smuzhiyun static int inno_video_phy_power_on(struct phy *phy)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun 	struct inno_video_phy *inno = phy_get_drvdata(phy);
85*4882a593Smuzhiyun 	enum phy_mode mode = phy_get_mode(phy);
86*4882a593Smuzhiyun 	const struct reg_sequence *wseq;
87*4882a593Smuzhiyun 	bool dual_channel = phy_get_bus_width(phy) == 2 ? true : false;
88*4882a593Smuzhiyun 	int nregs;
89*4882a593Smuzhiyun 	u32 status;
90*4882a593Smuzhiyun 	int ret;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	clk_prepare_enable(inno->pclk);
93*4882a593Smuzhiyun 	pm_runtime_get_sync(inno->dev);
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	switch (mode) {
96*4882a593Smuzhiyun 	case PHY_MODE_LVDS:
97*4882a593Smuzhiyun 		if (dual_channel) {
98*4882a593Smuzhiyun 			wseq = lvds_mode_dual_channel;
99*4882a593Smuzhiyun 			nregs = ARRAY_SIZE(lvds_mode_dual_channel);
100*4882a593Smuzhiyun 		} else {
101*4882a593Smuzhiyun 			wseq = lvds_mode_single_channel;
102*4882a593Smuzhiyun 			nregs = ARRAY_SIZE(lvds_mode_single_channel);
103*4882a593Smuzhiyun 		}
104*4882a593Smuzhiyun 		break;
105*4882a593Smuzhiyun 	default:
106*4882a593Smuzhiyun 		wseq = ttl_mode;
107*4882a593Smuzhiyun 		nregs = ARRAY_SIZE(ttl_mode);
108*4882a593Smuzhiyun 		break;
109*4882a593Smuzhiyun 	}
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	regmap_multi_reg_write(inno->regmap, wseq, nregs);
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun 	regmap_update_bits(inno->regmap, 0x0030, DISABLE_PLL, 0);
114*4882a593Smuzhiyun 	ret = regmap_read_poll_timeout(inno->regmap, 0x003c, status,
115*4882a593Smuzhiyun 				       status & PLL_LOCK, 50, 5000);
116*4882a593Smuzhiyun 	if (ret) {
117*4882a593Smuzhiyun 		dev_err(inno->dev, "PLL is not lock\n");
118*4882a593Smuzhiyun 		return ret;
119*4882a593Smuzhiyun 	}
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	regmap_update_bits(inno->regmap, 0x0084, ENABLE_TX, ENABLE_TX);
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	return 0;
124*4882a593Smuzhiyun }
125*4882a593Smuzhiyun 
inno_video_phy_power_off(struct phy * phy)126*4882a593Smuzhiyun static int inno_video_phy_power_off(struct phy *phy)
127*4882a593Smuzhiyun {
128*4882a593Smuzhiyun 	struct inno_video_phy *inno = phy_get_drvdata(phy);
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun 	regmap_update_bits(inno->regmap, 0x0084, ENABLE_TX, 0);
131*4882a593Smuzhiyun 	regmap_update_bits(inno->regmap, 0x0030, DISABLE_PLL, DISABLE_PLL);
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 	pm_runtime_put(inno->dev);
134*4882a593Smuzhiyun 	clk_disable_unprepare(inno->pclk);
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
inno_video_phy_set_mode(struct phy * phy,enum phy_mode mode)139*4882a593Smuzhiyun static int inno_video_phy_set_mode(struct phy *phy, enum phy_mode mode)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	return 0;
142*4882a593Smuzhiyun }
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun static const struct phy_ops inno_video_phy_ops = {
145*4882a593Smuzhiyun 	.set_mode = inno_video_phy_set_mode,
146*4882a593Smuzhiyun 	.power_on = inno_video_phy_power_on,
147*4882a593Smuzhiyun 	.power_off = inno_video_phy_power_off,
148*4882a593Smuzhiyun 	.owner = THIS_MODULE,
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun static const struct regmap_config inno_video_phy_regmap_config = {
152*4882a593Smuzhiyun 	.reg_bits = 32,
153*4882a593Smuzhiyun 	.val_bits = 32,
154*4882a593Smuzhiyun 	.reg_stride = 4,
155*4882a593Smuzhiyun 	.max_register = 0x0180,
156*4882a593Smuzhiyun };
157*4882a593Smuzhiyun 
inno_video_phy_probe(struct platform_device * pdev)158*4882a593Smuzhiyun static int inno_video_phy_probe(struct platform_device *pdev)
159*4882a593Smuzhiyun {
160*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
161*4882a593Smuzhiyun 	struct inno_video_phy *inno;
162*4882a593Smuzhiyun 	struct phy *phy;
163*4882a593Smuzhiyun 	struct phy_provider *phy_provider;
164*4882a593Smuzhiyun 	struct resource *res;
165*4882a593Smuzhiyun 	void __iomem *regs;
166*4882a593Smuzhiyun 	int ret;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
169*4882a593Smuzhiyun 	if (!inno)
170*4882a593Smuzhiyun 		return -ENOMEM;
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	inno->dev = dev;
173*4882a593Smuzhiyun 	platform_set_drvdata(pdev, inno);
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
176*4882a593Smuzhiyun 	regs = devm_ioremap_resource(dev, res);
177*4882a593Smuzhiyun 	if (IS_ERR(regs))
178*4882a593Smuzhiyun 		return PTR_ERR(regs);
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun 	inno->regmap = devm_regmap_init_mmio(dev, regs,
181*4882a593Smuzhiyun 					     &inno_video_phy_regmap_config);
182*4882a593Smuzhiyun 	if (IS_ERR(inno->regmap)) {
183*4882a593Smuzhiyun 		ret = PTR_ERR(inno->regmap);
184*4882a593Smuzhiyun 		dev_err(dev, "failed to init regmap: %d\n", ret);
185*4882a593Smuzhiyun 		return ret;
186*4882a593Smuzhiyun 	}
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun 	inno->pclk = devm_clk_get(dev, "pclk");
189*4882a593Smuzhiyun 	if (IS_ERR(inno->pclk)) {
190*4882a593Smuzhiyun 		dev_err(dev, "failed to get pclk\n");
191*4882a593Smuzhiyun 		return PTR_ERR(inno->pclk);
192*4882a593Smuzhiyun 	}
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun 	inno->rst = devm_reset_control_get(dev, "rst");
195*4882a593Smuzhiyun 	if (IS_ERR(inno->rst)) {
196*4882a593Smuzhiyun 		dev_err(dev, "failed to get reset control\n");
197*4882a593Smuzhiyun 		return PTR_ERR(inno->rst);
198*4882a593Smuzhiyun 	}
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun 	phy = devm_phy_create(dev, NULL, &inno_video_phy_ops);
201*4882a593Smuzhiyun 	if (IS_ERR(phy)) {
202*4882a593Smuzhiyun 		ret = PTR_ERR(phy);
203*4882a593Smuzhiyun 		dev_err(dev, "failed to create PHY: %d\n", ret);
204*4882a593Smuzhiyun 		return ret;
205*4882a593Smuzhiyun 	}
206*4882a593Smuzhiyun 
207*4882a593Smuzhiyun 	phy_set_drvdata(phy, inno);
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
210*4882a593Smuzhiyun 	if (IS_ERR(phy_provider)) {
211*4882a593Smuzhiyun 		dev_err(dev, "failed to register phy provider\n");
212*4882a593Smuzhiyun 		return PTR_ERR(phy_provider);
213*4882a593Smuzhiyun 	}
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	pm_runtime_enable(dev);
216*4882a593Smuzhiyun 
217*4882a593Smuzhiyun 	return 0;
218*4882a593Smuzhiyun }
219*4882a593Smuzhiyun 
inno_video_phy_remove(struct platform_device * pdev)220*4882a593Smuzhiyun static int inno_video_phy_remove(struct platform_device *pdev)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun 	pm_runtime_disable(&pdev->dev);
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun 	return 0;
225*4882a593Smuzhiyun }
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static const struct of_device_id inno_video_phy_of_match[] = {
228*4882a593Smuzhiyun 	{ .compatible = "rockchip,rk3288-video-phy", },
229*4882a593Smuzhiyun 	{}
230*4882a593Smuzhiyun };
231*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, inno_video_phy_of_match);
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun static struct platform_driver inno_video_phy_driver = {
234*4882a593Smuzhiyun 	.driver = {
235*4882a593Smuzhiyun 		.name = "inno-video-phy",
236*4882a593Smuzhiyun 		.of_match_table	= of_match_ptr(inno_video_phy_of_match),
237*4882a593Smuzhiyun 	},
238*4882a593Smuzhiyun 	.probe = inno_video_phy_probe,
239*4882a593Smuzhiyun 	.remove = inno_video_phy_remove,
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun module_platform_driver(inno_video_phy_driver);
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
244*4882a593Smuzhiyun MODULE_DESCRIPTION("Innosilicon LVDS/TTL PHY driver");
245*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
246