1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4 *
5 * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6 */
7
8 #include <linux/kernel.h>
9 #include <linux/clk.h>
10 #include <linux/iopoll.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/phy/phy.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/mfd/syscon.h>
21
22 #define PSEC_PER_SEC 1000000000000LL
23
24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l)))
25
26 /*
27 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
28 * is the first address, the other from the bit4 to bit0 is the second address.
29 * when you configure the registers, you must set both of them. The Clock Lane
30 * and Data Lane use the same registers with the same second address, but the
31 * first address is different.
32 */
33 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5)
34 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0)
35 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \
36 SECOND_ADDRESS(second))
37
38 /* Analog Register Part: reg00 */
39 #define BANDGAP_POWER_MASK BIT(7)
40 #define BANDGAP_POWER_DOWN BIT(7)
41 #define BANDGAP_POWER_ON 0
42 #define LANE_EN_MASK GENMASK(6, 2)
43 #define LANE_EN_CK BIT(6)
44 #define LANE_EN_3 BIT(5)
45 #define LANE_EN_2 BIT(4)
46 #define LANE_EN_1 BIT(3)
47 #define LANE_EN_0 BIT(2)
48 #define POWER_WORK_MASK GENMASK(1, 0)
49 #define POWER_WORK_ENABLE UPDATE(1, 1, 0)
50 #define POWER_WORK_DISABLE UPDATE(2, 1, 0)
51 /* Analog Register Part: reg01 */
52 #define REG_SYNCRST_MASK BIT(2)
53 #define REG_SYNCRST_RESET BIT(2)
54 #define REG_SYNCRST_NORMAL 0
55 #define REG_LDOPD_MASK BIT(1)
56 #define REG_LDOPD_POWER_DOWN BIT(1)
57 #define REG_LDOPD_POWER_ON 0
58 #define REG_PLLPD_MASK BIT(0)
59 #define REG_PLLPD_POWER_DOWN BIT(0)
60 #define REG_PLLPD_POWER_ON 0
61 /* Analog Register Part: reg03 */
62 #define REG_FBDIV_HI_MASK BIT(5)
63 #define REG_FBDIV_HI(x) UPDATE(x, 5, 5)
64 #define REG_PREDIV_MASK GENMASK(4, 0)
65 #define REG_PREDIV(x) UPDATE(x, 4, 0)
66 /* Analog Register Part: reg04 */
67 #define REG_FBDIV_LO_MASK GENMASK(7, 0)
68 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0)
69 /* Analog Register Part: reg05 */
70 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4)
71 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4)
72 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0)
73 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0)
74 /* Analog Register Part: reg06 */
75 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4)
76 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4)
77 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0)
78 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0)
79 /* Analog Register Part: reg07 */
80 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4)
81 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4)
82 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0)
83 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0)
84 /* Analog Register Part: reg08 */
85 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4)
86 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4)
87 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0
88 #define LOWFRE_EN_MASK BIT(5)
89 #define PLL_OUTPUT_FREQUENCY_DIV_BY_1 0
90 #define PLL_OUTPUT_FREQUENCY_DIV_BY_2 1
91 /* Analog Register Part: reg1e */
92 #define PLL_MODE_SEL_MASK GENMASK(6, 5)
93 #define PLL_MODE_SEL_LVDS_MODE 0
94 #define PLL_MODE_SEL_MIPI_MODE BIT(5)
95 /* Digital Register Part: reg00 */
96 #define REG_DIG_RSTN_MASK BIT(0)
97 #define REG_DIG_RSTN_NORMAL BIT(0)
98 #define REG_DIG_RSTN_RESET 0
99 /* Digital Register Part: reg01 */
100 #define INVERT_TXCLKESC_MASK BIT(1)
101 #define INVERT_TXCLKESC_ENABLE BIT(1)
102 #define INVERT_TXCLKESC_DISABLE 0
103 #define INVERT_TXBYTECLKHS_MASK BIT(0)
104 #define INVERT_TXBYTECLKHS_ENABLE BIT(0)
105 #define INVERT_TXBYTECLKHS_DISABLE 0
106 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
107 #define T_LPX_CNT_MASK GENMASK(5, 0)
108 #define T_LPX_CNT(x) UPDATE(x, 5, 0)
109 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
110 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0)
111 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0)
112 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
113 #define T_HS_ZERO_CNT_MASK GENMASK(5, 0)
114 #define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0)
115 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
116 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0)
117 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0)
118 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
119 #define T_HS_EXIT_CNT_MASK GENMASK(4, 0)
120 #define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0)
121 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
122 #define T_CLK_POST_CNT_MASK GENMASK(3, 0)
123 #define T_CLK_POST_CNT(x) UPDATE(x, 3, 0)
124 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
125 #define LPDT_TX_PPI_SYNC_MASK BIT(2)
126 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2)
127 #define LPDT_TX_PPI_SYNC_DISABLE 0
128 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0)
129 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0)
130 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
131 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0)
132 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0)
133 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
134 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0)
135 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0)
136 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
137 #define T_TA_GO_CNT_MASK GENMASK(5, 0)
138 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0)
139 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
140 #define T_TA_SURE_CNT_MASK GENMASK(5, 0)
141 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0)
142 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
143 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0)
144 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0)
145 /* LVDS Register Part: reg00 */
146 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2)
147 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2)
148 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0
149 /* LVDS Register Part: reg01 */
150 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7)
151 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7)
152 #define LVDS_DIGITAL_INTERNAL_DISABLE 0
153 /* LVDS Register Part: reg03 */
154 #define MODE_ENABLE_MASK GENMASK(2, 0)
155 #define TTL_MODE_ENABLE BIT(2)
156 #define LVDS_MODE_ENABLE BIT(1)
157 #define MIPI_MODE_ENABLE BIT(0)
158 /* LVDS Register Part: reg0b */
159 #define LVDS_LANE_EN_MASK GENMASK(7, 3)
160 #define LVDS_DATA_LANE0_EN BIT(7)
161 #define LVDS_DATA_LANE1_EN BIT(6)
162 #define LVDS_DATA_LANE2_EN BIT(5)
163 #define LVDS_DATA_LANE3_EN BIT(4)
164 #define LVDS_CLK_LANE_EN BIT(3)
165 #define LVDS_PLL_POWER_MASK BIT(2)
166 #define LVDS_PLL_POWER_OFF BIT(2)
167 #define LVDS_PLL_POWER_ON 0
168 #define LVDS_BANDGAP_POWER_MASK BIT(0)
169 #define LVDS_BANDGAP_POWER_DOWN BIT(0)
170 #define LVDS_BANDGAP_POWER_ON 0
171
172 #define DSI_PHY_RSTZ 0xa0
173 #define PHY_ENABLECLK BIT(2)
174 #define DSI_PHY_STATUS 0xb0
175 #define PHY_LOCK BIT(0)
176
177 struct mipi_dphy_timing {
178 unsigned int clkmiss;
179 unsigned int clkpost;
180 unsigned int clkpre;
181 unsigned int clkprepare;
182 unsigned int clksettle;
183 unsigned int clktermen;
184 unsigned int clktrail;
185 unsigned int clkzero;
186 unsigned int dtermen;
187 unsigned int eot;
188 unsigned int hsexit;
189 unsigned int hsprepare;
190 unsigned int hszero;
191 unsigned int hssettle;
192 unsigned int hsskip;
193 unsigned int hstrail;
194 unsigned int init;
195 unsigned int lpx;
196 unsigned int taget;
197 unsigned int tago;
198 unsigned int tasure;
199 unsigned int wakeup;
200 };
201
202 struct inno_video_phy {
203 struct device *dev;
204 struct clk *ref_clk;
205 struct clk *pclk_phy;
206 struct clk *pclk_host;
207 void __iomem *phy_base;
208 void __iomem *host_base;
209 struct reset_control *rst;
210
211 struct {
212 struct clk_hw hw;
213 u8 prediv;
214 u16 fbdiv;
215 unsigned long rate;
216 } pll;
217 };
218
219 enum {
220 REGISTER_PART_ANALOG,
221 REGISTER_PART_DIGITAL,
222 REGISTER_PART_CLOCK_LANE,
223 REGISTER_PART_DATA0_LANE,
224 REGISTER_PART_DATA1_LANE,
225 REGISTER_PART_DATA2_LANE,
226 REGISTER_PART_DATA3_LANE,
227 REGISTER_PART_LVDS,
228 };
229
hw_to_inno(struct clk_hw * hw)230 static inline struct inno_video_phy *hw_to_inno(struct clk_hw *hw)
231 {
232 return container_of(hw, struct inno_video_phy, pll.hw);
233 }
234
phy_update_bits(struct inno_video_phy * inno,u8 first,u8 second,u8 mask,u8 val)235 static void phy_update_bits(struct inno_video_phy *inno,
236 u8 first, u8 second, u8 mask, u8 val)
237 {
238 u32 reg = PHY_REG(first, second) << 2;
239 unsigned int tmp, orig;
240
241 orig = readl(inno->phy_base + reg);
242 tmp = orig & ~mask;
243 tmp |= val & mask;
244 writel(tmp, inno->phy_base + reg);
245 }
246
host_update_bits(struct inno_video_phy * inno,u32 reg,u32 mask,u32 val)247 static void host_update_bits(struct inno_video_phy *inno,
248 u32 reg, u32 mask, u32 val)
249 {
250 unsigned int tmp, orig;
251
252 orig = readl(inno->host_base + reg);
253 tmp = orig & ~mask;
254 tmp |= val & mask;
255 writel(tmp, inno->host_base + reg);
256 }
257
mipi_dphy_timing_get_default(struct mipi_dphy_timing * timing,unsigned long period)258 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
259 unsigned long period)
260 {
261 /* Global Operation Timing Parameters */
262 timing->clkmiss = 0;
263 timing->clkpost = 70000 + 52 * period;
264 timing->clkpre = 8 * period;
265 timing->clkprepare = 65000;
266 timing->clksettle = 95000;
267 timing->clktermen = 0;
268 timing->clktrail = 80000;
269 timing->clkzero = 260000;
270 timing->dtermen = 0;
271 timing->eot = 0;
272 timing->hsexit = 120000;
273 timing->hsprepare = 65000 + 4 * period;
274 timing->hszero = 145000 + 6 * period;
275 timing->hssettle = 85000 + 6 * period;
276 timing->hsskip = 40000;
277 timing->hstrail = max(8 * period, 60000 + 4 * period);
278 timing->init = 100000000;
279 timing->lpx = 60000;
280 timing->taget = 5 * timing->lpx;
281 timing->tago = 4 * timing->lpx;
282 timing->tasure = 2 * timing->lpx;
283 timing->wakeup = 1000000000;
284 }
285
inno_video_phy_mipi_mode_enable(struct inno_video_phy * inno)286 static void inno_video_phy_mipi_mode_enable(struct inno_video_phy *inno)
287 {
288 struct mipi_dphy_timing gotp;
289 const struct {
290 unsigned long rate;
291 u8 hs_prepare;
292 u8 clk_lane_hs_zero;
293 u8 data_lane_hs_zero;
294 u8 hs_trail;
295 } timings[] = {
296 { 110000000, 0x20, 0x16, 0x02, 0x22},
297 { 150000000, 0x06, 0x16, 0x03, 0x45},
298 { 200000000, 0x18, 0x17, 0x04, 0x0b},
299 { 250000000, 0x05, 0x17, 0x05, 0x16},
300 { 300000000, 0x51, 0x18, 0x06, 0x2c},
301 { 400000000, 0x64, 0x19, 0x07, 0x33},
302 { 500000000, 0x20, 0x1b, 0x07, 0x4e},
303 { 600000000, 0x6a, 0x1d, 0x08, 0x3a},
304 { 700000000, 0x3e, 0x1e, 0x08, 0x6a},
305 { 800000000, 0x21, 0x1f, 0x09, 0x29},
306 {1000000000, 0x09, 0x20, 0x09, 0x27},
307 };
308 u32 t_txbyteclkhs, t_txclkesc, ui;
309 u32 txbyteclkhs, txclkesc, esc_clk_div;
310 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
311 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
312 unsigned int i;
313
314 /* Select MIPI mode */
315 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
316 MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
317 /* Configure PLL */
318 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
319 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
320 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
321 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv >> 8));
322 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
323 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
324 /* Enable PLL and LDO */
325 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
326 REG_LDOPD_MASK | REG_PLLPD_MASK,
327 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
328 /* Reset analog */
329 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
330 REG_SYNCRST_MASK, REG_SYNCRST_RESET);
331 udelay(1);
332 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
333 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
334 /* Reset digital */
335 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
336 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
337 udelay(1);
338 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
339 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
340
341 txbyteclkhs = inno->pll.rate / 8;
342 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
343
344 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
345 txclkesc = txbyteclkhs / esc_clk_div;
346 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
347
348 ui = div_u64(PSEC_PER_SEC, inno->pll.rate);
349
350 memset(&gotp, 0, sizeof(gotp));
351 mipi_dphy_timing_get_default(&gotp, ui);
352
353 /*
354 * The value of counter for HS Ths-exit
355 * Ths-exit = Tpin_txbyteclkhs * value
356 */
357 hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs);
358 /*
359 * The value of counter for HS Tclk-post
360 * Tclk-post = Tpin_txbyteclkhs * value
361 */
362 clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs);
363 /*
364 * The value of counter for HS Tclk-pre
365 * Tclk-pre = Tpin_txbyteclkhs * value
366 */
367 clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs);
368
369 /*
370 * The value of counter for HS Tlpx Time
371 * Tlpx = Tpin_txbyteclkhs * (2 + value)
372 */
373 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs);
374 if (lpx >= 2)
375 lpx -= 2;
376
377 /*
378 * The value of counter for HS Tta-go
379 * Tta-go for turnaround
380 * Tta-go = Ttxclkesc * value
381 */
382 ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc);
383 /*
384 * The value of counter for HS Tta-sure
385 * Tta-sure for turnaround
386 * Tta-sure = Ttxclkesc * value
387 */
388 ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc);
389 /*
390 * The value of counter for HS Tta-wait
391 * Tta-wait for turnaround
392 * Tta-wait = Ttxclkesc * value
393 */
394 ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc);
395
396 for (i = 0; i < ARRAY_SIZE(timings); i++)
397 if (inno->pll.rate <= timings[i].rate)
398 break;
399
400 if (i == ARRAY_SIZE(timings))
401 --i;
402
403 hs_prepare = timings[i].hs_prepare;
404 hs_trail = timings[i].hs_trail;
405 clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
406 data_lane_hs_zero = timings[i].data_lane_hs_zero;
407 wakeup = 0x3ff;
408
409 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
410 if (i == REGISTER_PART_CLOCK_LANE)
411 hs_zero = clk_lane_hs_zero;
412 else
413 hs_zero = data_lane_hs_zero;
414
415 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
416 T_LPX_CNT(lpx));
417 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
418 T_HS_PREPARE_CNT(hs_prepare));
419 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
420 T_HS_ZERO_CNT(hs_zero));
421 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
422 T_HS_TRAIL_CNT(hs_trail));
423 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
424 T_HS_EXIT_CNT(hs_exit));
425 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
426 T_CLK_POST_CNT(clk_post));
427 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
428 T_CLK_PRE_CNT(clk_pre));
429 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
430 T_WAKEUP_CNT_HI(wakeup >> 8));
431 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
432 T_WAKEUP_CNT_LO(wakeup));
433 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
434 T_TA_GO_CNT(ta_go));
435 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
436 T_TA_SURE_CNT(ta_sure));
437 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
438 T_TA_WAIT_CNT(ta_wait));
439 }
440
441 /* Enable all lanes on analog part */
442 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
443 LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
444 LANE_EN_1 | LANE_EN_0);
445 }
446
inno_video_phy_lvds_mode_enable(struct inno_video_phy * inno)447 static void inno_video_phy_lvds_mode_enable(struct inno_video_phy *inno)
448 {
449 u8 prediv = 2;
450 u16 fbdiv = 28;
451 u32 val;
452 int ret;
453
454 /* Sample clock reverse direction */
455 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
456 SAMPLE_CLOCK_DIRECTION_MASK | LOWFRE_EN_MASK,
457 SAMPLE_CLOCK_DIRECTION_REVERSE |
458 PLL_OUTPUT_FREQUENCY_DIV_BY_1);
459 /* Select LVDS mode */
460 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
461 MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
462 /* Configure PLL */
463 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
464 REG_PREDIV_MASK, REG_PREDIV(prediv));
465 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
466 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv >> 8));
467 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
468 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
469 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
470 /* Enable PLL and Bandgap */
471 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
472 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
473 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
474
475 ret = readl_relaxed_poll_timeout(inno->host_base + DSI_PHY_STATUS,
476 val, val & PHY_LOCK, 50, 10000);
477 if (ret)
478 dev_err(inno->dev, "PLL is not lock\n");
479 /* Select PLL mode */
480 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x1e,
481 PLL_MODE_SEL_MASK, PLL_MODE_SEL_LVDS_MODE);
482
483 /* Reset LVDS digital logic */
484 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
485 LVDS_DIGITAL_INTERNAL_RESET_MASK,
486 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
487 udelay(1);
488 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
489 LVDS_DIGITAL_INTERNAL_RESET_MASK,
490 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
491 /* Enable LVDS digital logic */
492 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
493 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
494 LVDS_DIGITAL_INTERNAL_ENABLE);
495 /* Enable LVDS analog driver */
496 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
497 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
498 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
499 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
500 }
501
inno_video_phy_ttl_mode_enable(struct inno_video_phy * inno)502 static void inno_video_phy_ttl_mode_enable(struct inno_video_phy *inno)
503 {
504 /* Select TTL mode */
505 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
506 MODE_ENABLE_MASK, TTL_MODE_ENABLE);
507 /* Reset digital logic */
508 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
509 LVDS_DIGITAL_INTERNAL_RESET_MASK,
510 LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
511 udelay(1);
512 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
513 LVDS_DIGITAL_INTERNAL_RESET_MASK,
514 LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
515 /* Enable digital logic */
516 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
517 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
518 LVDS_DIGITAL_INTERNAL_ENABLE);
519 /* Enable analog driver */
520 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
521 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
522 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
523 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
524 /* Enable for clk lane in TTL mode */
525 host_update_bits(inno, DSI_PHY_RSTZ, PHY_ENABLECLK, PHY_ENABLECLK);
526 }
527
inno_video_phy_power_on(struct phy * phy)528 static int inno_video_phy_power_on(struct phy *phy)
529 {
530 struct inno_video_phy *inno = phy_get_drvdata(phy);
531 enum phy_mode mode = phy_get_mode(phy);
532
533 clk_prepare_enable(inno->pclk_host);
534 clk_prepare_enable(inno->pclk_phy);
535 pm_runtime_get_sync(inno->dev);
536
537 /* Bandgap power on */
538 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
539 BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
540 /* Enable power work */
541 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
542 POWER_WORK_MASK, POWER_WORK_ENABLE);
543
544 switch (mode) {
545 case PHY_MODE_MIPI_DPHY:
546 inno_video_phy_mipi_mode_enable(inno);
547 break;
548 case PHY_MODE_LVDS:
549 inno_video_phy_lvds_mode_enable(inno);
550 break;
551 default:
552 inno_video_phy_ttl_mode_enable(inno);
553 break;
554 }
555
556 return 0;
557 }
558
inno_video_phy_power_off(struct phy * phy)559 static int inno_video_phy_power_off(struct phy *phy)
560 {
561 struct inno_video_phy *inno = phy_get_drvdata(phy);
562
563 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
564 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
565 REG_LDOPD_MASK | REG_PLLPD_MASK,
566 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
567 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
568 POWER_WORK_MASK, POWER_WORK_DISABLE);
569 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
570 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
571
572 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
573 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
574 LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
575 LVDS_DIGITAL_INTERNAL_DISABLE);
576 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
577 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
578 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
579
580 pm_runtime_put(inno->dev);
581 clk_disable_unprepare(inno->pclk_phy);
582 clk_disable_unprepare(inno->pclk_host);
583
584 return 0;
585 }
586
inno_video_phy_set_mode(struct phy * phy,enum phy_mode mode)587 static int inno_video_phy_set_mode(struct phy *phy, enum phy_mode mode)
588 {
589 return 0;
590 }
591
592 static const struct phy_ops inno_video_phy_ops = {
593 .set_mode = inno_video_phy_set_mode,
594 .power_on = inno_video_phy_power_on,
595 .power_off = inno_video_phy_power_off,
596 .owner = THIS_MODULE,
597 };
598
inno_video_phy_pll_round_rate(struct inno_video_phy * inno,unsigned long prate,unsigned long rate,u8 * prediv,u16 * fbdiv)599 static unsigned long inno_video_phy_pll_round_rate(struct inno_video_phy *inno,
600 unsigned long prate,
601 unsigned long rate,
602 u8 *prediv, u16 *fbdiv)
603 {
604 unsigned long best_freq = 0;
605 unsigned long fref, fout;
606 u8 min_prediv, max_prediv;
607 u8 _prediv, best_prediv = 1;
608 u16 _fbdiv, best_fbdiv = 1;
609 u32 min_delta = UINT_MAX;
610
611 /*
612 * The PLL output frequency can be calculated using a simple formula:
613 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
614 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
615 */
616 fref = prate / 2;
617 if (rate > 1000000000UL)
618 fout = 1000000000UL;
619 else
620 fout = rate;
621
622 /* 5Mhz < Fref / prediv < 40MHz */
623 min_prediv = DIV_ROUND_UP(fref, 40000000);
624 max_prediv = fref / 5000000;
625
626 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
627 u64 tmp;
628 u32 delta;
629
630 tmp = (u64)fout * _prediv;
631 do_div(tmp, fref);
632 _fbdiv = tmp;
633
634 /*
635 * The all possible settings of feedback divider are
636 * 12, 13, 14, 16, ~ 511
637 */
638 if (_fbdiv == 15)
639 continue;
640
641 if (_fbdiv < 12 || _fbdiv > 511)
642 continue;
643
644 tmp = (u64)_fbdiv * fref;
645 do_div(tmp, _prediv);
646
647 delta = abs(fout - tmp);
648 if (!delta) {
649 best_prediv = _prediv;
650 best_fbdiv = _fbdiv;
651 best_freq = tmp;
652 break;
653 } else if (delta < min_delta) {
654 best_prediv = _prediv;
655 best_fbdiv = _fbdiv;
656 best_freq = tmp;
657 min_delta = delta;
658 }
659 }
660
661 if (best_freq) {
662 *prediv = best_prediv;
663 *fbdiv = best_fbdiv;
664 }
665
666 return best_freq;
667 }
668
inno_video_phy_pll_clk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * prate)669 static long inno_video_phy_pll_clk_round_rate(struct clk_hw *hw,
670 unsigned long rate,
671 unsigned long *prate)
672 {
673 struct inno_video_phy *inno = hw_to_inno(hw);
674 unsigned long fin = *prate;
675 unsigned long fout;
676 u16 fbdiv = 1;
677 u8 prediv = 1;
678
679 fout = inno_video_phy_pll_round_rate(inno, fin, rate,
680 &prediv, &fbdiv);
681
682 dev_dbg(inno->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n",
683 *prate, fout, prediv, fbdiv);
684
685 inno->pll.prediv = prediv;
686 inno->pll.fbdiv = fbdiv;
687 inno->pll.rate = fout;
688
689 return fout;
690 }
691
inno_video_phy_pll_clk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)692 static int inno_video_phy_pll_clk_set_rate(struct clk_hw *hw,
693 unsigned long rate,
694 unsigned long parent_rate)
695 {
696 struct inno_video_phy *inno = hw_to_inno(hw);
697
698 inno->pll.rate = rate;
699
700 return 0;
701 }
702
703 static unsigned long
inno_video_phy_pll_clk_recalc_rate(struct clk_hw * hw,unsigned long prate)704 inno_video_phy_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long prate)
705 {
706 struct inno_video_phy *inno = hw_to_inno(hw);
707
708 return inno->pll.rate;
709 }
710
711 static const struct clk_ops inno_video_phy_pll_clk_ops = {
712 .round_rate = inno_video_phy_pll_clk_round_rate,
713 .set_rate = inno_video_phy_pll_clk_set_rate,
714 .recalc_rate = inno_video_phy_pll_clk_recalc_rate,
715 };
716
inno_video_phy_pll_register(struct inno_video_phy * inno)717 static int inno_video_phy_pll_register(struct inno_video_phy *inno)
718 {
719 struct device *dev = inno->dev;
720 struct clk *clk;
721 const char *parent_name;
722 struct clk_init_data init = {};
723 int ret;
724 static int phy_pll_num;
725 char pll_name[20] = "video_phy_pll_";
726
727 parent_name = __clk_get_name(inno->ref_clk);
728
729 strcat(pll_name, phy_pll_num++ ? "1" : "0");
730 init.name = pll_name;
731 init.ops = &inno_video_phy_pll_clk_ops;
732 init.parent_names = &parent_name;
733 init.num_parents = 1;
734 init.flags = 0;
735
736 inno->pll.hw.init = &init;
737 clk = devm_clk_register(dev, &inno->pll.hw);
738 if (IS_ERR(clk)) {
739 ret = PTR_ERR(clk);
740 dev_err(dev, "failed to register PLL: %d\n", ret);
741 return ret;
742 }
743
744 return of_clk_add_provider(dev->of_node, of_clk_src_simple_get, clk);
745 }
746
inno_video_phy_pll_unregister(struct inno_video_phy * inno)747 static void inno_video_phy_pll_unregister(struct inno_video_phy *inno)
748 {
749 struct device *dev = inno->dev;
750
751 of_clk_del_provider(dev->of_node);
752 }
753
inno_video_phy_probe(struct platform_device * pdev)754 static int inno_video_phy_probe(struct platform_device *pdev)
755 {
756 struct device *dev = &pdev->dev;
757 struct inno_video_phy *inno;
758 struct phy_provider *phy_provider;
759 struct phy *phy;
760 struct resource *res;
761 int ret;
762
763 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
764 if (!inno)
765 return -ENOMEM;
766
767 inno->dev = dev;
768 platform_set_drvdata(pdev, inno);
769
770 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
771 if (!res) {
772 dev_err(dev, "invalid phy resource\n");
773 return -EINVAL;
774 }
775
776 inno->phy_base = devm_ioremap(dev, res->start, resource_size(res));
777 if (!inno->phy_base)
778 return -ENOMEM;
779
780 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
781 if (!res) {
782 dev_err(dev, "invalid host resource\n");
783 return -EINVAL;
784 }
785
786 inno->host_base = devm_ioremap(dev, res->start, resource_size(res));
787 if (!inno->host_base)
788 return -ENOMEM;
789
790 inno->ref_clk = devm_clk_get(dev, "ref");
791 if (IS_ERR(inno->ref_clk)) {
792 ret = PTR_ERR(inno->ref_clk);
793 dev_err(dev, "failed to get ref clock: %d\n", ret);
794 return ret;
795 }
796
797 inno->pclk_phy = devm_clk_get(dev, "pclk_phy");
798 if (IS_ERR(inno->pclk_phy)) {
799 ret = PTR_ERR(inno->pclk_phy);
800 dev_err(dev, "failed to get phy pclk: %d\n", ret);
801 return ret;
802 }
803
804 inno->pclk_host = devm_clk_get(dev, "pclk_host");
805 if (IS_ERR(inno->pclk_host)) {
806 ret = PTR_ERR(inno->pclk_host);
807 dev_err(dev, "failed to get host pclk: %d\n", ret);
808 return ret;
809 }
810
811 inno->rst = devm_reset_control_get(dev, "rst");
812 if (IS_ERR(inno->rst)) {
813 ret = PTR_ERR(inno->rst);
814 dev_err(dev, "failed to get system reset control: %d\n", ret);
815 return ret;
816 }
817
818 phy = devm_phy_create(dev, NULL, &inno_video_phy_ops);
819 if (IS_ERR(phy)) {
820 ret = PTR_ERR(phy);
821 dev_err(dev, "failed to create phy: %d\n", ret);
822 return ret;
823 }
824
825 phy_set_drvdata(phy, inno);
826
827 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
828 if (IS_ERR(phy_provider)) {
829 ret = PTR_ERR(phy_provider);
830 dev_err(dev, "failed to register phy provider: %d\n", ret);
831 return ret;
832 }
833
834 ret = inno_video_phy_pll_register(inno);
835 if (ret)
836 return ret;
837
838 pm_runtime_enable(dev);
839
840 return 0;
841 }
842
inno_video_phy_remove(struct platform_device * pdev)843 static int inno_video_phy_remove(struct platform_device *pdev)
844 {
845 struct inno_video_phy *inno = platform_get_drvdata(pdev);
846
847 pm_runtime_disable(inno->dev);
848 inno_video_phy_pll_unregister(inno);
849
850 return 0;
851 }
852
853 static const struct of_device_id inno_video_phy_of_match[] = {
854 { .compatible = "rockchip,px30-video-phy", },
855 { .compatible = "rockchip,rk3128-video-phy", },
856 { .compatible = "rockchip,rk3368-video-phy", },
857 { .compatible = "rockchip,rk3568-video-phy", },
858 {}
859 };
860 MODULE_DEVICE_TABLE(of, inno_video_phy_of_match);
861
862 static struct platform_driver inno_video_phy_driver = {
863 .driver = {
864 .name = "inno-video-combo-phy",
865 .of_match_table = of_match_ptr(inno_video_phy_of_match),
866 },
867 .probe = inno_video_phy_probe,
868 .remove = inno_video_phy_remove,
869 };
870 module_platform_driver(inno_video_phy_driver);
871
872 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
873 MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver");
874 MODULE_LICENSE("GPL v2");
875