1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Rockchip MIPI CSI2 DPHY driver 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2020 Rockchip Electronics Co., Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_ 9*4882a593Smuzhiyun #define _PHY_ROCKCHIP_CSI2_DPHY_COMMON_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/rk-camera-module.h> 12*4882a593Smuzhiyun #include <linux/rkcif-config.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define PHY_MAX 16 15*4882a593Smuzhiyun #define MAX_DEV_NAME_LEN 32 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define MAX_SAMSUNG_PHY_NUM 2 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define MAX_INNO_PHY_NUM 2 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* add new chip id in tail by time order */ 22*4882a593Smuzhiyun enum csi2_dphy_chip_id { 23*4882a593Smuzhiyun CHIP_ID_RK3568 = 0x0, 24*4882a593Smuzhiyun CHIP_ID_RK3588 = 0x1, 25*4882a593Smuzhiyun CHIP_ID_RK3588_DCPHY = 0x2, 26*4882a593Smuzhiyun CHIP_ID_RV1106 = 0x3, 27*4882a593Smuzhiyun CHIP_ID_RK3562 = 0x4, 28*4882a593Smuzhiyun }; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun enum csi2_dphy_rx_pads { 31*4882a593Smuzhiyun CSI2_DPHY_RX_PAD_SINK = 0, 32*4882a593Smuzhiyun CSI2_DPHY_RX_PAD_SOURCE, 33*4882a593Smuzhiyun CSI2_DPHY_RX_PADS_NUM, 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun enum csi2_dphy_lane_mode { 37*4882a593Smuzhiyun LANE_MODE_UNDEF = 0x0, 38*4882a593Smuzhiyun LANE_MODE_FULL, 39*4882a593Smuzhiyun LANE_MODE_SPLIT, 40*4882a593Smuzhiyun }; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct grf_reg { 43*4882a593Smuzhiyun u32 offset; 44*4882a593Smuzhiyun u32 mask; 45*4882a593Smuzhiyun u32 shift; 46*4882a593Smuzhiyun }; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun struct csi2dphy_reg { 49*4882a593Smuzhiyun u32 offset; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define MAX_DPHY_SENSORS (2) 53*4882a593Smuzhiyun #define MAX_NUM_CSI2_DPHY (0x2) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun struct csi2_sensor { 56*4882a593Smuzhiyun struct v4l2_subdev *sd; 57*4882a593Smuzhiyun struct v4l2_mbus_config mbus; 58*4882a593Smuzhiyun struct v4l2_mbus_framefmt format; 59*4882a593Smuzhiyun int lanes; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct csi2_dphy_hw; 63*4882a593Smuzhiyun struct samsung_mipi_dcphy; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct dphy_drv_data { 66*4882a593Smuzhiyun const char dev_name[MAX_DEV_NAME_LEN]; 67*4882a593Smuzhiyun enum csi2_dphy_chip_id chip_id; 68*4882a593Smuzhiyun char num_inno_phy; 69*4882a593Smuzhiyun char num_samsung_phy; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct csi2_dphy { 73*4882a593Smuzhiyun struct device *dev; 74*4882a593Smuzhiyun struct list_head list; 75*4882a593Smuzhiyun struct csi2_dphy_hw *dphy_hw; 76*4882a593Smuzhiyun struct csi2_dphy_hw *dphy_hw_group[MAX_INNO_PHY_NUM]; 77*4882a593Smuzhiyun struct samsung_mipi_dcphy *samsung_phy; 78*4882a593Smuzhiyun struct samsung_mipi_dcphy *samsung_phy_group[MAX_SAMSUNG_PHY_NUM]; 79*4882a593Smuzhiyun struct v4l2_async_notifier notifier; 80*4882a593Smuzhiyun struct v4l2_subdev sd; 81*4882a593Smuzhiyun struct mutex mutex; /* lock for updating protection */ 82*4882a593Smuzhiyun struct media_pad pads[CSI2_DPHY_RX_PADS_NUM]; 83*4882a593Smuzhiyun struct csi2_sensor sensors[MAX_DPHY_SENSORS]; 84*4882a593Smuzhiyun u64 data_rate_mbps; 85*4882a593Smuzhiyun int num_sensors; 86*4882a593Smuzhiyun int phy_index; 87*4882a593Smuzhiyun struct rkcif_csi_info csi_info; 88*4882a593Smuzhiyun void *phy_hw[RKMODULE_MULTI_DEV_NUM]; 89*4882a593Smuzhiyun bool is_streaming; 90*4882a593Smuzhiyun int lane_mode; 91*4882a593Smuzhiyun const struct dphy_drv_data *drv_data; 92*4882a593Smuzhiyun struct rkmodule_csi_dphy_param dphy_param; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct dphy_hw_drv_data { 96*4882a593Smuzhiyun const struct hsfreq_range *hsfreq_ranges; 97*4882a593Smuzhiyun int num_hsfreq_ranges; 98*4882a593Smuzhiyun const struct hsfreq_range *hsfreq_ranges_cphy; 99*4882a593Smuzhiyun int num_hsfreq_ranges_cphy; 100*4882a593Smuzhiyun const struct grf_reg *grf_regs; 101*4882a593Smuzhiyun const struct txrx_reg *txrx_regs; 102*4882a593Smuzhiyun const struct csi2dphy_reg *csi2dphy_regs; 103*4882a593Smuzhiyun void (*individual_init)(struct csi2_dphy_hw *hw); 104*4882a593Smuzhiyun int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 105*4882a593Smuzhiyun int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 106*4882a593Smuzhiyun enum csi2_dphy_chip_id chip_id; 107*4882a593Smuzhiyun }; 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun struct csi2_dphy_hw { 110*4882a593Smuzhiyun struct device *dev; 111*4882a593Smuzhiyun struct regmap *regmap_grf; 112*4882a593Smuzhiyun struct regmap *regmap_sys_grf; 113*4882a593Smuzhiyun const struct grf_reg *grf_regs; 114*4882a593Smuzhiyun const struct txrx_reg *txrx_regs; 115*4882a593Smuzhiyun const struct csi2dphy_reg *csi2dphy_regs; 116*4882a593Smuzhiyun const struct dphy_hw_drv_data *drv_data; 117*4882a593Smuzhiyun void __iomem *hw_base_addr; 118*4882a593Smuzhiyun struct clk_bulk_data *clks_bulk; 119*4882a593Smuzhiyun struct reset_control *rsts_bulk; 120*4882a593Smuzhiyun struct csi2_dphy *dphy_dev[MAX_NUM_CSI2_DPHY]; 121*4882a593Smuzhiyun struct v4l2_subdev sd; 122*4882a593Smuzhiyun struct mutex mutex; /* lock for updating protection */ 123*4882a593Smuzhiyun atomic_t stream_cnt; 124*4882a593Smuzhiyun int num_clks; 125*4882a593Smuzhiyun int num_sensors; 126*4882a593Smuzhiyun int dphy_dev_num; 127*4882a593Smuzhiyun enum csi2_dphy_lane_mode lane_mode; 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun int (*stream_on)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 130*4882a593Smuzhiyun int (*stream_off)(struct csi2_dphy *dphy, struct v4l2_subdev *sd); 131*4882a593Smuzhiyun int (*ttl_mode_enable)(struct csi2_dphy_hw *hw); 132*4882a593Smuzhiyun void (*ttl_mode_disable)(struct csi2_dphy_hw *hw); 133*4882a593Smuzhiyun }; 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun int rockchip_csi2_dphy_hw_init(void); 136*4882a593Smuzhiyun int rockchip_csi2_dphy_init(void); 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #endif 139