1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2017 John Crispin <john@phrozen.org>
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Based on code from
6*4882a593Smuzhiyun * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/err.h>
11*4882a593Smuzhiyun #include <linux/io.h>
12*4882a593Smuzhiyun #include <linux/kernel.h>
13*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
14*4882a593Smuzhiyun #include <linux/module.h>
15*4882a593Smuzhiyun #include <linux/mutex.h>
16*4882a593Smuzhiyun #include <linux/of_platform.h>
17*4882a593Smuzhiyun #include <linux/phy/phy.h>
18*4882a593Smuzhiyun #include <linux/platform_device.h>
19*4882a593Smuzhiyun #include <linux/regmap.h>
20*4882a593Smuzhiyun #include <linux/reset.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define RT_SYSC_REG_SYSCFG1 0x014
23*4882a593Smuzhiyun #define RT_SYSC_REG_CLKCFG1 0x030
24*4882a593Smuzhiyun #define RT_SYSC_REG_USB_PHY_CFG 0x05c
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun #define OFS_U2_PHY_AC0 0x800
27*4882a593Smuzhiyun #define OFS_U2_PHY_AC1 0x804
28*4882a593Smuzhiyun #define OFS_U2_PHY_AC2 0x808
29*4882a593Smuzhiyun #define OFS_U2_PHY_ACR0 0x810
30*4882a593Smuzhiyun #define OFS_U2_PHY_ACR1 0x814
31*4882a593Smuzhiyun #define OFS_U2_PHY_ACR2 0x818
32*4882a593Smuzhiyun #define OFS_U2_PHY_ACR3 0x81C
33*4882a593Smuzhiyun #define OFS_U2_PHY_ACR4 0x820
34*4882a593Smuzhiyun #define OFS_U2_PHY_AMON0 0x824
35*4882a593Smuzhiyun #define OFS_U2_PHY_DCR0 0x860
36*4882a593Smuzhiyun #define OFS_U2_PHY_DCR1 0x864
37*4882a593Smuzhiyun #define OFS_U2_PHY_DTM0 0x868
38*4882a593Smuzhiyun #define OFS_U2_PHY_DTM1 0x86C
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define RT_RSTCTRL_UDEV BIT(25)
41*4882a593Smuzhiyun #define RT_RSTCTRL_UHST BIT(22)
42*4882a593Smuzhiyun #define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun #define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
45*4882a593Smuzhiyun #define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
46*4882a593Smuzhiyun #define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
47*4882a593Smuzhiyun #define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun #define USB_PHY_UTMI_8B60M BIT(1)
50*4882a593Smuzhiyun #define UDEV_WAKEUP BIT(0)
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun struct ralink_usb_phy {
53*4882a593Smuzhiyun struct reset_control *rstdev;
54*4882a593Smuzhiyun struct reset_control *rsthost;
55*4882a593Smuzhiyun u32 clk;
56*4882a593Smuzhiyun struct phy *phy;
57*4882a593Smuzhiyun void __iomem *base;
58*4882a593Smuzhiyun struct regmap *sysctl;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun
u2_phy_w32(struct ralink_usb_phy * phy,u32 val,u32 reg)61*4882a593Smuzhiyun static void u2_phy_w32(struct ralink_usb_phy *phy, u32 val, u32 reg)
62*4882a593Smuzhiyun {
63*4882a593Smuzhiyun writel(val, phy->base + reg);
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
u2_phy_r32(struct ralink_usb_phy * phy,u32 reg)66*4882a593Smuzhiyun static u32 u2_phy_r32(struct ralink_usb_phy *phy, u32 reg)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun return readl(phy->base + reg);
69*4882a593Smuzhiyun }
70*4882a593Smuzhiyun
ralink_usb_phy_init(struct ralink_usb_phy * phy)71*4882a593Smuzhiyun static void ralink_usb_phy_init(struct ralink_usb_phy *phy)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun u2_phy_r32(phy, OFS_U2_PHY_AC2);
74*4882a593Smuzhiyun u2_phy_r32(phy, OFS_U2_PHY_ACR0);
75*4882a593Smuzhiyun u2_phy_r32(phy, OFS_U2_PHY_DCR0);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
78*4882a593Smuzhiyun u2_phy_r32(phy, OFS_U2_PHY_DCR0);
79*4882a593Smuzhiyun u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
80*4882a593Smuzhiyun u2_phy_r32(phy, OFS_U2_PHY_DCR0);
81*4882a593Smuzhiyun u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
82*4882a593Smuzhiyun u2_phy_r32(phy, OFS_U2_PHY_DCR0);
83*4882a593Smuzhiyun u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
84*4882a593Smuzhiyun u2_phy_r32(phy, OFS_U2_PHY_DCR0);
85*4882a593Smuzhiyun u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
86*4882a593Smuzhiyun u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
87*4882a593Smuzhiyun u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
88*4882a593Smuzhiyun u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
89*4882a593Smuzhiyun }
90*4882a593Smuzhiyun
ralink_usb_phy_power_on(struct phy * _phy)91*4882a593Smuzhiyun static int ralink_usb_phy_power_on(struct phy *_phy)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
94*4882a593Smuzhiyun u32 t;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* enable the phy */
97*4882a593Smuzhiyun regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
98*4882a593Smuzhiyun phy->clk, phy->clk);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* setup host mode */
101*4882a593Smuzhiyun regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1,
102*4882a593Smuzhiyun RT_SYSCFG1_USB0_HOST_MODE,
103*4882a593Smuzhiyun RT_SYSCFG1_USB0_HOST_MODE);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /* deassert the reset lines */
106*4882a593Smuzhiyun reset_control_deassert(phy->rsthost);
107*4882a593Smuzhiyun reset_control_deassert(phy->rstdev);
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun /*
110*4882a593Smuzhiyun * The SDK kernel had a delay of 100ms. however on device
111*4882a593Smuzhiyun * testing showed that 10ms is enough
112*4882a593Smuzhiyun */
113*4882a593Smuzhiyun mdelay(10);
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun if (phy->base)
116*4882a593Smuzhiyun ralink_usb_phy_init(phy);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun /* print some status info */
119*4882a593Smuzhiyun regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t);
120*4882a593Smuzhiyun dev_info(&phy->phy->dev, "remote usb device wakeup %s\n",
121*4882a593Smuzhiyun (t & UDEV_WAKEUP) ? ("enabled") : ("disabled"));
122*4882a593Smuzhiyun if (t & USB_PHY_UTMI_8B60M)
123*4882a593Smuzhiyun dev_info(&phy->phy->dev, "UTMI 8bit 60MHz\n");
124*4882a593Smuzhiyun else
125*4882a593Smuzhiyun dev_info(&phy->phy->dev, "UTMI 16bit 30MHz\n");
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
ralink_usb_phy_power_off(struct phy * _phy)130*4882a593Smuzhiyun static int ralink_usb_phy_power_off(struct phy *_phy)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct ralink_usb_phy *phy = phy_get_drvdata(_phy);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun /* disable the phy */
135*4882a593Smuzhiyun regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
136*4882a593Smuzhiyun phy->clk, 0);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun /* assert the reset lines */
139*4882a593Smuzhiyun reset_control_assert(phy->rstdev);
140*4882a593Smuzhiyun reset_control_assert(phy->rsthost);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static const struct phy_ops ralink_usb_phy_ops = {
146*4882a593Smuzhiyun .power_on = ralink_usb_phy_power_on,
147*4882a593Smuzhiyun .power_off = ralink_usb_phy_power_off,
148*4882a593Smuzhiyun .owner = THIS_MODULE,
149*4882a593Smuzhiyun };
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun static const struct of_device_id ralink_usb_phy_of_match[] = {
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun .compatible = "ralink,rt3352-usbphy",
154*4882a593Smuzhiyun .data = (void *)(uintptr_t)(RT_CLKCFG1_UPHY1_CLK_EN |
155*4882a593Smuzhiyun RT_CLKCFG1_UPHY0_CLK_EN)
156*4882a593Smuzhiyun },
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun .compatible = "mediatek,mt7620-usbphy",
159*4882a593Smuzhiyun .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
160*4882a593Smuzhiyun MT7620_CLKCFG1_UPHY0_CLK_EN)
161*4882a593Smuzhiyun },
162*4882a593Smuzhiyun {
163*4882a593Smuzhiyun .compatible = "mediatek,mt7628-usbphy",
164*4882a593Smuzhiyun .data = (void *)(uintptr_t)(MT7620_CLKCFG1_UPHY1_CLK_EN |
165*4882a593Smuzhiyun MT7620_CLKCFG1_UPHY0_CLK_EN) },
166*4882a593Smuzhiyun { },
167*4882a593Smuzhiyun };
168*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ralink_usb_phy_of_match);
169*4882a593Smuzhiyun
ralink_usb_phy_probe(struct platform_device * pdev)170*4882a593Smuzhiyun static int ralink_usb_phy_probe(struct platform_device *pdev)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun struct device *dev = &pdev->dev;
173*4882a593Smuzhiyun struct resource *res;
174*4882a593Smuzhiyun struct phy_provider *phy_provider;
175*4882a593Smuzhiyun const struct of_device_id *match;
176*4882a593Smuzhiyun struct ralink_usb_phy *phy;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun match = of_match_device(ralink_usb_phy_of_match, &pdev->dev);
179*4882a593Smuzhiyun if (!match)
180*4882a593Smuzhiyun return -ENODEV;
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
183*4882a593Smuzhiyun if (!phy)
184*4882a593Smuzhiyun return -ENOMEM;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun phy->clk = (uintptr_t)match->data;
187*4882a593Smuzhiyun phy->base = NULL;
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun phy->sysctl = syscon_regmap_lookup_by_phandle(dev->of_node, "ralink,sysctl");
190*4882a593Smuzhiyun if (IS_ERR(phy->sysctl)) {
191*4882a593Smuzhiyun dev_err(dev, "failed to get sysctl registers\n");
192*4882a593Smuzhiyun return PTR_ERR(phy->sysctl);
193*4882a593Smuzhiyun }
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun /* The MT7628 and MT7688 require extra setup of PHY registers. */
196*4882a593Smuzhiyun if (of_device_is_compatible(dev->of_node, "mediatek,mt7628-usbphy")) {
197*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
198*4882a593Smuzhiyun phy->base = devm_ioremap_resource(&pdev->dev, res);
199*4882a593Smuzhiyun if (IS_ERR(phy->base)) {
200*4882a593Smuzhiyun dev_err(dev, "failed to remap register memory\n");
201*4882a593Smuzhiyun return PTR_ERR(phy->base);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun }
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun phy->rsthost = devm_reset_control_get(&pdev->dev, "host");
206*4882a593Smuzhiyun if (IS_ERR(phy->rsthost)) {
207*4882a593Smuzhiyun dev_err(dev, "host reset is missing\n");
208*4882a593Smuzhiyun return PTR_ERR(phy->rsthost);
209*4882a593Smuzhiyun }
210*4882a593Smuzhiyun
211*4882a593Smuzhiyun phy->rstdev = devm_reset_control_get(&pdev->dev, "device");
212*4882a593Smuzhiyun if (IS_ERR(phy->rstdev)) {
213*4882a593Smuzhiyun dev_err(dev, "device reset is missing\n");
214*4882a593Smuzhiyun return PTR_ERR(phy->rstdev);
215*4882a593Smuzhiyun }
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun phy->phy = devm_phy_create(dev, NULL, &ralink_usb_phy_ops);
218*4882a593Smuzhiyun if (IS_ERR(phy->phy)) {
219*4882a593Smuzhiyun dev_err(dev, "failed to create PHY\n");
220*4882a593Smuzhiyun return PTR_ERR(phy->phy);
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun phy_set_drvdata(phy->phy, phy);
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(phy_provider);
227*4882a593Smuzhiyun }
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun static struct platform_driver ralink_usb_phy_driver = {
230*4882a593Smuzhiyun .probe = ralink_usb_phy_probe,
231*4882a593Smuzhiyun .driver = {
232*4882a593Smuzhiyun .of_match_table = ralink_usb_phy_of_match,
233*4882a593Smuzhiyun .name = "ralink-usb-phy",
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun };
236*4882a593Smuzhiyun module_platform_driver(ralink_usb_phy_driver);
237*4882a593Smuzhiyun
238*4882a593Smuzhiyun MODULE_DESCRIPTION("Ralink USB phy driver");
239*4882a593Smuzhiyun MODULE_AUTHOR("John Crispin <john@phrozen.org>");
240*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
241