1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * phy-mvebu-sata.c: SATA Phy driver for the Marvell mvebu SoCs.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2013 Andrew Lunn <andrew@lunn.ch>
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/kernel.h>
9*4882a593Smuzhiyun #include <linux/init.h>
10*4882a593Smuzhiyun #include <linux/clk.h>
11*4882a593Smuzhiyun #include <linux/phy/phy.h>
12*4882a593Smuzhiyun #include <linux/io.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun struct priv {
16*4882a593Smuzhiyun struct clk *clk;
17*4882a593Smuzhiyun void __iomem *base;
18*4882a593Smuzhiyun };
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #define SATA_PHY_MODE_2 0x0330
21*4882a593Smuzhiyun #define MODE_2_FORCE_PU_TX BIT(0)
22*4882a593Smuzhiyun #define MODE_2_FORCE_PU_RX BIT(1)
23*4882a593Smuzhiyun #define MODE_2_PU_PLL BIT(2)
24*4882a593Smuzhiyun #define MODE_2_PU_IVREF BIT(3)
25*4882a593Smuzhiyun #define SATA_IF_CTRL 0x0050
26*4882a593Smuzhiyun #define CTRL_PHY_SHUTDOWN BIT(9)
27*4882a593Smuzhiyun
phy_mvebu_sata_power_on(struct phy * phy)28*4882a593Smuzhiyun static int phy_mvebu_sata_power_on(struct phy *phy)
29*4882a593Smuzhiyun {
30*4882a593Smuzhiyun struct priv *priv = phy_get_drvdata(phy);
31*4882a593Smuzhiyun u32 reg;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun clk_prepare_enable(priv->clk);
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun /* Enable PLL and IVREF */
36*4882a593Smuzhiyun reg = readl(priv->base + SATA_PHY_MODE_2);
37*4882a593Smuzhiyun reg |= (MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
38*4882a593Smuzhiyun MODE_2_PU_PLL | MODE_2_PU_IVREF);
39*4882a593Smuzhiyun writel(reg , priv->base + SATA_PHY_MODE_2);
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* Enable PHY */
42*4882a593Smuzhiyun reg = readl(priv->base + SATA_IF_CTRL);
43*4882a593Smuzhiyun reg &= ~CTRL_PHY_SHUTDOWN;
44*4882a593Smuzhiyun writel(reg, priv->base + SATA_IF_CTRL);
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun clk_disable_unprepare(priv->clk);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun return 0;
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
phy_mvebu_sata_power_off(struct phy * phy)51*4882a593Smuzhiyun static int phy_mvebu_sata_power_off(struct phy *phy)
52*4882a593Smuzhiyun {
53*4882a593Smuzhiyun struct priv *priv = phy_get_drvdata(phy);
54*4882a593Smuzhiyun u32 reg;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun clk_prepare_enable(priv->clk);
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /* Disable PLL and IVREF */
59*4882a593Smuzhiyun reg = readl(priv->base + SATA_PHY_MODE_2);
60*4882a593Smuzhiyun reg &= ~(MODE_2_FORCE_PU_TX | MODE_2_FORCE_PU_RX |
61*4882a593Smuzhiyun MODE_2_PU_PLL | MODE_2_PU_IVREF);
62*4882a593Smuzhiyun writel(reg, priv->base + SATA_PHY_MODE_2);
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /* Disable PHY */
65*4882a593Smuzhiyun reg = readl(priv->base + SATA_IF_CTRL);
66*4882a593Smuzhiyun reg |= CTRL_PHY_SHUTDOWN;
67*4882a593Smuzhiyun writel(reg, priv->base + SATA_IF_CTRL);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun clk_disable_unprepare(priv->clk);
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun return 0;
72*4882a593Smuzhiyun }
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun static const struct phy_ops phy_mvebu_sata_ops = {
75*4882a593Smuzhiyun .power_on = phy_mvebu_sata_power_on,
76*4882a593Smuzhiyun .power_off = phy_mvebu_sata_power_off,
77*4882a593Smuzhiyun .owner = THIS_MODULE,
78*4882a593Smuzhiyun };
79*4882a593Smuzhiyun
phy_mvebu_sata_probe(struct platform_device * pdev)80*4882a593Smuzhiyun static int phy_mvebu_sata_probe(struct platform_device *pdev)
81*4882a593Smuzhiyun {
82*4882a593Smuzhiyun struct phy_provider *phy_provider;
83*4882a593Smuzhiyun struct resource *res;
84*4882a593Smuzhiyun struct priv *priv;
85*4882a593Smuzhiyun struct phy *phy;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
88*4882a593Smuzhiyun if (!priv)
89*4882a593Smuzhiyun return -ENOMEM;
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
92*4882a593Smuzhiyun priv->base = devm_ioremap_resource(&pdev->dev, res);
93*4882a593Smuzhiyun if (IS_ERR(priv->base))
94*4882a593Smuzhiyun return PTR_ERR(priv->base);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun priv->clk = devm_clk_get(&pdev->dev, "sata");
97*4882a593Smuzhiyun if (IS_ERR(priv->clk))
98*4882a593Smuzhiyun return PTR_ERR(priv->clk);
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun phy = devm_phy_create(&pdev->dev, NULL, &phy_mvebu_sata_ops);
101*4882a593Smuzhiyun if (IS_ERR(phy))
102*4882a593Smuzhiyun return PTR_ERR(phy);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun phy_set_drvdata(phy, priv);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun phy_provider = devm_of_phy_provider_register(&pdev->dev,
107*4882a593Smuzhiyun of_phy_simple_xlate);
108*4882a593Smuzhiyun if (IS_ERR(phy_provider))
109*4882a593Smuzhiyun return PTR_ERR(phy_provider);
110*4882a593Smuzhiyun
111*4882a593Smuzhiyun /* The boot loader may of left it on. Turn it off. */
112*4882a593Smuzhiyun phy_mvebu_sata_power_off(phy);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static const struct of_device_id phy_mvebu_sata_of_match[] = {
118*4882a593Smuzhiyun { .compatible = "marvell,mvebu-sata-phy" },
119*4882a593Smuzhiyun { },
120*4882a593Smuzhiyun };
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun static struct platform_driver phy_mvebu_sata_driver = {
123*4882a593Smuzhiyun .probe = phy_mvebu_sata_probe,
124*4882a593Smuzhiyun .driver = {
125*4882a593Smuzhiyun .name = "phy-mvebu-sata",
126*4882a593Smuzhiyun .of_match_table = phy_mvebu_sata_of_match,
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun };
129*4882a593Smuzhiyun builtin_platform_driver(phy_mvebu_sata_driver);
130