1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2014 Marvell Technology Group Ltd.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Antoine Tenart <antoine.tenart@free-electrons.com>
6*4882a593Smuzhiyun * Jisheng Zhang <jszhang@marvell.com>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/io.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_device.h>
12*4882a593Smuzhiyun #include <linux/phy/phy.h>
13*4882a593Smuzhiyun #include <linux/platform_device.h>
14*4882a593Smuzhiyun #include <linux/reset.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define USB_PHY_PLL 0x04
17*4882a593Smuzhiyun #define USB_PHY_PLL_CONTROL 0x08
18*4882a593Smuzhiyun #define USB_PHY_TX_CTRL0 0x10
19*4882a593Smuzhiyun #define USB_PHY_TX_CTRL1 0x14
20*4882a593Smuzhiyun #define USB_PHY_TX_CTRL2 0x18
21*4882a593Smuzhiyun #define USB_PHY_RX_CTRL 0x20
22*4882a593Smuzhiyun #define USB_PHY_ANALOG 0x34
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /* USB_PHY_PLL */
25*4882a593Smuzhiyun #define CLK_REF_DIV(x) ((x) << 4)
26*4882a593Smuzhiyun #define FEEDBACK_CLK_DIV(x) ((x) << 8)
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun /* USB_PHY_PLL_CONTROL */
29*4882a593Smuzhiyun #define CLK_STABLE BIT(0)
30*4882a593Smuzhiyun #define PLL_CTRL_PIN BIT(1)
31*4882a593Smuzhiyun #define PLL_CTRL_REG BIT(2)
32*4882a593Smuzhiyun #define PLL_ON BIT(3)
33*4882a593Smuzhiyun #define PHASE_OFF_TOL_125 (0x0 << 5)
34*4882a593Smuzhiyun #define PHASE_OFF_TOL_250 BIT(5)
35*4882a593Smuzhiyun #define KVC0_CALIB (0x0 << 9)
36*4882a593Smuzhiyun #define KVC0_REG_CTRL BIT(9)
37*4882a593Smuzhiyun #define KVC0_HIGH (0x0 << 10)
38*4882a593Smuzhiyun #define KVC0_LOW (0x3 << 10)
39*4882a593Smuzhiyun #define CLK_BLK_EN BIT(13)
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun /* USB_PHY_TX_CTRL0 */
42*4882a593Smuzhiyun #define EXT_HS_RCAL_EN BIT(3)
43*4882a593Smuzhiyun #define EXT_FS_RCAL_EN BIT(4)
44*4882a593Smuzhiyun #define IMPCAL_VTH_DIV(x) ((x) << 5)
45*4882a593Smuzhiyun #define EXT_RS_RCAL_DIV(x) ((x) << 8)
46*4882a593Smuzhiyun #define EXT_FS_RCAL_DIV(x) ((x) << 12)
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /* USB_PHY_TX_CTRL1 */
49*4882a593Smuzhiyun #define TX_VDD15_14 (0x0 << 4)
50*4882a593Smuzhiyun #define TX_VDD15_15 BIT(4)
51*4882a593Smuzhiyun #define TX_VDD15_16 (0x2 << 4)
52*4882a593Smuzhiyun #define TX_VDD15_17 (0x3 << 4)
53*4882a593Smuzhiyun #define TX_VDD12_VDD (0x0 << 6)
54*4882a593Smuzhiyun #define TX_VDD12_11 BIT(6)
55*4882a593Smuzhiyun #define TX_VDD12_12 (0x2 << 6)
56*4882a593Smuzhiyun #define TX_VDD12_13 (0x3 << 6)
57*4882a593Smuzhiyun #define LOW_VDD_EN BIT(8)
58*4882a593Smuzhiyun #define TX_OUT_AMP(x) ((x) << 9)
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun /* USB_PHY_TX_CTRL2 */
61*4882a593Smuzhiyun #define TX_CHAN_CTRL_REG(x) ((x) << 0)
62*4882a593Smuzhiyun #define DRV_SLEWRATE(x) ((x) << 4)
63*4882a593Smuzhiyun #define IMP_CAL_FS_HS_DLY_0 (0x0 << 6)
64*4882a593Smuzhiyun #define IMP_CAL_FS_HS_DLY_1 BIT(6)
65*4882a593Smuzhiyun #define IMP_CAL_FS_HS_DLY_2 (0x2 << 6)
66*4882a593Smuzhiyun #define IMP_CAL_FS_HS_DLY_3 (0x3 << 6)
67*4882a593Smuzhiyun #define FS_DRV_EN_MASK(x) ((x) << 8)
68*4882a593Smuzhiyun #define HS_DRV_EN_MASK(x) ((x) << 12)
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun /* USB_PHY_RX_CTRL */
71*4882a593Smuzhiyun #define PHASE_FREEZE_DLY_2_CL (0x0 << 0)
72*4882a593Smuzhiyun #define PHASE_FREEZE_DLY_4_CL BIT(0)
73*4882a593Smuzhiyun #define ACK_LENGTH_8_CL (0x0 << 2)
74*4882a593Smuzhiyun #define ACK_LENGTH_12_CL BIT(2)
75*4882a593Smuzhiyun #define ACK_LENGTH_16_CL (0x2 << 2)
76*4882a593Smuzhiyun #define ACK_LENGTH_20_CL (0x3 << 2)
77*4882a593Smuzhiyun #define SQ_LENGTH_3 (0x0 << 4)
78*4882a593Smuzhiyun #define SQ_LENGTH_6 BIT(4)
79*4882a593Smuzhiyun #define SQ_LENGTH_9 (0x2 << 4)
80*4882a593Smuzhiyun #define SQ_LENGTH_12 (0x3 << 4)
81*4882a593Smuzhiyun #define DISCON_THRESHOLD_260 (0x0 << 6)
82*4882a593Smuzhiyun #define DISCON_THRESHOLD_270 BIT(6)
83*4882a593Smuzhiyun #define DISCON_THRESHOLD_280 (0x2 << 6)
84*4882a593Smuzhiyun #define DISCON_THRESHOLD_290 (0x3 << 6)
85*4882a593Smuzhiyun #define SQ_THRESHOLD(x) ((x) << 8)
86*4882a593Smuzhiyun #define LPF_COEF(x) ((x) << 12)
87*4882a593Smuzhiyun #define INTPL_CUR_10 (0x0 << 14)
88*4882a593Smuzhiyun #define INTPL_CUR_20 BIT(14)
89*4882a593Smuzhiyun #define INTPL_CUR_30 (0x2 << 14)
90*4882a593Smuzhiyun #define INTPL_CUR_40 (0x3 << 14)
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun /* USB_PHY_ANALOG */
93*4882a593Smuzhiyun #define ANA_PWR_UP BIT(1)
94*4882a593Smuzhiyun #define ANA_PWR_DOWN BIT(2)
95*4882a593Smuzhiyun #define V2I_VCO_RATIO(x) ((x) << 7)
96*4882a593Smuzhiyun #define R_ROTATE_90 (0x0 << 10)
97*4882a593Smuzhiyun #define R_ROTATE_0 BIT(10)
98*4882a593Smuzhiyun #define MODE_TEST_EN BIT(11)
99*4882a593Smuzhiyun #define ANA_TEST_DC_CTRL(x) ((x) << 12)
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun static const u32 phy_berlin_pll_dividers[] = {
102*4882a593Smuzhiyun /* Berlin 2 */
103*4882a593Smuzhiyun CLK_REF_DIV(0x6) | FEEDBACK_CLK_DIV(0x55),
104*4882a593Smuzhiyun /* Berlin 2CD/Q */
105*4882a593Smuzhiyun CLK_REF_DIV(0xc) | FEEDBACK_CLK_DIV(0x54),
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun struct phy_berlin_usb_priv {
109*4882a593Smuzhiyun void __iomem *base;
110*4882a593Smuzhiyun struct reset_control *rst_ctrl;
111*4882a593Smuzhiyun u32 pll_divider;
112*4882a593Smuzhiyun };
113*4882a593Smuzhiyun
phy_berlin_usb_power_on(struct phy * phy)114*4882a593Smuzhiyun static int phy_berlin_usb_power_on(struct phy *phy)
115*4882a593Smuzhiyun {
116*4882a593Smuzhiyun struct phy_berlin_usb_priv *priv = phy_get_drvdata(phy);
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun reset_control_reset(priv->rst_ctrl);
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun writel(priv->pll_divider,
121*4882a593Smuzhiyun priv->base + USB_PHY_PLL);
122*4882a593Smuzhiyun writel(CLK_STABLE | PLL_CTRL_REG | PHASE_OFF_TOL_250 | KVC0_REG_CTRL |
123*4882a593Smuzhiyun CLK_BLK_EN, priv->base + USB_PHY_PLL_CONTROL);
124*4882a593Smuzhiyun writel(V2I_VCO_RATIO(0x5) | R_ROTATE_0 | ANA_TEST_DC_CTRL(0x5),
125*4882a593Smuzhiyun priv->base + USB_PHY_ANALOG);
126*4882a593Smuzhiyun writel(PHASE_FREEZE_DLY_4_CL | ACK_LENGTH_16_CL | SQ_LENGTH_12 |
127*4882a593Smuzhiyun DISCON_THRESHOLD_270 | SQ_THRESHOLD(0xa) | LPF_COEF(0x2) |
128*4882a593Smuzhiyun INTPL_CUR_30, priv->base + USB_PHY_RX_CTRL);
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun writel(TX_VDD12_13 | TX_OUT_AMP(0x3), priv->base + USB_PHY_TX_CTRL1);
131*4882a593Smuzhiyun writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
132*4882a593Smuzhiyun priv->base + USB_PHY_TX_CTRL0);
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4) |
135*4882a593Smuzhiyun EXT_FS_RCAL_DIV(0x2), priv->base + USB_PHY_TX_CTRL0);
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun writel(EXT_HS_RCAL_EN | IMPCAL_VTH_DIV(0x3) | EXT_RS_RCAL_DIV(0x4),
138*4882a593Smuzhiyun priv->base + USB_PHY_TX_CTRL0);
139*4882a593Smuzhiyun writel(TX_CHAN_CTRL_REG(0xf) | DRV_SLEWRATE(0x3) | IMP_CAL_FS_HS_DLY_3 |
140*4882a593Smuzhiyun FS_DRV_EN_MASK(0xd), priv->base + USB_PHY_TX_CTRL2);
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun return 0;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun static const struct phy_ops phy_berlin_usb_ops = {
146*4882a593Smuzhiyun .power_on = phy_berlin_usb_power_on,
147*4882a593Smuzhiyun .owner = THIS_MODULE,
148*4882a593Smuzhiyun };
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun static const struct of_device_id phy_berlin_usb_of_match[] = {
151*4882a593Smuzhiyun {
152*4882a593Smuzhiyun .compatible = "marvell,berlin2-usb-phy",
153*4882a593Smuzhiyun .data = &phy_berlin_pll_dividers[0],
154*4882a593Smuzhiyun },
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun .compatible = "marvell,berlin2cd-usb-phy",
157*4882a593Smuzhiyun .data = &phy_berlin_pll_dividers[1],
158*4882a593Smuzhiyun },
159*4882a593Smuzhiyun { },
160*4882a593Smuzhiyun };
161*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, phy_berlin_usb_of_match);
162*4882a593Smuzhiyun
phy_berlin_usb_probe(struct platform_device * pdev)163*4882a593Smuzhiyun static int phy_berlin_usb_probe(struct platform_device *pdev)
164*4882a593Smuzhiyun {
165*4882a593Smuzhiyun const struct of_device_id *match =
166*4882a593Smuzhiyun of_match_device(phy_berlin_usb_of_match, &pdev->dev);
167*4882a593Smuzhiyun struct phy_berlin_usb_priv *priv;
168*4882a593Smuzhiyun struct resource *res;
169*4882a593Smuzhiyun struct phy *phy;
170*4882a593Smuzhiyun struct phy_provider *phy_provider;
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
173*4882a593Smuzhiyun if (!priv)
174*4882a593Smuzhiyun return -ENOMEM;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
177*4882a593Smuzhiyun priv->base = devm_ioremap_resource(&pdev->dev, res);
178*4882a593Smuzhiyun if (IS_ERR(priv->base))
179*4882a593Smuzhiyun return PTR_ERR(priv->base);
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun priv->rst_ctrl = devm_reset_control_get(&pdev->dev, NULL);
182*4882a593Smuzhiyun if (IS_ERR(priv->rst_ctrl))
183*4882a593Smuzhiyun return PTR_ERR(priv->rst_ctrl);
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun priv->pll_divider = *((u32 *)match->data);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun phy = devm_phy_create(&pdev->dev, NULL, &phy_berlin_usb_ops);
188*4882a593Smuzhiyun if (IS_ERR(phy)) {
189*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to create PHY\n");
190*4882a593Smuzhiyun return PTR_ERR(phy);
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun phy_set_drvdata(phy, priv);
194*4882a593Smuzhiyun
195*4882a593Smuzhiyun phy_provider =
196*4882a593Smuzhiyun devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate);
197*4882a593Smuzhiyun return PTR_ERR_OR_ZERO(phy_provider);
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun static struct platform_driver phy_berlin_usb_driver = {
201*4882a593Smuzhiyun .probe = phy_berlin_usb_probe,
202*4882a593Smuzhiyun .driver = {
203*4882a593Smuzhiyun .name = "phy-berlin-usb",
204*4882a593Smuzhiyun .of_match_table = phy_berlin_usb_of_match,
205*4882a593Smuzhiyun },
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun module_platform_driver(phy_berlin_usb_driver);
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>");
210*4882a593Smuzhiyun MODULE_DESCRIPTION("Marvell Berlin PHY driver for USB");
211*4882a593Smuzhiyun MODULE_LICENSE("GPL");
212