xref: /OK3568_Linux_fs/kernel/drivers/phy/hisilicon/phy-hi6220-usb.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-or-later
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2015 Linaro Ltd.
4*4882a593Smuzhiyun  * Copyright (c) 2015 Hisilicon Limited.
5*4882a593Smuzhiyun  */
6*4882a593Smuzhiyun 
7*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/platform_device.h>
10*4882a593Smuzhiyun #include <linux/phy/phy.h>
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun #define SC_PERIPH_CTRL4			0x00c
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define CTRL4_PICO_SIDDQ		BIT(6)
16*4882a593Smuzhiyun #define CTRL4_PICO_OGDISABLE		BIT(8)
17*4882a593Smuzhiyun #define CTRL4_PICO_VBUSVLDEXT		BIT(10)
18*4882a593Smuzhiyun #define CTRL4_PICO_VBUSVLDEXTSEL	BIT(11)
19*4882a593Smuzhiyun #define CTRL4_OTG_PHY_SEL		BIT(21)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun #define SC_PERIPH_CTRL5			0x010
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define CTRL5_USBOTG_RES_SEL		BIT(3)
24*4882a593Smuzhiyun #define CTRL5_PICOPHY_ACAENB		BIT(4)
25*4882a593Smuzhiyun #define CTRL5_PICOPHY_BC_MODE		BIT(5)
26*4882a593Smuzhiyun #define CTRL5_PICOPHY_CHRGSEL		BIT(6)
27*4882a593Smuzhiyun #define CTRL5_PICOPHY_VDATSRCEND	BIT(7)
28*4882a593Smuzhiyun #define CTRL5_PICOPHY_VDATDETENB	BIT(8)
29*4882a593Smuzhiyun #define CTRL5_PICOPHY_DCDENB		BIT(9)
30*4882a593Smuzhiyun #define CTRL5_PICOPHY_IDDIG		BIT(10)
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun #define SC_PERIPH_CTRL8			0x018
33*4882a593Smuzhiyun #define SC_PERIPH_RSTEN0		0x300
34*4882a593Smuzhiyun #define SC_PERIPH_RSTDIS0		0x304
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun #define RST0_USBOTG_BUS			BIT(4)
37*4882a593Smuzhiyun #define RST0_POR_PICOPHY		BIT(5)
38*4882a593Smuzhiyun #define RST0_USBOTG			BIT(6)
39*4882a593Smuzhiyun #define RST0_USBOTG_32K			BIT(7)
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define EYE_PATTERN_PARA		0x7053348c
42*4882a593Smuzhiyun 
43*4882a593Smuzhiyun struct hi6220_priv {
44*4882a593Smuzhiyun 	struct regmap *reg;
45*4882a593Smuzhiyun 	struct device *dev;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun 
hi6220_phy_init(struct hi6220_priv * priv)48*4882a593Smuzhiyun static void hi6220_phy_init(struct hi6220_priv *priv)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun 	struct regmap *reg = priv->reg;
51*4882a593Smuzhiyun 	u32 val, mask;
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun 	val = RST0_USBOTG_BUS | RST0_POR_PICOPHY |
54*4882a593Smuzhiyun 	      RST0_USBOTG | RST0_USBOTG_32K;
55*4882a593Smuzhiyun 	mask = val;
56*4882a593Smuzhiyun 	regmap_update_bits(reg, SC_PERIPH_RSTEN0, mask, val);
57*4882a593Smuzhiyun 	regmap_update_bits(reg, SC_PERIPH_RSTDIS0, mask, val);
58*4882a593Smuzhiyun }
59*4882a593Smuzhiyun 
hi6220_phy_setup(struct hi6220_priv * priv,bool on)60*4882a593Smuzhiyun static int hi6220_phy_setup(struct hi6220_priv *priv, bool on)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun 	struct regmap *reg = priv->reg;
63*4882a593Smuzhiyun 	u32 val, mask;
64*4882a593Smuzhiyun 	int ret;
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	if (on) {
67*4882a593Smuzhiyun 		val = CTRL5_USBOTG_RES_SEL | CTRL5_PICOPHY_ACAENB;
68*4882a593Smuzhiyun 		mask = val | CTRL5_PICOPHY_BC_MODE;
69*4882a593Smuzhiyun 		ret = regmap_update_bits(reg, SC_PERIPH_CTRL5, mask, val);
70*4882a593Smuzhiyun 		if (ret)
71*4882a593Smuzhiyun 			goto out;
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 		val =  CTRL4_PICO_VBUSVLDEXT | CTRL4_PICO_VBUSVLDEXTSEL |
74*4882a593Smuzhiyun 		       CTRL4_OTG_PHY_SEL;
75*4882a593Smuzhiyun 		mask = val | CTRL4_PICO_SIDDQ | CTRL4_PICO_OGDISABLE;
76*4882a593Smuzhiyun 		ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val);
77*4882a593Smuzhiyun 		if (ret)
78*4882a593Smuzhiyun 			goto out;
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 		ret = regmap_write(reg, SC_PERIPH_CTRL8, EYE_PATTERN_PARA);
81*4882a593Smuzhiyun 		if (ret)
82*4882a593Smuzhiyun 			goto out;
83*4882a593Smuzhiyun 	} else {
84*4882a593Smuzhiyun 		val = CTRL4_PICO_SIDDQ;
85*4882a593Smuzhiyun 		mask = val;
86*4882a593Smuzhiyun 		ret = regmap_update_bits(reg, SC_PERIPH_CTRL4, mask, val);
87*4882a593Smuzhiyun 		if (ret)
88*4882a593Smuzhiyun 			goto out;
89*4882a593Smuzhiyun 	}
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	return 0;
92*4882a593Smuzhiyun out:
93*4882a593Smuzhiyun 	dev_err(priv->dev, "failed to setup phy ret: %d\n", ret);
94*4882a593Smuzhiyun 	return ret;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun 
hi6220_phy_start(struct phy * phy)97*4882a593Smuzhiyun static int hi6220_phy_start(struct phy *phy)
98*4882a593Smuzhiyun {
99*4882a593Smuzhiyun 	struct hi6220_priv *priv = phy_get_drvdata(phy);
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	return hi6220_phy_setup(priv, true);
102*4882a593Smuzhiyun }
103*4882a593Smuzhiyun 
hi6220_phy_exit(struct phy * phy)104*4882a593Smuzhiyun static int hi6220_phy_exit(struct phy *phy)
105*4882a593Smuzhiyun {
106*4882a593Smuzhiyun 	struct hi6220_priv *priv = phy_get_drvdata(phy);
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	return hi6220_phy_setup(priv, false);
109*4882a593Smuzhiyun }
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun static const struct phy_ops hi6220_phy_ops = {
112*4882a593Smuzhiyun 	.init		= hi6220_phy_start,
113*4882a593Smuzhiyun 	.exit		= hi6220_phy_exit,
114*4882a593Smuzhiyun 	.owner		= THIS_MODULE,
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun 
hi6220_phy_probe(struct platform_device * pdev)117*4882a593Smuzhiyun static int hi6220_phy_probe(struct platform_device *pdev)
118*4882a593Smuzhiyun {
119*4882a593Smuzhiyun 	struct phy_provider *phy_provider;
120*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
121*4882a593Smuzhiyun 	struct phy *phy;
122*4882a593Smuzhiyun 	struct hi6220_priv *priv;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
125*4882a593Smuzhiyun 	if (!priv)
126*4882a593Smuzhiyun 		return -ENOMEM;
127*4882a593Smuzhiyun 
128*4882a593Smuzhiyun 	priv->dev = dev;
129*4882a593Smuzhiyun 	priv->reg = syscon_regmap_lookup_by_phandle(dev->of_node,
130*4882a593Smuzhiyun 					"hisilicon,peripheral-syscon");
131*4882a593Smuzhiyun 	if (IS_ERR(priv->reg)) {
132*4882a593Smuzhiyun 		dev_err(dev, "no hisilicon,peripheral-syscon\n");
133*4882a593Smuzhiyun 		return PTR_ERR(priv->reg);
134*4882a593Smuzhiyun 	}
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	hi6220_phy_init(priv);
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	phy = devm_phy_create(dev, NULL, &hi6220_phy_ops);
139*4882a593Smuzhiyun 	if (IS_ERR(phy))
140*4882a593Smuzhiyun 		return PTR_ERR(phy);
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun 	phy_set_drvdata(phy, priv);
143*4882a593Smuzhiyun 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
144*4882a593Smuzhiyun 	return PTR_ERR_OR_ZERO(phy_provider);
145*4882a593Smuzhiyun }
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun static const struct of_device_id hi6220_phy_of_match[] = {
148*4882a593Smuzhiyun 	{.compatible = "hisilicon,hi6220-usb-phy",},
149*4882a593Smuzhiyun 	{ },
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, hi6220_phy_of_match);
152*4882a593Smuzhiyun 
153*4882a593Smuzhiyun static struct platform_driver hi6220_phy_driver = {
154*4882a593Smuzhiyun 	.probe	= hi6220_phy_probe,
155*4882a593Smuzhiyun 	.driver = {
156*4882a593Smuzhiyun 		.name	= "hi6220-usb-phy",
157*4882a593Smuzhiyun 		.of_match_table	= hi6220_phy_of_match,
158*4882a593Smuzhiyun 	}
159*4882a593Smuzhiyun };
160*4882a593Smuzhiyun module_platform_driver(hi6220_phy_driver);
161*4882a593Smuzhiyun 
162*4882a593Smuzhiyun MODULE_DESCRIPTION("HISILICON HI6220 USB PHY driver");
163*4882a593Smuzhiyun MODULE_ALIAS("platform:hi6220-usb-phy");
164*4882a593Smuzhiyun MODULE_LICENSE("GPL");
165