1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright (C) 2016 Broadcom
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or
5*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License as
6*4882a593Smuzhiyun * published by the Free Software Foundation version 2.
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9*4882a593Smuzhiyun * kind, whether express or implied; without even the implied warranty
10*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11*4882a593Smuzhiyun * GNU General Public License for more details.
12*4882a593Smuzhiyun */
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/device.h>
15*4882a593Smuzhiyun #include <linux/module.h>
16*4882a593Smuzhiyun #include <linux/of_mdio.h>
17*4882a593Smuzhiyun #include <linux/mdio.h>
18*4882a593Smuzhiyun #include <linux/phy.h>
19*4882a593Smuzhiyun #include <linux/phy/phy.h>
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun #define BLK_ADDR_REG_OFFSET 0x1f
22*4882a593Smuzhiyun #define PLL_AFE1_100MHZ_BLK 0x2100
23*4882a593Smuzhiyun #define PLL_CLK_AMP_OFFSET 0x03
24*4882a593Smuzhiyun #define PLL_CLK_AMP_2P05V 0x2b18
25*4882a593Smuzhiyun
ns2_pci_phy_init(struct phy * p)26*4882a593Smuzhiyun static int ns2_pci_phy_init(struct phy *p)
27*4882a593Smuzhiyun {
28*4882a593Smuzhiyun struct mdio_device *mdiodev = phy_get_drvdata(p);
29*4882a593Smuzhiyun int rc;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* select the AFE 100MHz block page */
32*4882a593Smuzhiyun rc = mdiobus_write(mdiodev->bus, mdiodev->addr,
33*4882a593Smuzhiyun BLK_ADDR_REG_OFFSET, PLL_AFE1_100MHZ_BLK);
34*4882a593Smuzhiyun if (rc)
35*4882a593Smuzhiyun goto err;
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun /* set the 100 MHz reference clock amplitude to 2.05 v */
38*4882a593Smuzhiyun rc = mdiobus_write(mdiodev->bus, mdiodev->addr,
39*4882a593Smuzhiyun PLL_CLK_AMP_OFFSET, PLL_CLK_AMP_2P05V);
40*4882a593Smuzhiyun if (rc)
41*4882a593Smuzhiyun goto err;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun return 0;
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun err:
46*4882a593Smuzhiyun dev_err(&mdiodev->dev, "Error %d writing to phy\n", rc);
47*4882a593Smuzhiyun return rc;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun static const struct phy_ops ns2_pci_phy_ops = {
51*4882a593Smuzhiyun .init = ns2_pci_phy_init,
52*4882a593Smuzhiyun .owner = THIS_MODULE,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
ns2_pci_phy_probe(struct mdio_device * mdiodev)55*4882a593Smuzhiyun static int ns2_pci_phy_probe(struct mdio_device *mdiodev)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun struct device *dev = &mdiodev->dev;
58*4882a593Smuzhiyun struct phy_provider *provider;
59*4882a593Smuzhiyun struct phy *phy;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun phy = devm_phy_create(dev, dev->of_node, &ns2_pci_phy_ops);
62*4882a593Smuzhiyun if (IS_ERR(phy)) {
63*4882a593Smuzhiyun dev_err(dev, "failed to create Phy\n");
64*4882a593Smuzhiyun return PTR_ERR(phy);
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun
67*4882a593Smuzhiyun phy_set_drvdata(phy, mdiodev);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun provider = devm_of_phy_provider_register(&phy->dev,
70*4882a593Smuzhiyun of_phy_simple_xlate);
71*4882a593Smuzhiyun if (IS_ERR(provider)) {
72*4882a593Smuzhiyun dev_err(dev, "failed to register Phy provider\n");
73*4882a593Smuzhiyun return PTR_ERR(provider);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun dev_info(dev, "%s PHY registered\n", dev_name(dev));
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun return 0;
79*4882a593Smuzhiyun }
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun static const struct of_device_id ns2_pci_phy_of_match[] = {
82*4882a593Smuzhiyun { .compatible = "brcm,ns2-pcie-phy", },
83*4882a593Smuzhiyun { /* sentinel */ },
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ns2_pci_phy_of_match);
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static struct mdio_driver ns2_pci_phy_driver = {
88*4882a593Smuzhiyun .mdiodrv = {
89*4882a593Smuzhiyun .driver = {
90*4882a593Smuzhiyun .name = "phy-bcm-ns2-pci",
91*4882a593Smuzhiyun .of_match_table = ns2_pci_phy_of_match,
92*4882a593Smuzhiyun },
93*4882a593Smuzhiyun },
94*4882a593Smuzhiyun .probe = ns2_pci_phy_probe,
95*4882a593Smuzhiyun };
96*4882a593Smuzhiyun mdio_module_driver(ns2_pci_phy_driver);
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun MODULE_AUTHOR("Broadcom");
99*4882a593Smuzhiyun MODULE_DESCRIPTION("Broadcom Northstar2 PCI Phy driver");
100*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
101*4882a593Smuzhiyun MODULE_ALIAS("platform:phy-bcm-ns2-pci");
102