1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * FILE NAME 3*4882a593Smuzhiyun * drivers/pcmcia/vrc4173_cardu.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * BRIEF MODULE DESCRIPTION 6*4882a593Smuzhiyun * Include file for NEC VRC4173 CARDU. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright 2002 Yoichi Yuasa <yuasa@linux-mips.org> 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or modify it 11*4882a593Smuzhiyun * under the terms of the GNU General Public License as published by the 12*4882a593Smuzhiyun * Free Software Foundation; either version 2 of the License, or (at your 13*4882a593Smuzhiyun * option) any later version. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED 16*4882a593Smuzhiyun * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 17*4882a593Smuzhiyun * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18*4882a593Smuzhiyun * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19*4882a593Smuzhiyun * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20*4882a593Smuzhiyun * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 21*4882a593Smuzhiyun * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 22*4882a593Smuzhiyun * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 23*4882a593Smuzhiyun * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE 24*4882a593Smuzhiyun * USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25*4882a593Smuzhiyun * 26*4882a593Smuzhiyun * You should have received a copy of the GNU General Public License along 27*4882a593Smuzhiyun * with this program; if not, write to the Free Software Foundation, Inc., 28*4882a593Smuzhiyun * 675 Mass Ave, Cambridge, MA 02139, USA. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #ifndef _VRC4173_CARDU_H 31*4882a593Smuzhiyun #define _VRC4173_CARDU_H 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #include <linux/pci.h> 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #include <pcmcia/ss.h> 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define CARDU_MAX_SOCKETS 2 38*4882a593Smuzhiyun #define CARDU1 0 39*4882a593Smuzhiyun #define CARDU2 1 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* 42*4882a593Smuzhiyun * PCI Configuration Registers 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define BRGCNT 0x3e 45*4882a593Smuzhiyun #define POST_WR_EN 0x0400 46*4882a593Smuzhiyun #define MEM1_PREF_EN 0x0200 47*4882a593Smuzhiyun #define MEM0_PREF_EN 0x0100 48*4882a593Smuzhiyun #define IREQ_INT 0x0080 49*4882a593Smuzhiyun #define CARD_RST 0x0040 50*4882a593Smuzhiyun #define MABORT_MODE 0x0020 51*4882a593Smuzhiyun #define VGA_EN 0x0008 52*4882a593Smuzhiyun #define ISA_EN 0x0004 53*4882a593Smuzhiyun #define SERR_EN 0x0002 54*4882a593Smuzhiyun #define PERR_EN 0x0001 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define SYSCNT 0x80 57*4882a593Smuzhiyun #define BAD_VCC_REQ_DISB 0x00200000 58*4882a593Smuzhiyun #define PCPCI_EN 0x00080000 59*4882a593Smuzhiyun #define CH_ASSIGN_MASK 0x00070000 60*4882a593Smuzhiyun #define CH_ASSIGN_NODMA 0x00040000 61*4882a593Smuzhiyun #define SUB_ID_WR_EN 0x00000008 62*4882a593Smuzhiyun #define ASYN_INT_MODE 0x00000004 63*4882a593Smuzhiyun #define PCI_CLK_RIN 0x00000002 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define DEVCNT 0x91 66*4882a593Smuzhiyun #define ZOOM_VIDEO_EN 0x40 67*4882a593Smuzhiyun #define SR_PCI_INT_SEL_MASK 0x18 68*4882a593Smuzhiyun #define SR_PCI_INT_SEL_NONE 0x00 69*4882a593Smuzhiyun #define PCI_INT_MODE 0x04 70*4882a593Smuzhiyun #define IRQ_MODE 0x02 71*4882a593Smuzhiyun #define IFG 0x01 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define CHIPCNT 0x9c 74*4882a593Smuzhiyun #define S_PREF_DISB 0x10 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define SERRDIS 0x9f 77*4882a593Smuzhiyun #define SERR_DIS_MAB 0x10 78*4882a593Smuzhiyun #define SERR_DIS_TAB 0x08 79*4882a593Smuzhiyun #define SERR_DIS_DT_PERR 0x04 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun /* 82*4882a593Smuzhiyun * ExCA Registers 83*4882a593Smuzhiyun */ 84*4882a593Smuzhiyun #define EXCA_REGS_BASE 0x800 85*4882a593Smuzhiyun #define EXCA_REGS_SIZE 0x800 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define ID_REV 0x000 88*4882a593Smuzhiyun #define IF_TYPE_16BIT 0x80 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun #define IF_STATUS 0x001 91*4882a593Smuzhiyun #define CARD_PWR 0x40 92*4882a593Smuzhiyun #define READY 0x20 93*4882a593Smuzhiyun #define CARD_WP 0x10 94*4882a593Smuzhiyun #define CARD_DETECT2 0x08 95*4882a593Smuzhiyun #define CARD_DETECT1 0x04 96*4882a593Smuzhiyun #define BV_DETECT_MASK 0x03 97*4882a593Smuzhiyun #define BV_DETECT_GOOD 0x03 /* Memory card */ 98*4882a593Smuzhiyun #define BV_DETECT_WARN 0x02 99*4882a593Smuzhiyun #define BV_DETECT_BAD1 0x01 100*4882a593Smuzhiyun #define BV_DETECT_BAD0 0x00 101*4882a593Smuzhiyun #define STSCHG 0x02 /* I/O card */ 102*4882a593Smuzhiyun #define SPKR 0x01 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #define PWR_CNT 0x002 105*4882a593Smuzhiyun #define CARD_OUT_EN 0x80 106*4882a593Smuzhiyun #define VCC_MASK 0x18 107*4882a593Smuzhiyun #define VCC_3V 0x18 108*4882a593Smuzhiyun #define VCC_5V 0x10 109*4882a593Smuzhiyun #define VCC_0V 0x00 110*4882a593Smuzhiyun #define VPP_MASK 0x03 111*4882a593Smuzhiyun #define VPP_12V 0x02 112*4882a593Smuzhiyun #define VPP_VCC 0x01 113*4882a593Smuzhiyun #define VPP_0V 0x00 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun #define INT_GEN_CNT 0x003 116*4882a593Smuzhiyun #define CARD_REST0 0x40 117*4882a593Smuzhiyun #define CARD_TYPE_MASK 0x20 118*4882a593Smuzhiyun #define CARD_TYPE_IO 0x20 119*4882a593Smuzhiyun #define CARD_TYPE_MEM 0x00 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define CARD_SC 0x004 122*4882a593Smuzhiyun #define CARD_DT_CHG 0x08 123*4882a593Smuzhiyun #define RDY_CHG 0x04 124*4882a593Smuzhiyun #define BAT_WAR_CHG 0x02 125*4882a593Smuzhiyun #define BAT_DEAD_ST_CHG 0x01 126*4882a593Smuzhiyun 127*4882a593Smuzhiyun #define CARD_SCI 0x005 128*4882a593Smuzhiyun #define CARD_DT_EN 0x08 129*4882a593Smuzhiyun #define RDY_EN 0x04 130*4882a593Smuzhiyun #define BAT_WAR_EN 0x02 131*4882a593Smuzhiyun #define BAT_DEAD_EN 0x01 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun #define ADR_WIN_EN 0x006 134*4882a593Smuzhiyun #define IO_WIN_EN(x) (0x40 << (x)) 135*4882a593Smuzhiyun #define MEM_WIN_EN(x) (0x01 << (x)) 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define IO_WIN_CNT 0x007 138*4882a593Smuzhiyun #define IO_WIN_CNT_MASK(x) (0x03 << ((x) << 2)) 139*4882a593Smuzhiyun #define IO_WIN_DATA_AUTOSZ(x) (0x02 << ((x) << 2)) 140*4882a593Smuzhiyun #define IO_WIN_DATA_16BIT(x) (0x01 << ((x) << 2)) 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define IO_WIN_SA(x) (0x008 + ((x) << 2)) 143*4882a593Smuzhiyun #define IO_WIN_EA(x) (0x00a + ((x) << 2)) 144*4882a593Smuzhiyun 145*4882a593Smuzhiyun #define MEM_WIN_SA(x) (0x010 + ((x) << 3)) 146*4882a593Smuzhiyun #define MEM_WIN_DSIZE 0x8000 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun #define MEM_WIN_EA(x) (0x012 + ((x) << 3)) 149*4882a593Smuzhiyun 150*4882a593Smuzhiyun #define MEM_WIN_OA(x) (0x014 + ((x) << 3)) 151*4882a593Smuzhiyun #define MEM_WIN_WP 0x8000 152*4882a593Smuzhiyun #define MEM_WIN_REGSET 0x4000 153*4882a593Smuzhiyun 154*4882a593Smuzhiyun #define GEN_CNT 0x016 155*4882a593Smuzhiyun #define VS2_STATUS 0x80 156*4882a593Smuzhiyun #define VS1_STATUS 0x40 157*4882a593Smuzhiyun #define EXCA_REG_RST_EN 0x02 158*4882a593Smuzhiyun 159*4882a593Smuzhiyun #define GLO_CNT 0x01e 160*4882a593Smuzhiyun #define FUN_INT_LEV 0x08 161*4882a593Smuzhiyun #define INT_WB_CLR 0x04 162*4882a593Smuzhiyun #define CSC_INT_LEV 0x02 163*4882a593Smuzhiyun 164*4882a593Smuzhiyun #define IO_WIN_OAL(x) (0x036 + ((x) << 1)) 165*4882a593Smuzhiyun #define IO_WIN_OAH(x) (0x037 + ((x) << 1)) 166*4882a593Smuzhiyun 167*4882a593Smuzhiyun #define MEM_WIN_SAU(x) (0x040 + (x)) 168*4882a593Smuzhiyun 169*4882a593Smuzhiyun #define IO_SETUP_TIM 0x080 170*4882a593Smuzhiyun #define IO_CMD_TIM 0x081 171*4882a593Smuzhiyun #define IO_HOLD_TIM 0x082 172*4882a593Smuzhiyun #define MEM_SETUP_TIM(x) (0x084 + ((x) << 2)) 173*4882a593Smuzhiyun #define MEM_CMD_TIM(x) (0x085 + ((x) << 2)) 174*4882a593Smuzhiyun #define MEM_HOLD_TIM(x) (0x086 + ((x) << 2)) 175*4882a593Smuzhiyun #define TIM_CLOCKS(x) ((x) - 1) 176*4882a593Smuzhiyun 177*4882a593Smuzhiyun #define MEM_TIM_SEL1 0x08c 178*4882a593Smuzhiyun #define MEM_TIM_SEL2 0x08d 179*4882a593Smuzhiyun #define MEM_WIN_TIMSEL1(x) (0x03 << (((x) & 3) << 1)) 180*4882a593Smuzhiyun 181*4882a593Smuzhiyun #define MEM_WIN_PWEN 0x091 182*4882a593Smuzhiyun #define POSTWEN 0x01 183*4882a593Smuzhiyun 184*4882a593Smuzhiyun /* 185*4882a593Smuzhiyun * CardBus Socket Registers 186*4882a593Smuzhiyun */ 187*4882a593Smuzhiyun #define CARDBUS_SOCKET_REGS_BASE 0x000 188*4882a593Smuzhiyun #define CARDBUS_SOCKET_REGS_SIZE 0x800 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun #define SKT_EV 0x000 191*4882a593Smuzhiyun #define POW_CYC_EV 0x00000008 192*4882a593Smuzhiyun #define CCD2_EV 0x00000004 193*4882a593Smuzhiyun #define CCD1_EV 0x00000002 194*4882a593Smuzhiyun #define CSTSCHG_EV 0x00000001 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun #define SKT_MASK 0x004 197*4882a593Smuzhiyun #define POW_CYC_MASK 0x00000008 198*4882a593Smuzhiyun #define CCD_MASK 0x00000006 199*4882a593Smuzhiyun #define CSC_MASK 0x00000001 200*4882a593Smuzhiyun 201*4882a593Smuzhiyun #define SKT_PRE_STATE 0x008 202*4882a593Smuzhiyun #define SKT_FORCE_EV 0x00c 203*4882a593Smuzhiyun #define VOL_3V_SKT 0x20000000 204*4882a593Smuzhiyun #define VOL_5V_SKT 0x10000000 205*4882a593Smuzhiyun #define CVS_TEST 0x00004000 206*4882a593Smuzhiyun #define VOL_YV_CARD_DT 0x00002000 207*4882a593Smuzhiyun #define VOL_XV_CARD_DT 0x00001000 208*4882a593Smuzhiyun #define VOL_3V_CARD_DT 0x00000800 209*4882a593Smuzhiyun #define VOL_5V_CARD_DT 0x00000400 210*4882a593Smuzhiyun #define BAD_VCC_REQ 0x00000200 211*4882a593Smuzhiyun #define DATA_LOST 0x00000100 212*4882a593Smuzhiyun #define NOT_A_CARD 0x00000080 213*4882a593Smuzhiyun #define CREADY 0x00000040 214*4882a593Smuzhiyun #define CB_CARD_DT 0x00000020 215*4882a593Smuzhiyun #define R2_CARD_DT 0x00000010 216*4882a593Smuzhiyun #define POW_UP 0x00000008 217*4882a593Smuzhiyun #define CCD20 0x00000004 218*4882a593Smuzhiyun #define CCD10 0x00000002 219*4882a593Smuzhiyun #define CSTSCHG 0x00000001 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun #define SKT_CNT 0x010 222*4882a593Smuzhiyun #define STP_CLK_EN 0x00000080 223*4882a593Smuzhiyun #define VCC_CNT_MASK 0x00000070 224*4882a593Smuzhiyun #define VCC_CNT_3V 0x00000030 225*4882a593Smuzhiyun #define VCC_CNT_5V 0x00000020 226*4882a593Smuzhiyun #define VCC_CNT_0V 0x00000000 227*4882a593Smuzhiyun #define VPP_CNT_MASK 0x00000007 228*4882a593Smuzhiyun #define VPP_CNT_3V 0x00000003 229*4882a593Smuzhiyun #define VPP_CNT_5V 0x00000002 230*4882a593Smuzhiyun #define VPP_CNT_12V 0x00000001 231*4882a593Smuzhiyun #define VPP_CNT_0V 0x00000000 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun typedef struct vrc4173_socket { 234*4882a593Smuzhiyun int noprobe; 235*4882a593Smuzhiyun struct pci_dev *dev; 236*4882a593Smuzhiyun void *base; 237*4882a593Smuzhiyun void (*handler)(void *, unsigned int); 238*4882a593Smuzhiyun void *info; 239*4882a593Smuzhiyun socket_cap_t cap; 240*4882a593Smuzhiyun spinlock_t event_lock; 241*4882a593Smuzhiyun uint16_t events; 242*4882a593Smuzhiyun struct socket_info_t *pcmcia_socket; 243*4882a593Smuzhiyun struct work_struct tq_work; 244*4882a593Smuzhiyun char name[20]; 245*4882a593Smuzhiyun } vrc4173_socket_t; 246*4882a593Smuzhiyun 247*4882a593Smuzhiyun #endif /* _VRC4173_CARDU_H */ 248