xref: /OK3568_Linux_fs/kernel/drivers/pcmcia/sa11xx_base.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*======================================================================
2*4882a593Smuzhiyun 
3*4882a593Smuzhiyun     Device driver for the PCMCIA control functionality of StrongARM
4*4882a593Smuzhiyun     SA-1100 microprocessors.
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun     The contents of this file are subject to the Mozilla Public
7*4882a593Smuzhiyun     License Version 1.1 (the "License"); you may not use this file
8*4882a593Smuzhiyun     except in compliance with the License. You may obtain a copy of
9*4882a593Smuzhiyun     the License at http://www.mozilla.org/MPL/
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun     Software distributed under the License is distributed on an "AS
12*4882a593Smuzhiyun     IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
13*4882a593Smuzhiyun     implied. See the License for the specific language governing
14*4882a593Smuzhiyun     rights and limitations under the License.
15*4882a593Smuzhiyun 
16*4882a593Smuzhiyun     The initial developer of the original code is John G. Dorsey
17*4882a593Smuzhiyun     <john+@cs.cmu.edu>.  Portions created by John G. Dorsey are
18*4882a593Smuzhiyun     Copyright (C) 1999 John G. Dorsey.  All Rights Reserved.
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun     Alternatively, the contents of this file may be used under the
21*4882a593Smuzhiyun     terms of the GNU Public License version 2 (the "GPL"), in which
22*4882a593Smuzhiyun     case the provisions of the GPL are applicable instead of the
23*4882a593Smuzhiyun     above.  If you wish to allow the use of your version of this file
24*4882a593Smuzhiyun     only under the terms of the GPL and not to allow others to use
25*4882a593Smuzhiyun     your version of this file under the MPL, indicate your decision
26*4882a593Smuzhiyun     by deleting the provisions above and replace them with the notice
27*4882a593Smuzhiyun     and other provisions required by the GPL.  If you do not delete
28*4882a593Smuzhiyun     the provisions above, a recipient may use your version of this
29*4882a593Smuzhiyun     file under either the MPL or the GPL.
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun ======================================================================*/
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #if !defined(_PCMCIA_SA1100_H)
34*4882a593Smuzhiyun # define _PCMCIA_SA1100_H
35*4882a593Smuzhiyun 
36*4882a593Smuzhiyun /* SA-1100 PCMCIA Memory and I/O timing
37*4882a593Smuzhiyun  * ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
38*4882a593Smuzhiyun  * The SA-1110 Developer's Manual, section 10.2.5, says the following:
39*4882a593Smuzhiyun  *
40*4882a593Smuzhiyun  *  "To calculate the recommended BS_xx value for each address space:
41*4882a593Smuzhiyun  *   divide the command width time (the greater of twIOWR and twIORD,
42*4882a593Smuzhiyun  *   or the greater of twWE and twOE) by processor cycle time; divide
43*4882a593Smuzhiyun  *   by 2; divide again by 3 (number of BCLK's per command assertion);
44*4882a593Smuzhiyun  *   round up to the next whole number; and subtract 1."
45*4882a593Smuzhiyun  */
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* MECR: Expansion Memory Configuration Register
48*4882a593Smuzhiyun  * (SA-1100 Developers Manual, p.10-13; SA-1110 Developers Manual, p.10-24)
49*4882a593Smuzhiyun  *
50*4882a593Smuzhiyun  * MECR layout is:
51*4882a593Smuzhiyun  *
52*4882a593Smuzhiyun  *   FAST1 BSM1<4:0> BSA1<4:0> BSIO1<4:0> FAST0 BSM0<4:0> BSA0<4:0> BSIO0<4:0>
53*4882a593Smuzhiyun  *
54*4882a593Smuzhiyun  * (This layout is actually true only for the SA-1110; the FASTn bits are
55*4882a593Smuzhiyun  * reserved on the SA-1100.)
56*4882a593Smuzhiyun  */
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun #define MECR_SOCKET_0_SHIFT (0)
59*4882a593Smuzhiyun #define MECR_SOCKET_1_SHIFT (16)
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun #define MECR_BS_MASK        (0x1f)
62*4882a593Smuzhiyun #define MECR_FAST_MODE_MASK (0x01)
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun #define MECR_BSIO_SHIFT (0)
65*4882a593Smuzhiyun #define MECR_BSA_SHIFT  (5)
66*4882a593Smuzhiyun #define MECR_BSM_SHIFT  (10)
67*4882a593Smuzhiyun #define MECR_FAST_SHIFT (15)
68*4882a593Smuzhiyun 
69*4882a593Smuzhiyun #define MECR_SET(mecr, sock, shift, mask, bs) \
70*4882a593Smuzhiyun ((mecr)=((mecr)&~(((mask)<<(shift))<<\
71*4882a593Smuzhiyun                   ((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))|\
72*4882a593Smuzhiyun         (((bs)<<(shift))<<((sock)==0?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT)))
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun #define MECR_GET(mecr, sock, shift, mask) \
75*4882a593Smuzhiyun ((((mecr)>>(((sock)==0)?MECR_SOCKET_0_SHIFT:MECR_SOCKET_1_SHIFT))>>\
76*4882a593Smuzhiyun  (shift))&(mask))
77*4882a593Smuzhiyun 
78*4882a593Smuzhiyun #define MECR_BSIO_SET(mecr, sock, bs) \
79*4882a593Smuzhiyun MECR_SET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK, (bs))
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun #define MECR_BSIO_GET(mecr, sock) \
82*4882a593Smuzhiyun MECR_GET((mecr), (sock), MECR_BSIO_SHIFT, MECR_BS_MASK)
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #define MECR_BSA_SET(mecr, sock, bs) \
85*4882a593Smuzhiyun MECR_SET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK, (bs))
86*4882a593Smuzhiyun 
87*4882a593Smuzhiyun #define MECR_BSA_GET(mecr, sock) \
88*4882a593Smuzhiyun MECR_GET((mecr), (sock), MECR_BSA_SHIFT, MECR_BS_MASK)
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define MECR_BSM_SET(mecr, sock, bs) \
91*4882a593Smuzhiyun MECR_SET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK, (bs))
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun #define MECR_BSM_GET(mecr, sock) \
94*4882a593Smuzhiyun MECR_GET((mecr), (sock), MECR_BSM_SHIFT, MECR_BS_MASK)
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun #define MECR_FAST_SET(mecr, sock, fast) \
97*4882a593Smuzhiyun MECR_SET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK, (fast))
98*4882a593Smuzhiyun 
99*4882a593Smuzhiyun #define MECR_FAST_GET(mecr, sock) \
100*4882a593Smuzhiyun MECR_GET((mecr), (sock), MECR_FAST_SHIFT, MECR_FAST_MODE_MASK)
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun /* This function implements the BS value calculation for setting the MECR
104*4882a593Smuzhiyun  * using integer arithmetic:
105*4882a593Smuzhiyun  */
sa1100_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns,unsigned int cpu_clock_khz)106*4882a593Smuzhiyun static inline unsigned int sa1100_pcmcia_mecr_bs(unsigned int pcmcia_cycle_ns,
107*4882a593Smuzhiyun 						 unsigned int cpu_clock_khz){
108*4882a593Smuzhiyun   unsigned int t = ((pcmcia_cycle_ns * cpu_clock_khz) / 6) - 1000000;
109*4882a593Smuzhiyun   return (t / 1000000) + (((t % 1000000) == 0) ? 0 : 1);
110*4882a593Smuzhiyun }
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun /* This function returns the (approximate) command assertion period, in
113*4882a593Smuzhiyun  * nanoseconds, for a given CPU clock frequency and MECR BS value:
114*4882a593Smuzhiyun  */
sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz,unsigned int pcmcia_mecr_bs)115*4882a593Smuzhiyun static inline unsigned int sa1100_pcmcia_cmd_time(unsigned int cpu_clock_khz,
116*4882a593Smuzhiyun 						  unsigned int pcmcia_mecr_bs){
117*4882a593Smuzhiyun   return (((10000000 * 2) / cpu_clock_khz) * (3 * (pcmcia_mecr_bs + 1))) / 10;
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun int sa11xx_drv_pcmcia_add_one(struct soc_pcmcia_socket *skt);
122*4882a593Smuzhiyun void sa11xx_drv_pcmcia_ops(struct pcmcia_low_level *ops);
123*4882a593Smuzhiyun extern int sa11xx_drv_pcmcia_probe(struct device *dev, struct pcmcia_low_level *ops, int first, int nr);
124*4882a593Smuzhiyun 
125*4882a593Smuzhiyun #endif  /* !defined(_PCMCIA_SA1100_H) */
126