1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * o2micro.h 1.13 1999/10/25 20:03:34
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * The contents of this file are subject to the Mozilla Public License
5*4882a593Smuzhiyun * Version 1.1 (the "License"); you may not use this file except in
6*4882a593Smuzhiyun * compliance with the License. You may obtain a copy of the License
7*4882a593Smuzhiyun * at http://www.mozilla.org/MPL/
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * Software distributed under the License is distributed on an "AS IS"
10*4882a593Smuzhiyun * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See
11*4882a593Smuzhiyun * the License for the specific language governing rights and
12*4882a593Smuzhiyun * limitations under the License.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * The initial developer of the original code is David A. Hinds
15*4882a593Smuzhiyun * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
16*4882a593Smuzhiyun * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
17*4882a593Smuzhiyun *
18*4882a593Smuzhiyun * Alternatively, the contents of this file may be used under the
19*4882a593Smuzhiyun * terms of the GNU General Public License version 2 (the "GPL"), in which
20*4882a593Smuzhiyun * case the provisions of the GPL are applicable instead of the
21*4882a593Smuzhiyun * above. If you wish to allow the use of your version of this file
22*4882a593Smuzhiyun * only under the terms of the GPL and not to allow others to use
23*4882a593Smuzhiyun * your version of this file under the MPL, indicate your decision by
24*4882a593Smuzhiyun * deleting the provisions above and replace them with the notice and
25*4882a593Smuzhiyun * other provisions required by the GPL. If you do not delete the
26*4882a593Smuzhiyun * provisions above, a recipient may use your version of this file
27*4882a593Smuzhiyun * under either the MPL or the GPL.
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #ifndef _LINUX_O2MICRO_H
31*4882a593Smuzhiyun #define _LINUX_O2MICRO_H
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /* Additional PCI configuration registers */
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define O2_MUX_CONTROL 0x90 /* 32 bit */
36*4882a593Smuzhiyun #define O2_MUX_RING_OUT 0x0000000f
37*4882a593Smuzhiyun #define O2_MUX_SKTB_ACTV 0x000000f0
38*4882a593Smuzhiyun #define O2_MUX_SCTA_ACTV_ENA 0x00000100
39*4882a593Smuzhiyun #define O2_MUX_SCTB_ACTV_ENA 0x00000200
40*4882a593Smuzhiyun #define O2_MUX_SER_IRQ_ROUTE 0x0000e000
41*4882a593Smuzhiyun #define O2_MUX_SER_PCI 0x00010000
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun #define O2_MUX_SKTA_TURBO 0x000c0000 /* for 6833, 6860 */
44*4882a593Smuzhiyun #define O2_MUX_SKTB_TURBO 0x00300000
45*4882a593Smuzhiyun #define O2_MUX_AUX_VCC_3V 0x00400000
46*4882a593Smuzhiyun #define O2_MUX_PCI_VCC_5V 0x00800000
47*4882a593Smuzhiyun #define O2_MUX_PME_MUX 0x0f000000
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* Additional ExCA registers */
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun #define O2_MODE_A 0x38
52*4882a593Smuzhiyun #define O2_MODE_A_2 0x26 /* for 6833B, 6860C */
53*4882a593Smuzhiyun #define O2_MODE_A_CD_PULSE 0x04
54*4882a593Smuzhiyun #define O2_MODE_A_SUSP_EDGE 0x08
55*4882a593Smuzhiyun #define O2_MODE_A_HOST_SUSP 0x10
56*4882a593Smuzhiyun #define O2_MODE_A_PWR_MASK 0x60
57*4882a593Smuzhiyun #define O2_MODE_A_QUIET 0x80
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define O2_MODE_B 0x39
60*4882a593Smuzhiyun #define O2_MODE_B_2 0x2e /* for 6833B, 6860C */
61*4882a593Smuzhiyun #define O2_MODE_B_IDENT 0x03
62*4882a593Smuzhiyun #define O2_MODE_B_ID_BSTEP 0x00
63*4882a593Smuzhiyun #define O2_MODE_B_ID_CSTEP 0x01
64*4882a593Smuzhiyun #define O2_MODE_B_ID_O2 0x02
65*4882a593Smuzhiyun #define O2_MODE_B_VS1 0x04
66*4882a593Smuzhiyun #define O2_MODE_B_VS2 0x08
67*4882a593Smuzhiyun #define O2_MODE_B_IRQ15_RI 0x80
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun #define O2_MODE_C 0x3a
70*4882a593Smuzhiyun #define O2_MODE_C_DREQ_MASK 0x03
71*4882a593Smuzhiyun #define O2_MODE_C_DREQ_INPACK 0x01
72*4882a593Smuzhiyun #define O2_MODE_C_DREQ_WP 0x02
73*4882a593Smuzhiyun #define O2_MODE_C_DREQ_BVD2 0x03
74*4882a593Smuzhiyun #define O2_MODE_C_ZVIDEO 0x08
75*4882a593Smuzhiyun #define O2_MODE_C_IREQ_SEL 0x30
76*4882a593Smuzhiyun #define O2_MODE_C_MGMT_SEL 0xc0
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define O2_MODE_D 0x3b
79*4882a593Smuzhiyun #define O2_MODE_D_IRQ_MODE 0x03
80*4882a593Smuzhiyun #define O2_MODE_D_PCI_CLKRUN 0x04
81*4882a593Smuzhiyun #define O2_MODE_D_CB_CLKRUN 0x08
82*4882a593Smuzhiyun #define O2_MODE_D_SKT_ACTV 0x20
83*4882a593Smuzhiyun #define O2_MODE_D_PCI_FIFO 0x40 /* for OZ6729, OZ6730 */
84*4882a593Smuzhiyun #define O2_MODE_D_W97_IRQ 0x40
85*4882a593Smuzhiyun #define O2_MODE_D_ISA_IRQ 0x80
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define O2_MHPG_DMA 0x3c
88*4882a593Smuzhiyun #define O2_MHPG_CHANNEL 0x07
89*4882a593Smuzhiyun #define O2_MHPG_CINT_ENA 0x08
90*4882a593Smuzhiyun #define O2_MHPG_CSC_ENA 0x10
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun #define O2_FIFO_ENA 0x3d
93*4882a593Smuzhiyun #define O2_FIFO_ZVIDEO_3 0x08
94*4882a593Smuzhiyun #define O2_FIFO_PCI_FIFO 0x10
95*4882a593Smuzhiyun #define O2_FIFO_POSTWR 0x40
96*4882a593Smuzhiyun #define O2_FIFO_BUFFER 0x80
97*4882a593Smuzhiyun
98*4882a593Smuzhiyun #define O2_MODE_E 0x3e
99*4882a593Smuzhiyun #define O2_MODE_E_MHPG_DMA 0x01
100*4882a593Smuzhiyun #define O2_MODE_E_SPKR_OUT 0x02
101*4882a593Smuzhiyun #define O2_MODE_E_LED_OUT 0x08
102*4882a593Smuzhiyun #define O2_MODE_E_SKTA_ACTV 0x10
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun #define O2_RESERVED1 0x94
105*4882a593Smuzhiyun #define O2_RESERVED2 0xD4
106*4882a593Smuzhiyun #define O2_RES_READ_PREFETCH 0x02
107*4882a593Smuzhiyun #define O2_RES_WRITE_BURST 0x08
108*4882a593Smuzhiyun
o2micro_override(struct yenta_socket * socket)109*4882a593Smuzhiyun static int o2micro_override(struct yenta_socket *socket)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun /*
112*4882a593Smuzhiyun * 'reserved' register at 0x94/D4. allows setting read prefetch and write
113*4882a593Smuzhiyun * bursting. read prefetching for example makes the RME Hammerfall DSP
114*4882a593Smuzhiyun * working. for some bridges it is at 0x94, for others at 0xD4. it's
115*4882a593Smuzhiyun * ok to write to both registers on all O2 bridges.
116*4882a593Smuzhiyun * from Eric Still, 02Micro.
117*4882a593Smuzhiyun */
118*4882a593Smuzhiyun u8 a, b;
119*4882a593Smuzhiyun bool use_speedup;
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun if (PCI_FUNC(socket->dev->devfn) == 0) {
122*4882a593Smuzhiyun a = config_readb(socket, O2_RESERVED1);
123*4882a593Smuzhiyun b = config_readb(socket, O2_RESERVED2);
124*4882a593Smuzhiyun dev_dbg(&socket->dev->dev, "O2: 0x94/0xD4: %02x/%02x\n", a, b);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun switch (socket->dev->device) {
127*4882a593Smuzhiyun /*
128*4882a593Smuzhiyun * older bridges have problems with both read prefetch and write
129*4882a593Smuzhiyun * bursting depending on the combination of the chipset, bridge
130*4882a593Smuzhiyun * and the cardbus card. so disable them to be on the safe side.
131*4882a593Smuzhiyun */
132*4882a593Smuzhiyun case PCI_DEVICE_ID_O2_6729:
133*4882a593Smuzhiyun case PCI_DEVICE_ID_O2_6730:
134*4882a593Smuzhiyun case PCI_DEVICE_ID_O2_6812:
135*4882a593Smuzhiyun case PCI_DEVICE_ID_O2_6832:
136*4882a593Smuzhiyun case PCI_DEVICE_ID_O2_6836:
137*4882a593Smuzhiyun case PCI_DEVICE_ID_O2_6933:
138*4882a593Smuzhiyun use_speedup = false;
139*4882a593Smuzhiyun break;
140*4882a593Smuzhiyun default:
141*4882a593Smuzhiyun use_speedup = true;
142*4882a593Smuzhiyun break;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* the user may override our decision */
146*4882a593Smuzhiyun if (strcasecmp(o2_speedup, "on") == 0)
147*4882a593Smuzhiyun use_speedup = true;
148*4882a593Smuzhiyun else if (strcasecmp(o2_speedup, "off") == 0)
149*4882a593Smuzhiyun use_speedup = false;
150*4882a593Smuzhiyun else if (strcasecmp(o2_speedup, "default") != 0)
151*4882a593Smuzhiyun dev_warn(&socket->dev->dev,
152*4882a593Smuzhiyun "O2: Unknown parameter, using 'default'");
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (use_speedup) {
155*4882a593Smuzhiyun dev_info(&socket->dev->dev,
156*4882a593Smuzhiyun "O2: enabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=off'\n");
157*4882a593Smuzhiyun config_writeb(socket, O2_RESERVED1,
158*4882a593Smuzhiyun a | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
159*4882a593Smuzhiyun config_writeb(socket, O2_RESERVED2,
160*4882a593Smuzhiyun b | O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST);
161*4882a593Smuzhiyun } else {
162*4882a593Smuzhiyun dev_info(&socket->dev->dev,
163*4882a593Smuzhiyun "O2: disabling read prefetch/write burst. If you experience problems or performance issues, use the yenta_socket parameter 'o2_speedup=on'\n");
164*4882a593Smuzhiyun config_writeb(socket, O2_RESERVED1,
165*4882a593Smuzhiyun a & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
166*4882a593Smuzhiyun config_writeb(socket, O2_RESERVED2,
167*4882a593Smuzhiyun b & ~(O2_RES_READ_PREFETCH | O2_RES_WRITE_BURST));
168*4882a593Smuzhiyun }
169*4882a593Smuzhiyun }
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun return 0;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun
o2micro_restore_state(struct yenta_socket * socket)174*4882a593Smuzhiyun static void o2micro_restore_state(struct yenta_socket *socket)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun /*
177*4882a593Smuzhiyun * as long as read prefetch is the only thing in
178*4882a593Smuzhiyun * o2micro_override, it's safe to call it from here
179*4882a593Smuzhiyun */
180*4882a593Smuzhiyun o2micro_override(socket);
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun #endif /* _LINUX_O2MICRO_H */
184