1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * MAX1600 PCMCIA power switch library
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016 Russell King
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #include <linux/device.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
10*4882a593Smuzhiyun #include <linux/slab.h>
11*4882a593Smuzhiyun #include "max1600.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static const char *max1600_gpio_name[2][MAX1600_GPIO_MAX] = {
14*4882a593Smuzhiyun { "a0vcc", "a1vcc", "a0vpp", "a1vpp" },
15*4882a593Smuzhiyun { "b0vcc", "b1vcc", "b0vpp", "b1vpp" },
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun
max1600_init(struct device * dev,struct max1600 ** ptr,unsigned int channel,unsigned int code)18*4882a593Smuzhiyun int max1600_init(struct device *dev, struct max1600 **ptr,
19*4882a593Smuzhiyun unsigned int channel, unsigned int code)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun struct max1600 *m;
22*4882a593Smuzhiyun int chan;
23*4882a593Smuzhiyun int i;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun switch (channel) {
26*4882a593Smuzhiyun case MAX1600_CHAN_A:
27*4882a593Smuzhiyun chan = 0;
28*4882a593Smuzhiyun break;
29*4882a593Smuzhiyun case MAX1600_CHAN_B:
30*4882a593Smuzhiyun chan = 1;
31*4882a593Smuzhiyun break;
32*4882a593Smuzhiyun default:
33*4882a593Smuzhiyun return -EINVAL;
34*4882a593Smuzhiyun }
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun if (code != MAX1600_CODE_LOW && code != MAX1600_CODE_HIGH)
37*4882a593Smuzhiyun return -EINVAL;
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun m = devm_kzalloc(dev, sizeof(*m), GFP_KERNEL);
40*4882a593Smuzhiyun if (!m)
41*4882a593Smuzhiyun return -ENOMEM;
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun m->dev = dev;
44*4882a593Smuzhiyun m->code = code;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun for (i = 0; i < MAX1600_GPIO_MAX; i++) {
47*4882a593Smuzhiyun const char *name;
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun name = max1600_gpio_name[chan][i];
50*4882a593Smuzhiyun if (i != MAX1600_GPIO_0VPP) {
51*4882a593Smuzhiyun m->gpio[i] = devm_gpiod_get(dev, name, GPIOD_OUT_LOW);
52*4882a593Smuzhiyun } else {
53*4882a593Smuzhiyun m->gpio[i] = devm_gpiod_get_optional(dev, name,
54*4882a593Smuzhiyun GPIOD_OUT_LOW);
55*4882a593Smuzhiyun if (!m->gpio[i])
56*4882a593Smuzhiyun break;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun if (IS_ERR(m->gpio[i]))
59*4882a593Smuzhiyun return PTR_ERR(m->gpio[i]);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun *ptr = m;
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun return 0;
65*4882a593Smuzhiyun }
66*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(max1600_init);
67*4882a593Smuzhiyun
max1600_configure(struct max1600 * m,unsigned int vcc,unsigned int vpp)68*4882a593Smuzhiyun int max1600_configure(struct max1600 *m, unsigned int vcc, unsigned int vpp)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun DECLARE_BITMAP(values, MAX1600_GPIO_MAX) = { 0, };
71*4882a593Smuzhiyun int n = MAX1600_GPIO_0VPP;
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun if (m->gpio[MAX1600_GPIO_0VPP]) {
74*4882a593Smuzhiyun if (vpp == 0) {
75*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_0VPP, values, 0);
76*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_1VPP, values, 0);
77*4882a593Smuzhiyun } else if (vpp == 120) {
78*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_0VPP, values, 0);
79*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_1VPP, values, 1);
80*4882a593Smuzhiyun } else if (vpp == vcc) {
81*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_0VPP, values, 1);
82*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_1VPP, values, 0);
83*4882a593Smuzhiyun } else {
84*4882a593Smuzhiyun dev_err(m->dev, "unrecognised Vpp %u.%uV\n",
85*4882a593Smuzhiyun vpp / 10, vpp % 10);
86*4882a593Smuzhiyun return -EINVAL;
87*4882a593Smuzhiyun }
88*4882a593Smuzhiyun n = MAX1600_GPIO_MAX;
89*4882a593Smuzhiyun } else if (vpp != vcc && vpp != 0) {
90*4882a593Smuzhiyun dev_err(m->dev, "no VPP control\n");
91*4882a593Smuzhiyun return -EINVAL;
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun if (vcc == 0) {
95*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_0VCC, values, 0);
96*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_1VCC, values, 0);
97*4882a593Smuzhiyun } else if (vcc == 33) { /* VY */
98*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_0VCC, values, 1);
99*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_1VCC, values, 0);
100*4882a593Smuzhiyun } else if (vcc == 50) { /* VX */
101*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_0VCC, values, 0);
102*4882a593Smuzhiyun __assign_bit(MAX1600_GPIO_1VCC, values, 1);
103*4882a593Smuzhiyun } else {
104*4882a593Smuzhiyun dev_err(m->dev, "unrecognised Vcc %u.%uV\n",
105*4882a593Smuzhiyun vcc / 10, vcc % 10);
106*4882a593Smuzhiyun return -EINVAL;
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun if (m->code == MAX1600_CODE_HIGH) {
110*4882a593Smuzhiyun /*
111*4882a593Smuzhiyun * Cirrus mode appears to be the same as Intel mode,
112*4882a593Smuzhiyun * except the VCC pins are inverted.
113*4882a593Smuzhiyun */
114*4882a593Smuzhiyun __change_bit(MAX1600_GPIO_0VCC, values);
115*4882a593Smuzhiyun __change_bit(MAX1600_GPIO_1VCC, values);
116*4882a593Smuzhiyun }
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun return gpiod_set_array_value_cansleep(n, m->gpio, NULL, values);
119*4882a593Smuzhiyun }
120*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(max1600_configure);
121*4882a593Smuzhiyun
122*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
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