1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * i82365.h 1.15 1999/10/25 20:03:34 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * The contents of this file are subject to the Mozilla Public License 5*4882a593Smuzhiyun * Version 1.1 (the "License"); you may not use this file except in 6*4882a593Smuzhiyun * compliance with the License. You may obtain a copy of the License 7*4882a593Smuzhiyun * at http://www.mozilla.org/MPL/ 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Software distributed under the License is distributed on an "AS IS" 10*4882a593Smuzhiyun * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See 11*4882a593Smuzhiyun * the License for the specific language governing rights and 12*4882a593Smuzhiyun * limitations under the License. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * The initial developer of the original code is David A. Hinds 15*4882a593Smuzhiyun * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds 16*4882a593Smuzhiyun * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Alternatively, the contents of this file may be used under the 19*4882a593Smuzhiyun * terms of the GNU General Public License version 2 (the "GPL"), in which 20*4882a593Smuzhiyun * case the provisions of the GPL are applicable instead of the 21*4882a593Smuzhiyun * above. If you wish to allow the use of your version of this file 22*4882a593Smuzhiyun * only under the terms of the GPL and not to allow others to use 23*4882a593Smuzhiyun * your version of this file under the MPL, indicate your decision by 24*4882a593Smuzhiyun * deleting the provisions above and replace them with the notice and 25*4882a593Smuzhiyun * other provisions required by the GPL. If you do not delete the 26*4882a593Smuzhiyun * provisions above, a recipient may use your version of this file 27*4882a593Smuzhiyun * under either the MPL or the GPL. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #ifndef _LINUX_I82365_H 31*4882a593Smuzhiyun #define _LINUX_I82365_H 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* register definitions for the Intel 82365SL PCMCIA controller */ 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Offsets for PCIC registers */ 36*4882a593Smuzhiyun #define I365_IDENT 0x00 /* Identification and revision */ 37*4882a593Smuzhiyun #define I365_STATUS 0x01 /* Interface status */ 38*4882a593Smuzhiyun #define I365_POWER 0x02 /* Power and RESETDRV control */ 39*4882a593Smuzhiyun #define I365_INTCTL 0x03 /* Interrupt and general control */ 40*4882a593Smuzhiyun #define I365_CSC 0x04 /* Card status change */ 41*4882a593Smuzhiyun #define I365_CSCINT 0x05 /* Card status change interrupt control */ 42*4882a593Smuzhiyun #define I365_ADDRWIN 0x06 /* Address window enable */ 43*4882a593Smuzhiyun #define I365_IOCTL 0x07 /* I/O control */ 44*4882a593Smuzhiyun #define I365_GENCTL 0x16 /* Card detect and general control */ 45*4882a593Smuzhiyun #define I365_GBLCTL 0x1E /* Global control register */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /* Offsets for I/O and memory window registers */ 48*4882a593Smuzhiyun #define I365_IO(map) (0x08+((map)<<2)) 49*4882a593Smuzhiyun #define I365_MEM(map) (0x10+((map)<<3)) 50*4882a593Smuzhiyun #define I365_W_START 0 51*4882a593Smuzhiyun #define I365_W_STOP 2 52*4882a593Smuzhiyun #define I365_W_OFF 4 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Flags for I365_STATUS */ 55*4882a593Smuzhiyun #define I365_CS_BVD1 0x01 56*4882a593Smuzhiyun #define I365_CS_STSCHG 0x01 57*4882a593Smuzhiyun #define I365_CS_BVD2 0x02 58*4882a593Smuzhiyun #define I365_CS_SPKR 0x02 59*4882a593Smuzhiyun #define I365_CS_DETECT 0x0C 60*4882a593Smuzhiyun #define I365_CS_WRPROT 0x10 61*4882a593Smuzhiyun #define I365_CS_READY 0x20 /* Inverted */ 62*4882a593Smuzhiyun #define I365_CS_POWERON 0x40 63*4882a593Smuzhiyun #define I365_CS_GPI 0x80 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun /* Flags for I365_POWER */ 66*4882a593Smuzhiyun #define I365_PWR_OFF 0x00 /* Turn off the socket */ 67*4882a593Smuzhiyun #define I365_PWR_OUT 0x80 /* Output enable */ 68*4882a593Smuzhiyun #define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */ 69*4882a593Smuzhiyun #define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */ 70*4882a593Smuzhiyun #define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */ 71*4882a593Smuzhiyun /* There are different layouts for B-step and DF-step chips: the B 72*4882a593Smuzhiyun step has independent Vpp1/Vpp2 control, and the DF step has only 73*4882a593Smuzhiyun Vpp1 control, plus 3V control */ 74*4882a593Smuzhiyun #define I365_VCC_5V 0x10 /* Vcc = 5.0v */ 75*4882a593Smuzhiyun #define I365_VCC_3V 0x18 /* Vcc = 3.3v */ 76*4882a593Smuzhiyun #define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */ 77*4882a593Smuzhiyun #define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */ 78*4882a593Smuzhiyun #define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */ 79*4882a593Smuzhiyun #define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */ 80*4882a593Smuzhiyun #define I365_VPP1_5V 0x01 /* Vpp1 = 5.0v */ 81*4882a593Smuzhiyun #define I365_VPP1_12V 0x02 /* Vpp1 = 12.0v */ 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* Flags for I365_INTCTL */ 84*4882a593Smuzhiyun #define I365_RING_ENA 0x80 85*4882a593Smuzhiyun #define I365_PC_RESET 0x40 86*4882a593Smuzhiyun #define I365_PC_IOCARD 0x20 87*4882a593Smuzhiyun #define I365_INTR_ENA 0x10 88*4882a593Smuzhiyun #define I365_IRQ_MASK 0x0F 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* Flags for I365_CSC and I365_CSCINT*/ 91*4882a593Smuzhiyun #define I365_CSC_BVD1 0x01 92*4882a593Smuzhiyun #define I365_CSC_STSCHG 0x01 93*4882a593Smuzhiyun #define I365_CSC_BVD2 0x02 94*4882a593Smuzhiyun #define I365_CSC_READY 0x04 95*4882a593Smuzhiyun #define I365_CSC_DETECT 0x08 96*4882a593Smuzhiyun #define I365_CSC_ANY 0x0F 97*4882a593Smuzhiyun #define I365_CSC_GPI 0x10 98*4882a593Smuzhiyun #define I365_CSC_IRQ_MASK 0xF0 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* Flags for I365_ADDRWIN */ 101*4882a593Smuzhiyun #define I365_ENA_IO(map) (0x40 << (map)) 102*4882a593Smuzhiyun #define I365_ENA_MEM(map) (0x01 << (map)) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Flags for I365_IOCTL */ 105*4882a593Smuzhiyun #define I365_IOCTL_MASK(map) (0x0F << (map<<2)) 106*4882a593Smuzhiyun #define I365_IOCTL_WAIT(map) (0x08 << (map<<2)) 107*4882a593Smuzhiyun #define I365_IOCTL_0WS(map) (0x04 << (map<<2)) 108*4882a593Smuzhiyun #define I365_IOCTL_IOCS16(map) (0x02 << (map<<2)) 109*4882a593Smuzhiyun #define I365_IOCTL_16BIT(map) (0x01 << (map<<2)) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun /* Flags for I365_GENCTL */ 112*4882a593Smuzhiyun #define I365_CTL_16DELAY 0x01 113*4882a593Smuzhiyun #define I365_CTL_RESET 0x02 114*4882a593Smuzhiyun #define I365_CTL_GPI_ENA 0x04 115*4882a593Smuzhiyun #define I365_CTL_GPI_CTL 0x08 116*4882a593Smuzhiyun #define I365_CTL_RESUME 0x10 117*4882a593Smuzhiyun #define I365_CTL_SW_IRQ 0x20 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* Flags for I365_GBLCTL */ 120*4882a593Smuzhiyun #define I365_GBL_PWRDOWN 0x01 121*4882a593Smuzhiyun #define I365_GBL_CSC_LEV 0x02 122*4882a593Smuzhiyun #define I365_GBL_WRBACK 0x04 123*4882a593Smuzhiyun #define I365_GBL_IRQ_0_LEV 0x08 124*4882a593Smuzhiyun #define I365_GBL_IRQ_1_LEV 0x10 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* Flags for memory window registers */ 127*4882a593Smuzhiyun #define I365_MEM_16BIT 0x8000 /* In memory start high byte */ 128*4882a593Smuzhiyun #define I365_MEM_0WS 0x4000 129*4882a593Smuzhiyun #define I365_MEM_WS1 0x8000 /* In memory stop high byte */ 130*4882a593Smuzhiyun #define I365_MEM_WS0 0x4000 131*4882a593Smuzhiyun #define I365_MEM_WRPROT 0x8000 /* In offset high byte */ 132*4882a593Smuzhiyun #define I365_MEM_REG 0x4000 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun #define I365_REG(slot, reg) (((slot) << 6) + reg) 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun #endif /* _LINUX_I82365_H */ 137