1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * cirrus.h 1.4 1999/10/25 20:03:34 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * The contents of this file are subject to the Mozilla Public License 5*4882a593Smuzhiyun * Version 1.1 (the "License"); you may not use this file except in 6*4882a593Smuzhiyun * compliance with the License. You may obtain a copy of the License 7*4882a593Smuzhiyun * at http://www.mozilla.org/MPL/ 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Software distributed under the License is distributed on an "AS IS" 10*4882a593Smuzhiyun * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See 11*4882a593Smuzhiyun * the License for the specific language governing rights and 12*4882a593Smuzhiyun * limitations under the License. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * The initial developer of the original code is David A. Hinds 15*4882a593Smuzhiyun * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds 16*4882a593Smuzhiyun * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. 17*4882a593Smuzhiyun * 18*4882a593Smuzhiyun * Alternatively, the contents of this file may be used under the 19*4882a593Smuzhiyun * terms of the GNU General Public License version 2 (the "GPL"), in which 20*4882a593Smuzhiyun * case the provisions of the GPL are applicable instead of the 21*4882a593Smuzhiyun * above. If you wish to allow the use of your version of this file 22*4882a593Smuzhiyun * only under the terms of the GPL and not to allow others to use 23*4882a593Smuzhiyun * your version of this file under the MPL, indicate your decision by 24*4882a593Smuzhiyun * deleting the provisions above and replace them with the notice and 25*4882a593Smuzhiyun * other provisions required by the GPL. If you do not delete the 26*4882a593Smuzhiyun * provisions above, a recipient may use your version of this file 27*4882a593Smuzhiyun * under either the MPL or the GPL. 28*4882a593Smuzhiyun */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #ifndef _LINUX_CIRRUS_H 31*4882a593Smuzhiyun #define _LINUX_CIRRUS_H 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define PD67_MISC_CTL_1 0x16 /* Misc control 1 */ 34*4882a593Smuzhiyun #define PD67_FIFO_CTL 0x17 /* FIFO control */ 35*4882a593Smuzhiyun #define PD67_MISC_CTL_2 0x1E /* Misc control 2 */ 36*4882a593Smuzhiyun #define PD67_CHIP_INFO 0x1f /* Chip information */ 37*4882a593Smuzhiyun #define PD67_ATA_CTL 0x026 /* 6730: ATA control */ 38*4882a593Smuzhiyun #define PD67_EXT_INDEX 0x2e /* Extension index */ 39*4882a593Smuzhiyun #define PD67_EXT_DATA 0x2f /* Extension data */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */ 42*4882a593Smuzhiyun #define PD67_DATA_MASK0 0x01 /* Data mask 0 */ 43*4882a593Smuzhiyun #define PD67_DATA_MASK1 0x02 /* Data mask 1 */ 44*4882a593Smuzhiyun #define PD67_DMA_CTL 0x03 /* DMA control */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */ 47*4882a593Smuzhiyun #define PD67_EXT_CTL_1 0x03 /* Extension control 1 */ 48*4882a593Smuzhiyun #define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */ 49*4882a593Smuzhiyun #define PD67_EXTERN_DATA 0x0a 50*4882a593Smuzhiyun #define PD67_MISC_CTL_3 0x25 51*4882a593Smuzhiyun #define PD67_SMB_PWR_CTL 0x26 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* I/O window address offset */ 54*4882a593Smuzhiyun #define PD67_IO_OFF(w) (0x36+((w)<<1)) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* Timing register sets */ 57*4882a593Smuzhiyun #define PD67_TIME_SETUP(n) (0x3a + 3*(n)) 58*4882a593Smuzhiyun #define PD67_TIME_CMD(n) (0x3b + 3*(n)) 59*4882a593Smuzhiyun #define PD67_TIME_RECOV(n) (0x3c + 3*(n)) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* Flags for PD67_MISC_CTL_1 */ 62*4882a593Smuzhiyun #define PD67_MC1_5V_DET 0x01 /* 5v detect */ 63*4882a593Smuzhiyun #define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */ 64*4882a593Smuzhiyun #define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */ 65*4882a593Smuzhiyun #define PD67_MC1_PULSE_MGMT 0x04 66*4882a593Smuzhiyun #define PD67_MC1_PULSE_IRQ 0x08 67*4882a593Smuzhiyun #define PD67_MC1_SPKR_ENA 0x10 68*4882a593Smuzhiyun #define PD67_MC1_INPACK_ENA 0x80 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Flags for PD67_FIFO_CTL */ 71*4882a593Smuzhiyun #define PD67_FIFO_EMPTY 0x80 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* Flags for PD67_MISC_CTL_2 */ 74*4882a593Smuzhiyun #define PD67_MC2_FREQ_BYPASS 0x01 75*4882a593Smuzhiyun #define PD67_MC2_DYNAMIC_MODE 0x02 76*4882a593Smuzhiyun #define PD67_MC2_SUSPEND 0x04 77*4882a593Smuzhiyun #define PD67_MC2_5V_CORE 0x08 78*4882a593Smuzhiyun #define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */ 79*4882a593Smuzhiyun #define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */ 80*4882a593Smuzhiyun #define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */ 81*4882a593Smuzhiyun #define PD67_MC2_DMA_MODE 0x40 82*4882a593Smuzhiyun #define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */ 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* Flags for PD67_CHIP_INFO */ 85*4882a593Smuzhiyun #define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */ 86*4882a593Smuzhiyun #define PD67_INFO_CHIP_ID 0xc0 87*4882a593Smuzhiyun #define PD67_INFO_REV 0x1c 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* Fields in PD67_TIME_* registers */ 90*4882a593Smuzhiyun #define PD67_TIME_SCALE 0xc0 91*4882a593Smuzhiyun #define PD67_TIME_SCALE_1 0x00 92*4882a593Smuzhiyun #define PD67_TIME_SCALE_16 0x40 93*4882a593Smuzhiyun #define PD67_TIME_SCALE_256 0x80 94*4882a593Smuzhiyun #define PD67_TIME_SCALE_4096 0xc0 95*4882a593Smuzhiyun #define PD67_TIME_MULT 0x3f 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* Fields in PD67_DMA_CTL */ 98*4882a593Smuzhiyun #define PD67_DMA_MODE 0xc0 99*4882a593Smuzhiyun #define PD67_DMA_OFF 0x00 100*4882a593Smuzhiyun #define PD67_DMA_DREQ_INPACK 0x40 101*4882a593Smuzhiyun #define PD67_DMA_DREQ_WP 0x80 102*4882a593Smuzhiyun #define PD67_DMA_DREQ_BVD2 0xc0 103*4882a593Smuzhiyun #define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /* Fields in PD67_EXT_CTL_1 */ 106*4882a593Smuzhiyun #define PD67_EC1_VCC_PWR_LOCK 0x01 107*4882a593Smuzhiyun #define PD67_EC1_AUTO_PWR_CLEAR 0x02 108*4882a593Smuzhiyun #define PD67_EC1_LED_ENA 0x04 109*4882a593Smuzhiyun #define PD67_EC1_INV_CARD_IRQ 0x08 110*4882a593Smuzhiyun #define PD67_EC1_INV_MGMT_IRQ 0x10 111*4882a593Smuzhiyun #define PD67_EC1_PULLUP_CTL 0x20 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* Fields in PD67_MISC_CTL_3 */ 114*4882a593Smuzhiyun #define PD67_MC3_IRQ_MASK 0x03 115*4882a593Smuzhiyun #define PD67_MC3_IRQ_PCPCI 0x00 116*4882a593Smuzhiyun #define PD67_MC3_IRQ_EXTERN 0x01 117*4882a593Smuzhiyun #define PD67_MC3_IRQ_PCIWAY 0x02 118*4882a593Smuzhiyun #define PD67_MC3_IRQ_PCI 0x03 119*4882a593Smuzhiyun #define PD67_MC3_PWR_MASK 0x0c 120*4882a593Smuzhiyun #define PD67_MC3_PWR_SERIAL 0x00 121*4882a593Smuzhiyun #define PD67_MC3_PWR_TI2202 0x08 122*4882a593Smuzhiyun #define PD67_MC3_PWR_SMB 0x0c 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */ 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */ 127*4882a593Smuzhiyun #define PD68_EXT_CTL_2 0x0b 128*4882a593Smuzhiyun #define PD68_PCI_SPACE 0x22 129*4882a593Smuzhiyun #define PD68_PCCARD_SPACE 0x23 130*4882a593Smuzhiyun #define PD68_WINDOW_TYPE 0x24 131*4882a593Smuzhiyun #define PD68_EXT_CSC 0x2e 132*4882a593Smuzhiyun #define PD68_MISC_CTL_4 0x2f 133*4882a593Smuzhiyun #define PD68_MISC_CTL_5 0x30 134*4882a593Smuzhiyun #define PD68_MISC_CTL_6 0x31 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* Extra flags in PD67_MISC_CTL_3 */ 137*4882a593Smuzhiyun #define PD68_MC3_HW_SUSP 0x10 138*4882a593Smuzhiyun #define PD68_MC3_MM_EXPAND 0x40 139*4882a593Smuzhiyun #define PD68_MC3_MM_ARM 0x80 140*4882a593Smuzhiyun 141*4882a593Smuzhiyun /* Bridge Control Register */ 142*4882a593Smuzhiyun #define PD6832_BCR_MGMT_IRQ_ENA 0x0800 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun /* Socket Number Register */ 145*4882a593Smuzhiyun #define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */ 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun #endif /* _LINUX_CIRRUS_H */ 148