1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * cardbus.c -- 16-bit PCMCIA core support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * The initial developer of the original code is David A. Hinds
6*4882a593Smuzhiyun * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds
7*4882a593Smuzhiyun * are Copyright (C) 1999 David A. Hinds. All Rights Reserved.
8*4882a593Smuzhiyun *
9*4882a593Smuzhiyun * (C) 1999 David A. Hinds
10*4882a593Smuzhiyun */
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun /*
13*4882a593Smuzhiyun * Cardbus handling has been re-written to be more of a PCI bridge thing,
14*4882a593Smuzhiyun * and the PCI code basically does all the resource handling.
15*4882a593Smuzhiyun *
16*4882a593Smuzhiyun * Linus, Jan 2000
17*4882a593Smuzhiyun */
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/kernel.h>
21*4882a593Smuzhiyun #include <linux/module.h>
22*4882a593Smuzhiyun #include <linux/pci.h>
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #include <pcmcia/ss.h>
25*4882a593Smuzhiyun #include <pcmcia/cistpl.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "cs_internal.h"
28*4882a593Smuzhiyun
cardbus_config_irq_and_cls(struct pci_bus * bus,int irq)29*4882a593Smuzhiyun static void cardbus_config_irq_and_cls(struct pci_bus *bus, int irq)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun struct pci_dev *dev;
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun list_for_each_entry(dev, &bus->devices, bus_list) {
34*4882a593Smuzhiyun u8 irq_pin;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun /*
37*4882a593Smuzhiyun * Since there is only one interrupt available to
38*4882a593Smuzhiyun * CardBus devices, all devices downstream of this
39*4882a593Smuzhiyun * device must be using this IRQ.
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq_pin);
42*4882a593Smuzhiyun if (irq_pin) {
43*4882a593Smuzhiyun dev->irq = irq;
44*4882a593Smuzhiyun pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun /*
48*4882a593Smuzhiyun * Some controllers transfer very slowly with 0 CLS.
49*4882a593Smuzhiyun * Configure it. This may fail as CLS configuration
50*4882a593Smuzhiyun * is mandatory only for MWI.
51*4882a593Smuzhiyun */
52*4882a593Smuzhiyun pci_set_cacheline_size(dev);
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun if (dev->subordinate)
55*4882a593Smuzhiyun cardbus_config_irq_and_cls(dev->subordinate, irq);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun /**
60*4882a593Smuzhiyun * cb_alloc() - add CardBus device
61*4882a593Smuzhiyun * @s: the pcmcia_socket where the CardBus device is located
62*4882a593Smuzhiyun *
63*4882a593Smuzhiyun * cb_alloc() allocates the kernel data structures for a Cardbus device
64*4882a593Smuzhiyun * and handles the lowest level PCI device setup issues.
65*4882a593Smuzhiyun */
cb_alloc(struct pcmcia_socket * s)66*4882a593Smuzhiyun int __ref cb_alloc(struct pcmcia_socket *s)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct pci_bus *bus = s->cb_dev->subordinate;
69*4882a593Smuzhiyun struct pci_dev *dev;
70*4882a593Smuzhiyun unsigned int max, pass;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun pci_lock_rescan_remove();
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun s->functions = pci_scan_slot(bus, PCI_DEVFN(0, 0));
75*4882a593Smuzhiyun pci_fixup_cardbus(bus);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun max = bus->busn_res.start;
78*4882a593Smuzhiyun for (pass = 0; pass < 2; pass++)
79*4882a593Smuzhiyun for_each_pci_bridge(dev, bus)
80*4882a593Smuzhiyun max = pci_scan_bridge(bus, dev, max, pass);
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun /*
83*4882a593Smuzhiyun * Size all resources below the CardBus controller.
84*4882a593Smuzhiyun */
85*4882a593Smuzhiyun pci_bus_size_bridges(bus);
86*4882a593Smuzhiyun pci_bus_assign_resources(bus);
87*4882a593Smuzhiyun cardbus_config_irq_and_cls(bus, s->pci_irq);
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun /* socket specific tune function */
90*4882a593Smuzhiyun if (s->tune_bridge)
91*4882a593Smuzhiyun s->tune_bridge(s, bus);
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun pci_bus_add_devices(bus);
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun pci_unlock_rescan_remove();
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun /**
100*4882a593Smuzhiyun * cb_free() - remove CardBus device
101*4882a593Smuzhiyun * @s: the pcmcia_socket where the CardBus device was located
102*4882a593Smuzhiyun *
103*4882a593Smuzhiyun * cb_free() handles the lowest level PCI device cleanup.
104*4882a593Smuzhiyun */
cb_free(struct pcmcia_socket * s)105*4882a593Smuzhiyun void cb_free(struct pcmcia_socket *s)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun struct pci_dev *bridge, *dev, *tmp;
108*4882a593Smuzhiyun struct pci_bus *bus;
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun bridge = s->cb_dev;
111*4882a593Smuzhiyun if (!bridge)
112*4882a593Smuzhiyun return;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun bus = bridge->subordinate;
115*4882a593Smuzhiyun if (!bus)
116*4882a593Smuzhiyun return;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun pci_lock_rescan_remove();
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun list_for_each_entry_safe(dev, tmp, &bus->devices, bus_list)
121*4882a593Smuzhiyun pci_stop_and_remove_bus_device(dev);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun pci_unlock_rescan_remove();
124*4882a593Smuzhiyun }
125