1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * PCI VPD support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2010 Broadcom Corporation.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/pci.h>
9*4882a593Smuzhiyun #include <linux/delay.h>
10*4882a593Smuzhiyun #include <linux/export.h>
11*4882a593Smuzhiyun #include <linux/sched/signal.h>
12*4882a593Smuzhiyun #include "pci.h"
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun /* VPD access through PCI 2.2+ VPD capability */
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct pci_vpd_ops {
17*4882a593Smuzhiyun ssize_t (*read)(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
18*4882a593Smuzhiyun ssize_t (*write)(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
19*4882a593Smuzhiyun int (*set_size)(struct pci_dev *dev, size_t len);
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct pci_vpd {
23*4882a593Smuzhiyun const struct pci_vpd_ops *ops;
24*4882a593Smuzhiyun struct bin_attribute *attr; /* Descriptor for sysfs VPD entry */
25*4882a593Smuzhiyun struct mutex lock;
26*4882a593Smuzhiyun unsigned int len;
27*4882a593Smuzhiyun u16 flag;
28*4882a593Smuzhiyun u8 cap;
29*4882a593Smuzhiyun unsigned int busy:1;
30*4882a593Smuzhiyun unsigned int valid:1;
31*4882a593Smuzhiyun };
32*4882a593Smuzhiyun
33*4882a593Smuzhiyun /**
34*4882a593Smuzhiyun * pci_read_vpd - Read one entry from Vital Product Data
35*4882a593Smuzhiyun * @dev: pci device struct
36*4882a593Smuzhiyun * @pos: offset in vpd space
37*4882a593Smuzhiyun * @count: number of bytes to read
38*4882a593Smuzhiyun * @buf: pointer to where to store result
39*4882a593Smuzhiyun */
pci_read_vpd(struct pci_dev * dev,loff_t pos,size_t count,void * buf)40*4882a593Smuzhiyun ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun if (!dev->vpd || !dev->vpd->ops)
43*4882a593Smuzhiyun return -ENODEV;
44*4882a593Smuzhiyun return dev->vpd->ops->read(dev, pos, count, buf);
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun EXPORT_SYMBOL(pci_read_vpd);
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun /**
49*4882a593Smuzhiyun * pci_write_vpd - Write entry to Vital Product Data
50*4882a593Smuzhiyun * @dev: pci device struct
51*4882a593Smuzhiyun * @pos: offset in vpd space
52*4882a593Smuzhiyun * @count: number of bytes to write
53*4882a593Smuzhiyun * @buf: buffer containing write data
54*4882a593Smuzhiyun */
pci_write_vpd(struct pci_dev * dev,loff_t pos,size_t count,const void * buf)55*4882a593Smuzhiyun ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf)
56*4882a593Smuzhiyun {
57*4882a593Smuzhiyun if (!dev->vpd || !dev->vpd->ops)
58*4882a593Smuzhiyun return -ENODEV;
59*4882a593Smuzhiyun return dev->vpd->ops->write(dev, pos, count, buf);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun EXPORT_SYMBOL(pci_write_vpd);
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /**
64*4882a593Smuzhiyun * pci_set_vpd_size - Set size of Vital Product Data space
65*4882a593Smuzhiyun * @dev: pci device struct
66*4882a593Smuzhiyun * @len: size of vpd space
67*4882a593Smuzhiyun */
pci_set_vpd_size(struct pci_dev * dev,size_t len)68*4882a593Smuzhiyun int pci_set_vpd_size(struct pci_dev *dev, size_t len)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun if (!dev->vpd || !dev->vpd->ops)
71*4882a593Smuzhiyun return -ENODEV;
72*4882a593Smuzhiyun return dev->vpd->ops->set_size(dev, len);
73*4882a593Smuzhiyun }
74*4882a593Smuzhiyun EXPORT_SYMBOL(pci_set_vpd_size);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define PCI_VPD_MAX_SIZE (PCI_VPD_ADDR_MASK + 1)
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun /**
79*4882a593Smuzhiyun * pci_vpd_size - determine actual size of Vital Product Data
80*4882a593Smuzhiyun * @dev: pci device struct
81*4882a593Smuzhiyun * @old_size: current assumed size, also maximum allowed size
82*4882a593Smuzhiyun */
pci_vpd_size(struct pci_dev * dev,size_t old_size)83*4882a593Smuzhiyun static size_t pci_vpd_size(struct pci_dev *dev, size_t old_size)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun size_t off = 0;
86*4882a593Smuzhiyun unsigned char header[1+2]; /* 1 byte tag, 2 bytes length */
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun while (off < old_size &&
89*4882a593Smuzhiyun pci_read_vpd(dev, off, 1, header) == 1) {
90*4882a593Smuzhiyun unsigned char tag;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (header[0] & PCI_VPD_LRDT) {
93*4882a593Smuzhiyun /* Large Resource Data Type Tag */
94*4882a593Smuzhiyun tag = pci_vpd_lrdt_tag(header);
95*4882a593Smuzhiyun /* Only read length from known tag items */
96*4882a593Smuzhiyun if ((tag == PCI_VPD_LTIN_ID_STRING) ||
97*4882a593Smuzhiyun (tag == PCI_VPD_LTIN_RO_DATA) ||
98*4882a593Smuzhiyun (tag == PCI_VPD_LTIN_RW_DATA)) {
99*4882a593Smuzhiyun if (pci_read_vpd(dev, off+1, 2,
100*4882a593Smuzhiyun &header[1]) != 2) {
101*4882a593Smuzhiyun pci_warn(dev, "invalid large VPD tag %02x size at offset %zu",
102*4882a593Smuzhiyun tag, off + 1);
103*4882a593Smuzhiyun return 0;
104*4882a593Smuzhiyun }
105*4882a593Smuzhiyun off += PCI_VPD_LRDT_TAG_SIZE +
106*4882a593Smuzhiyun pci_vpd_lrdt_size(header);
107*4882a593Smuzhiyun }
108*4882a593Smuzhiyun } else {
109*4882a593Smuzhiyun /* Short Resource Data Type Tag */
110*4882a593Smuzhiyun off += PCI_VPD_SRDT_TAG_SIZE +
111*4882a593Smuzhiyun pci_vpd_srdt_size(header);
112*4882a593Smuzhiyun tag = pci_vpd_srdt_tag(header);
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun
115*4882a593Smuzhiyun if (tag == PCI_VPD_STIN_END) /* End tag descriptor */
116*4882a593Smuzhiyun return off;
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun if ((tag != PCI_VPD_LTIN_ID_STRING) &&
119*4882a593Smuzhiyun (tag != PCI_VPD_LTIN_RO_DATA) &&
120*4882a593Smuzhiyun (tag != PCI_VPD_LTIN_RW_DATA)) {
121*4882a593Smuzhiyun pci_warn(dev, "invalid %s VPD tag %02x at offset %zu",
122*4882a593Smuzhiyun (header[0] & PCI_VPD_LRDT) ? "large" : "short",
123*4882a593Smuzhiyun tag, off);
124*4882a593Smuzhiyun return 0;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun }
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
130*4882a593Smuzhiyun /*
131*4882a593Smuzhiyun * Wait for last operation to complete.
132*4882a593Smuzhiyun * This code has to spin since there is no other notification from the PCI
133*4882a593Smuzhiyun * hardware. Since the VPD is often implemented by serial attachment to an
134*4882a593Smuzhiyun * EEPROM, it may take many milliseconds to complete.
135*4882a593Smuzhiyun *
136*4882a593Smuzhiyun * Returns 0 on success, negative values indicate error.
137*4882a593Smuzhiyun */
pci_vpd_wait(struct pci_dev * dev)138*4882a593Smuzhiyun static int pci_vpd_wait(struct pci_dev *dev)
139*4882a593Smuzhiyun {
140*4882a593Smuzhiyun struct pci_vpd *vpd = dev->vpd;
141*4882a593Smuzhiyun unsigned long timeout = jiffies + msecs_to_jiffies(125);
142*4882a593Smuzhiyun unsigned long max_sleep = 16;
143*4882a593Smuzhiyun u16 status;
144*4882a593Smuzhiyun int ret;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (!vpd->busy)
147*4882a593Smuzhiyun return 0;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun do {
150*4882a593Smuzhiyun ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
151*4882a593Smuzhiyun &status);
152*4882a593Smuzhiyun if (ret < 0)
153*4882a593Smuzhiyun return ret;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
156*4882a593Smuzhiyun vpd->busy = 0;
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (fatal_signal_pending(current))
161*4882a593Smuzhiyun return -EINTR;
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun if (time_after(jiffies, timeout))
164*4882a593Smuzhiyun break;
165*4882a593Smuzhiyun
166*4882a593Smuzhiyun usleep_range(10, max_sleep);
167*4882a593Smuzhiyun if (max_sleep < 1024)
168*4882a593Smuzhiyun max_sleep *= 2;
169*4882a593Smuzhiyun } while (true);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun pci_warn(dev, "VPD access failed. This is likely a firmware bug on this device. Contact the card vendor for a firmware update\n");
172*4882a593Smuzhiyun return -ETIMEDOUT;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
pci_vpd_read(struct pci_dev * dev,loff_t pos,size_t count,void * arg)175*4882a593Smuzhiyun static ssize_t pci_vpd_read(struct pci_dev *dev, loff_t pos, size_t count,
176*4882a593Smuzhiyun void *arg)
177*4882a593Smuzhiyun {
178*4882a593Smuzhiyun struct pci_vpd *vpd = dev->vpd;
179*4882a593Smuzhiyun int ret;
180*4882a593Smuzhiyun loff_t end = pos + count;
181*4882a593Smuzhiyun u8 *buf = arg;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun if (pos < 0)
184*4882a593Smuzhiyun return -EINVAL;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun if (!vpd->valid) {
187*4882a593Smuzhiyun vpd->valid = 1;
188*4882a593Smuzhiyun vpd->len = pci_vpd_size(dev, vpd->len);
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun if (vpd->len == 0)
192*4882a593Smuzhiyun return -EIO;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun if (pos > vpd->len)
195*4882a593Smuzhiyun return 0;
196*4882a593Smuzhiyun
197*4882a593Smuzhiyun if (end > vpd->len) {
198*4882a593Smuzhiyun end = vpd->len;
199*4882a593Smuzhiyun count = end - pos;
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
202*4882a593Smuzhiyun if (mutex_lock_killable(&vpd->lock))
203*4882a593Smuzhiyun return -EINTR;
204*4882a593Smuzhiyun
205*4882a593Smuzhiyun ret = pci_vpd_wait(dev);
206*4882a593Smuzhiyun if (ret < 0)
207*4882a593Smuzhiyun goto out;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun while (pos < end) {
210*4882a593Smuzhiyun u32 val;
211*4882a593Smuzhiyun unsigned int i, skip;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
214*4882a593Smuzhiyun pos & ~3);
215*4882a593Smuzhiyun if (ret < 0)
216*4882a593Smuzhiyun break;
217*4882a593Smuzhiyun vpd->busy = 1;
218*4882a593Smuzhiyun vpd->flag = PCI_VPD_ADDR_F;
219*4882a593Smuzhiyun ret = pci_vpd_wait(dev);
220*4882a593Smuzhiyun if (ret < 0)
221*4882a593Smuzhiyun break;
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun ret = pci_user_read_config_dword(dev, vpd->cap + PCI_VPD_DATA, &val);
224*4882a593Smuzhiyun if (ret < 0)
225*4882a593Smuzhiyun break;
226*4882a593Smuzhiyun
227*4882a593Smuzhiyun skip = pos & 3;
228*4882a593Smuzhiyun for (i = 0; i < sizeof(u32); i++) {
229*4882a593Smuzhiyun if (i >= skip) {
230*4882a593Smuzhiyun *buf++ = val;
231*4882a593Smuzhiyun if (++pos == end)
232*4882a593Smuzhiyun break;
233*4882a593Smuzhiyun }
234*4882a593Smuzhiyun val >>= 8;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun }
237*4882a593Smuzhiyun out:
238*4882a593Smuzhiyun mutex_unlock(&vpd->lock);
239*4882a593Smuzhiyun return ret ? ret : count;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
pci_vpd_write(struct pci_dev * dev,loff_t pos,size_t count,const void * arg)242*4882a593Smuzhiyun static ssize_t pci_vpd_write(struct pci_dev *dev, loff_t pos, size_t count,
243*4882a593Smuzhiyun const void *arg)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun struct pci_vpd *vpd = dev->vpd;
246*4882a593Smuzhiyun const u8 *buf = arg;
247*4882a593Smuzhiyun loff_t end = pos + count;
248*4882a593Smuzhiyun int ret = 0;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun if (pos < 0 || (pos & 3) || (count & 3))
251*4882a593Smuzhiyun return -EINVAL;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun if (!vpd->valid) {
254*4882a593Smuzhiyun vpd->valid = 1;
255*4882a593Smuzhiyun vpd->len = pci_vpd_size(dev, vpd->len);
256*4882a593Smuzhiyun }
257*4882a593Smuzhiyun
258*4882a593Smuzhiyun if (vpd->len == 0)
259*4882a593Smuzhiyun return -EIO;
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun if (end > vpd->len)
262*4882a593Smuzhiyun return -EINVAL;
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun if (mutex_lock_killable(&vpd->lock))
265*4882a593Smuzhiyun return -EINTR;
266*4882a593Smuzhiyun
267*4882a593Smuzhiyun ret = pci_vpd_wait(dev);
268*4882a593Smuzhiyun if (ret < 0)
269*4882a593Smuzhiyun goto out;
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun while (pos < end) {
272*4882a593Smuzhiyun u32 val;
273*4882a593Smuzhiyun
274*4882a593Smuzhiyun val = *buf++;
275*4882a593Smuzhiyun val |= *buf++ << 8;
276*4882a593Smuzhiyun val |= *buf++ << 16;
277*4882a593Smuzhiyun val |= *buf++ << 24;
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun ret = pci_user_write_config_dword(dev, vpd->cap + PCI_VPD_DATA, val);
280*4882a593Smuzhiyun if (ret < 0)
281*4882a593Smuzhiyun break;
282*4882a593Smuzhiyun ret = pci_user_write_config_word(dev, vpd->cap + PCI_VPD_ADDR,
283*4882a593Smuzhiyun pos | PCI_VPD_ADDR_F);
284*4882a593Smuzhiyun if (ret < 0)
285*4882a593Smuzhiyun break;
286*4882a593Smuzhiyun
287*4882a593Smuzhiyun vpd->busy = 1;
288*4882a593Smuzhiyun vpd->flag = 0;
289*4882a593Smuzhiyun ret = pci_vpd_wait(dev);
290*4882a593Smuzhiyun if (ret < 0)
291*4882a593Smuzhiyun break;
292*4882a593Smuzhiyun
293*4882a593Smuzhiyun pos += sizeof(u32);
294*4882a593Smuzhiyun }
295*4882a593Smuzhiyun out:
296*4882a593Smuzhiyun mutex_unlock(&vpd->lock);
297*4882a593Smuzhiyun return ret ? ret : count;
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
pci_vpd_set_size(struct pci_dev * dev,size_t len)300*4882a593Smuzhiyun static int pci_vpd_set_size(struct pci_dev *dev, size_t len)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct pci_vpd *vpd = dev->vpd;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun if (len == 0 || len > PCI_VPD_MAX_SIZE)
305*4882a593Smuzhiyun return -EIO;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun vpd->valid = 1;
308*4882a593Smuzhiyun vpd->len = len;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun return 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun static const struct pci_vpd_ops pci_vpd_ops = {
314*4882a593Smuzhiyun .read = pci_vpd_read,
315*4882a593Smuzhiyun .write = pci_vpd_write,
316*4882a593Smuzhiyun .set_size = pci_vpd_set_size,
317*4882a593Smuzhiyun };
318*4882a593Smuzhiyun
pci_vpd_f0_read(struct pci_dev * dev,loff_t pos,size_t count,void * arg)319*4882a593Smuzhiyun static ssize_t pci_vpd_f0_read(struct pci_dev *dev, loff_t pos, size_t count,
320*4882a593Smuzhiyun void *arg)
321*4882a593Smuzhiyun {
322*4882a593Smuzhiyun struct pci_dev *tdev = pci_get_slot(dev->bus,
323*4882a593Smuzhiyun PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
324*4882a593Smuzhiyun ssize_t ret;
325*4882a593Smuzhiyun
326*4882a593Smuzhiyun if (!tdev)
327*4882a593Smuzhiyun return -ENODEV;
328*4882a593Smuzhiyun
329*4882a593Smuzhiyun ret = pci_read_vpd(tdev, pos, count, arg);
330*4882a593Smuzhiyun pci_dev_put(tdev);
331*4882a593Smuzhiyun return ret;
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun
pci_vpd_f0_write(struct pci_dev * dev,loff_t pos,size_t count,const void * arg)334*4882a593Smuzhiyun static ssize_t pci_vpd_f0_write(struct pci_dev *dev, loff_t pos, size_t count,
335*4882a593Smuzhiyun const void *arg)
336*4882a593Smuzhiyun {
337*4882a593Smuzhiyun struct pci_dev *tdev = pci_get_slot(dev->bus,
338*4882a593Smuzhiyun PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
339*4882a593Smuzhiyun ssize_t ret;
340*4882a593Smuzhiyun
341*4882a593Smuzhiyun if (!tdev)
342*4882a593Smuzhiyun return -ENODEV;
343*4882a593Smuzhiyun
344*4882a593Smuzhiyun ret = pci_write_vpd(tdev, pos, count, arg);
345*4882a593Smuzhiyun pci_dev_put(tdev);
346*4882a593Smuzhiyun return ret;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
pci_vpd_f0_set_size(struct pci_dev * dev,size_t len)349*4882a593Smuzhiyun static int pci_vpd_f0_set_size(struct pci_dev *dev, size_t len)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun struct pci_dev *tdev = pci_get_slot(dev->bus,
352*4882a593Smuzhiyun PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
353*4882a593Smuzhiyun int ret;
354*4882a593Smuzhiyun
355*4882a593Smuzhiyun if (!tdev)
356*4882a593Smuzhiyun return -ENODEV;
357*4882a593Smuzhiyun
358*4882a593Smuzhiyun ret = pci_set_vpd_size(tdev, len);
359*4882a593Smuzhiyun pci_dev_put(tdev);
360*4882a593Smuzhiyun return ret;
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
363*4882a593Smuzhiyun static const struct pci_vpd_ops pci_vpd_f0_ops = {
364*4882a593Smuzhiyun .read = pci_vpd_f0_read,
365*4882a593Smuzhiyun .write = pci_vpd_f0_write,
366*4882a593Smuzhiyun .set_size = pci_vpd_f0_set_size,
367*4882a593Smuzhiyun };
368*4882a593Smuzhiyun
pci_vpd_init(struct pci_dev * dev)369*4882a593Smuzhiyun int pci_vpd_init(struct pci_dev *dev)
370*4882a593Smuzhiyun {
371*4882a593Smuzhiyun struct pci_vpd *vpd;
372*4882a593Smuzhiyun u8 cap;
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun cap = pci_find_capability(dev, PCI_CAP_ID_VPD);
375*4882a593Smuzhiyun if (!cap)
376*4882a593Smuzhiyun return -ENODEV;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun vpd = kzalloc(sizeof(*vpd), GFP_ATOMIC);
379*4882a593Smuzhiyun if (!vpd)
380*4882a593Smuzhiyun return -ENOMEM;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun vpd->len = PCI_VPD_MAX_SIZE;
383*4882a593Smuzhiyun if (dev->dev_flags & PCI_DEV_FLAGS_VPD_REF_F0)
384*4882a593Smuzhiyun vpd->ops = &pci_vpd_f0_ops;
385*4882a593Smuzhiyun else
386*4882a593Smuzhiyun vpd->ops = &pci_vpd_ops;
387*4882a593Smuzhiyun mutex_init(&vpd->lock);
388*4882a593Smuzhiyun vpd->cap = cap;
389*4882a593Smuzhiyun vpd->busy = 0;
390*4882a593Smuzhiyun vpd->valid = 0;
391*4882a593Smuzhiyun dev->vpd = vpd;
392*4882a593Smuzhiyun return 0;
393*4882a593Smuzhiyun }
394*4882a593Smuzhiyun
pci_vpd_release(struct pci_dev * dev)395*4882a593Smuzhiyun void pci_vpd_release(struct pci_dev *dev)
396*4882a593Smuzhiyun {
397*4882a593Smuzhiyun kfree(dev->vpd);
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
read_vpd_attr(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)400*4882a593Smuzhiyun static ssize_t read_vpd_attr(struct file *filp, struct kobject *kobj,
401*4882a593Smuzhiyun struct bin_attribute *bin_attr, char *buf,
402*4882a593Smuzhiyun loff_t off, size_t count)
403*4882a593Smuzhiyun {
404*4882a593Smuzhiyun struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
405*4882a593Smuzhiyun
406*4882a593Smuzhiyun if (bin_attr->size > 0) {
407*4882a593Smuzhiyun if (off > bin_attr->size)
408*4882a593Smuzhiyun count = 0;
409*4882a593Smuzhiyun else if (count > bin_attr->size - off)
410*4882a593Smuzhiyun count = bin_attr->size - off;
411*4882a593Smuzhiyun }
412*4882a593Smuzhiyun
413*4882a593Smuzhiyun return pci_read_vpd(dev, off, count, buf);
414*4882a593Smuzhiyun }
415*4882a593Smuzhiyun
write_vpd_attr(struct file * filp,struct kobject * kobj,struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)416*4882a593Smuzhiyun static ssize_t write_vpd_attr(struct file *filp, struct kobject *kobj,
417*4882a593Smuzhiyun struct bin_attribute *bin_attr, char *buf,
418*4882a593Smuzhiyun loff_t off, size_t count)
419*4882a593Smuzhiyun {
420*4882a593Smuzhiyun struct pci_dev *dev = to_pci_dev(kobj_to_dev(kobj));
421*4882a593Smuzhiyun
422*4882a593Smuzhiyun if (bin_attr->size > 0) {
423*4882a593Smuzhiyun if (off > bin_attr->size)
424*4882a593Smuzhiyun count = 0;
425*4882a593Smuzhiyun else if (count > bin_attr->size - off)
426*4882a593Smuzhiyun count = bin_attr->size - off;
427*4882a593Smuzhiyun }
428*4882a593Smuzhiyun
429*4882a593Smuzhiyun return pci_write_vpd(dev, off, count, buf);
430*4882a593Smuzhiyun }
431*4882a593Smuzhiyun
pcie_vpd_create_sysfs_dev_files(struct pci_dev * dev)432*4882a593Smuzhiyun void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev)
433*4882a593Smuzhiyun {
434*4882a593Smuzhiyun int retval;
435*4882a593Smuzhiyun struct bin_attribute *attr;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun if (!dev->vpd)
438*4882a593Smuzhiyun return;
439*4882a593Smuzhiyun
440*4882a593Smuzhiyun attr = kzalloc(sizeof(*attr), GFP_ATOMIC);
441*4882a593Smuzhiyun if (!attr)
442*4882a593Smuzhiyun return;
443*4882a593Smuzhiyun
444*4882a593Smuzhiyun sysfs_bin_attr_init(attr);
445*4882a593Smuzhiyun attr->size = 0;
446*4882a593Smuzhiyun attr->attr.name = "vpd";
447*4882a593Smuzhiyun attr->attr.mode = S_IRUSR | S_IWUSR;
448*4882a593Smuzhiyun attr->read = read_vpd_attr;
449*4882a593Smuzhiyun attr->write = write_vpd_attr;
450*4882a593Smuzhiyun retval = sysfs_create_bin_file(&dev->dev.kobj, attr);
451*4882a593Smuzhiyun if (retval) {
452*4882a593Smuzhiyun kfree(attr);
453*4882a593Smuzhiyun return;
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun
456*4882a593Smuzhiyun dev->vpd->attr = attr;
457*4882a593Smuzhiyun }
458*4882a593Smuzhiyun
pcie_vpd_remove_sysfs_dev_files(struct pci_dev * dev)459*4882a593Smuzhiyun void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev)
460*4882a593Smuzhiyun {
461*4882a593Smuzhiyun if (dev->vpd && dev->vpd->attr) {
462*4882a593Smuzhiyun sysfs_remove_bin_file(&dev->dev.kobj, dev->vpd->attr);
463*4882a593Smuzhiyun kfree(dev->vpd->attr);
464*4882a593Smuzhiyun }
465*4882a593Smuzhiyun }
466*4882a593Smuzhiyun
pci_vpd_find_tag(const u8 * buf,unsigned int off,unsigned int len,u8 rdt)467*4882a593Smuzhiyun int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt)
468*4882a593Smuzhiyun {
469*4882a593Smuzhiyun int i;
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun for (i = off; i < len; ) {
472*4882a593Smuzhiyun u8 val = buf[i];
473*4882a593Smuzhiyun
474*4882a593Smuzhiyun if (val & PCI_VPD_LRDT) {
475*4882a593Smuzhiyun /* Don't return success of the tag isn't complete */
476*4882a593Smuzhiyun if (i + PCI_VPD_LRDT_TAG_SIZE > len)
477*4882a593Smuzhiyun break;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun if (val == rdt)
480*4882a593Smuzhiyun return i;
481*4882a593Smuzhiyun
482*4882a593Smuzhiyun i += PCI_VPD_LRDT_TAG_SIZE +
483*4882a593Smuzhiyun pci_vpd_lrdt_size(&buf[i]);
484*4882a593Smuzhiyun } else {
485*4882a593Smuzhiyun u8 tag = val & ~PCI_VPD_SRDT_LEN_MASK;
486*4882a593Smuzhiyun
487*4882a593Smuzhiyun if (tag == rdt)
488*4882a593Smuzhiyun return i;
489*4882a593Smuzhiyun
490*4882a593Smuzhiyun if (tag == PCI_VPD_SRDT_END)
491*4882a593Smuzhiyun break;
492*4882a593Smuzhiyun
493*4882a593Smuzhiyun i += PCI_VPD_SRDT_TAG_SIZE +
494*4882a593Smuzhiyun pci_vpd_srdt_size(&buf[i]);
495*4882a593Smuzhiyun }
496*4882a593Smuzhiyun }
497*4882a593Smuzhiyun
498*4882a593Smuzhiyun return -ENOENT;
499*4882a593Smuzhiyun }
500*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(pci_vpd_find_tag);
501*4882a593Smuzhiyun
pci_vpd_find_info_keyword(const u8 * buf,unsigned int off,unsigned int len,const char * kw)502*4882a593Smuzhiyun int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
503*4882a593Smuzhiyun unsigned int len, const char *kw)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun int i;
506*4882a593Smuzhiyun
507*4882a593Smuzhiyun for (i = off; i + PCI_VPD_INFO_FLD_HDR_SIZE <= off + len;) {
508*4882a593Smuzhiyun if (buf[i + 0] == kw[0] &&
509*4882a593Smuzhiyun buf[i + 1] == kw[1])
510*4882a593Smuzhiyun return i;
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun i += PCI_VPD_INFO_FLD_HDR_SIZE +
513*4882a593Smuzhiyun pci_vpd_info_field_size(&buf[i]);
514*4882a593Smuzhiyun }
515*4882a593Smuzhiyun
516*4882a593Smuzhiyun return -ENOENT;
517*4882a593Smuzhiyun }
518*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(pci_vpd_find_info_keyword);
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun #ifdef CONFIG_PCI_QUIRKS
521*4882a593Smuzhiyun /*
522*4882a593Smuzhiyun * Quirk non-zero PCI functions to route VPD access through function 0 for
523*4882a593Smuzhiyun * devices that share VPD resources between functions. The functions are
524*4882a593Smuzhiyun * expected to be identical devices.
525*4882a593Smuzhiyun */
quirk_f0_vpd_link(struct pci_dev * dev)526*4882a593Smuzhiyun static void quirk_f0_vpd_link(struct pci_dev *dev)
527*4882a593Smuzhiyun {
528*4882a593Smuzhiyun struct pci_dev *f0;
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun if (!PCI_FUNC(dev->devfn))
531*4882a593Smuzhiyun return;
532*4882a593Smuzhiyun
533*4882a593Smuzhiyun f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
534*4882a593Smuzhiyun if (!f0)
535*4882a593Smuzhiyun return;
536*4882a593Smuzhiyun
537*4882a593Smuzhiyun if (f0->vpd && dev->class == f0->class &&
538*4882a593Smuzhiyun dev->vendor == f0->vendor && dev->device == f0->device)
539*4882a593Smuzhiyun dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun pci_dev_put(f0);
542*4882a593Smuzhiyun }
543*4882a593Smuzhiyun DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
544*4882a593Smuzhiyun PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun /*
547*4882a593Smuzhiyun * If a device follows the VPD format spec, the PCI core will not read or
548*4882a593Smuzhiyun * write past the VPD End Tag. But some vendors do not follow the VPD
549*4882a593Smuzhiyun * format spec, so we can't tell how much data is safe to access. Devices
550*4882a593Smuzhiyun * may behave unpredictably if we access too much. Blacklist these devices
551*4882a593Smuzhiyun * so we don't touch VPD at all.
552*4882a593Smuzhiyun */
quirk_blacklist_vpd(struct pci_dev * dev)553*4882a593Smuzhiyun static void quirk_blacklist_vpd(struct pci_dev *dev)
554*4882a593Smuzhiyun {
555*4882a593Smuzhiyun if (dev->vpd) {
556*4882a593Smuzhiyun dev->vpd->len = 0;
557*4882a593Smuzhiyun pci_warn(dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun }
560*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
561*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
562*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
563*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
564*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
565*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
566*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
567*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
568*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
569*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
570*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
571*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
572*4882a593Smuzhiyun quirk_blacklist_vpd);
573*4882a593Smuzhiyun /*
574*4882a593Smuzhiyun * The Amazon Annapurna Labs 0x0031 device id is reused for other non Root Port
575*4882a593Smuzhiyun * device types, so the quirk is registered for the PCI_CLASS_BRIDGE_PCI class.
576*4882a593Smuzhiyun */
577*4882a593Smuzhiyun DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031,
578*4882a593Smuzhiyun PCI_CLASS_BRIDGE_PCI, 8, quirk_blacklist_vpd);
579*4882a593Smuzhiyun
580*4882a593Smuzhiyun /*
581*4882a593Smuzhiyun * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
582*4882a593Smuzhiyun * VPD end tag will hang the device. This problem was initially
583*4882a593Smuzhiyun * observed when a vpd entry was created in sysfs
584*4882a593Smuzhiyun * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
585*4882a593Smuzhiyun * will dump 32k of data. Reading a full 32k will cause an access
586*4882a593Smuzhiyun * beyond the VPD end tag causing the device to hang. Once the device
587*4882a593Smuzhiyun * is hung, the bnx2 driver will not be able to reset the device.
588*4882a593Smuzhiyun * We believe that it is legal to read beyond the end tag and
589*4882a593Smuzhiyun * therefore the solution is to limit the read/write length.
590*4882a593Smuzhiyun */
quirk_brcm_570x_limit_vpd(struct pci_dev * dev)591*4882a593Smuzhiyun static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
592*4882a593Smuzhiyun {
593*4882a593Smuzhiyun /*
594*4882a593Smuzhiyun * Only disable the VPD capability for 5706, 5706S, 5708,
595*4882a593Smuzhiyun * 5708S and 5709 rev. A
596*4882a593Smuzhiyun */
597*4882a593Smuzhiyun if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
598*4882a593Smuzhiyun (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
599*4882a593Smuzhiyun (dev->device == PCI_DEVICE_ID_NX2_5708) ||
600*4882a593Smuzhiyun (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
601*4882a593Smuzhiyun ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
602*4882a593Smuzhiyun (dev->revision & 0xf0) == 0x0)) {
603*4882a593Smuzhiyun if (dev->vpd)
604*4882a593Smuzhiyun dev->vpd->len = 0x80;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun }
607*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
608*4882a593Smuzhiyun PCI_DEVICE_ID_NX2_5706,
609*4882a593Smuzhiyun quirk_brcm_570x_limit_vpd);
610*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
611*4882a593Smuzhiyun PCI_DEVICE_ID_NX2_5706S,
612*4882a593Smuzhiyun quirk_brcm_570x_limit_vpd);
613*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
614*4882a593Smuzhiyun PCI_DEVICE_ID_NX2_5708,
615*4882a593Smuzhiyun quirk_brcm_570x_limit_vpd);
616*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
617*4882a593Smuzhiyun PCI_DEVICE_ID_NX2_5708S,
618*4882a593Smuzhiyun quirk_brcm_570x_limit_vpd);
619*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
620*4882a593Smuzhiyun PCI_DEVICE_ID_NX2_5709,
621*4882a593Smuzhiyun quirk_brcm_570x_limit_vpd);
622*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
623*4882a593Smuzhiyun PCI_DEVICE_ID_NX2_5709S,
624*4882a593Smuzhiyun quirk_brcm_570x_limit_vpd);
625*4882a593Smuzhiyun
quirk_chelsio_extend_vpd(struct pci_dev * dev)626*4882a593Smuzhiyun static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
627*4882a593Smuzhiyun {
628*4882a593Smuzhiyun int chip = (dev->device & 0xf000) >> 12;
629*4882a593Smuzhiyun int func = (dev->device & 0x0f00) >> 8;
630*4882a593Smuzhiyun int prod = (dev->device & 0x00ff) >> 0;
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun /*
633*4882a593Smuzhiyun * If this is a T3-based adapter, there's a 1KB VPD area at offset
634*4882a593Smuzhiyun * 0xc00 which contains the preferred VPD values. If this is a T4 or
635*4882a593Smuzhiyun * later based adapter, the special VPD is at offset 0x400 for the
636*4882a593Smuzhiyun * Physical Functions (the SR-IOV Virtual Functions have no VPD
637*4882a593Smuzhiyun * Capabilities). The PCI VPD Access core routines will normally
638*4882a593Smuzhiyun * compute the size of the VPD by parsing the VPD Data Structure at
639*4882a593Smuzhiyun * offset 0x000. This will result in silent failures when attempting
640*4882a593Smuzhiyun * to accesses these other VPD areas which are beyond those computed
641*4882a593Smuzhiyun * limits.
642*4882a593Smuzhiyun */
643*4882a593Smuzhiyun if (chip == 0x0 && prod >= 0x20)
644*4882a593Smuzhiyun pci_set_vpd_size(dev, 8192);
645*4882a593Smuzhiyun else if (chip >= 0x4 && func < 0x8)
646*4882a593Smuzhiyun pci_set_vpd_size(dev, 2048);
647*4882a593Smuzhiyun }
648*4882a593Smuzhiyun
649*4882a593Smuzhiyun DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
650*4882a593Smuzhiyun quirk_chelsio_extend_vpd);
651*4882a593Smuzhiyun
652*4882a593Smuzhiyun #endif
653