xref: /OK3568_Linux_fs/kernel/drivers/pci/pcie/portdrv_pci.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Purpose:	PCI Express Port Bus Driver
4*4882a593Smuzhiyun  * Author:	Tom Nguyen <tom.l.nguyen@intel.com>
5*4882a593Smuzhiyun  *
6*4882a593Smuzhiyun  * Copyright (C) 2004 Intel
7*4882a593Smuzhiyun  * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
8*4882a593Smuzhiyun  */
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun #include <linux/pci.h>
11*4882a593Smuzhiyun #include <linux/kernel.h>
12*4882a593Smuzhiyun #include <linux/errno.h>
13*4882a593Smuzhiyun #include <linux/pm.h>
14*4882a593Smuzhiyun #include <linux/pm_runtime.h>
15*4882a593Smuzhiyun #include <linux/init.h>
16*4882a593Smuzhiyun #include <linux/aer.h>
17*4882a593Smuzhiyun #include <linux/dmi.h>
18*4882a593Smuzhiyun 
19*4882a593Smuzhiyun #include "../pci.h"
20*4882a593Smuzhiyun #include "portdrv.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun /* If this switch is set, PCIe port native services should not be enabled. */
23*4882a593Smuzhiyun bool pcie_ports_disabled;
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun  * If the user specified "pcie_ports=native", use the PCIe services regardless
27*4882a593Smuzhiyun  * of whether the platform has given us permission.  On ACPI systems, this
28*4882a593Smuzhiyun  * means we ignore _OSC.
29*4882a593Smuzhiyun  */
30*4882a593Smuzhiyun bool pcie_ports_native;
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun  * If the user specified "pcie_ports=dpc-native", use the Linux DPC PCIe
34*4882a593Smuzhiyun  * service even if the platform hasn't given us permission.
35*4882a593Smuzhiyun  */
36*4882a593Smuzhiyun bool pcie_ports_dpc_native;
37*4882a593Smuzhiyun 
pcie_port_setup(char * str)38*4882a593Smuzhiyun static int __init pcie_port_setup(char *str)
39*4882a593Smuzhiyun {
40*4882a593Smuzhiyun 	if (!strncmp(str, "compat", 6))
41*4882a593Smuzhiyun 		pcie_ports_disabled = true;
42*4882a593Smuzhiyun 	else if (!strncmp(str, "native", 6))
43*4882a593Smuzhiyun 		pcie_ports_native = true;
44*4882a593Smuzhiyun 	else if (!strncmp(str, "dpc-native", 10))
45*4882a593Smuzhiyun 		pcie_ports_dpc_native = true;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	return 1;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun __setup("pcie_ports=", pcie_port_setup);
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun /* global data */
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #ifdef CONFIG_PM
pcie_port_runtime_suspend(struct device * dev)54*4882a593Smuzhiyun static int pcie_port_runtime_suspend(struct device *dev)
55*4882a593Smuzhiyun {
56*4882a593Smuzhiyun 	if (!to_pci_dev(dev)->bridge_d3)
57*4882a593Smuzhiyun 		return -EBUSY;
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun 	return pcie_port_device_runtime_suspend(dev);
60*4882a593Smuzhiyun }
61*4882a593Smuzhiyun 
pcie_port_runtime_idle(struct device * dev)62*4882a593Smuzhiyun static int pcie_port_runtime_idle(struct device *dev)
63*4882a593Smuzhiyun {
64*4882a593Smuzhiyun 	/*
65*4882a593Smuzhiyun 	 * Assume the PCI core has set bridge_d3 whenever it thinks the port
66*4882a593Smuzhiyun 	 * should be good to go to D3.  Everything else, including moving
67*4882a593Smuzhiyun 	 * the port to D3, is handled by the PCI core.
68*4882a593Smuzhiyun 	 */
69*4882a593Smuzhiyun 	return to_pci_dev(dev)->bridge_d3 ? 0 : -EBUSY;
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static const struct dev_pm_ops pcie_portdrv_pm_ops = {
73*4882a593Smuzhiyun 	.suspend	= pcie_port_device_suspend,
74*4882a593Smuzhiyun 	.resume_noirq	= pcie_port_device_resume_noirq,
75*4882a593Smuzhiyun 	.resume		= pcie_port_device_resume,
76*4882a593Smuzhiyun 	.freeze		= pcie_port_device_suspend,
77*4882a593Smuzhiyun 	.thaw		= pcie_port_device_resume,
78*4882a593Smuzhiyun 	.poweroff	= pcie_port_device_suspend,
79*4882a593Smuzhiyun 	.restore_noirq	= pcie_port_device_resume_noirq,
80*4882a593Smuzhiyun 	.restore	= pcie_port_device_resume,
81*4882a593Smuzhiyun 	.runtime_suspend = pcie_port_runtime_suspend,
82*4882a593Smuzhiyun 	.runtime_resume	= pcie_port_device_runtime_resume,
83*4882a593Smuzhiyun 	.runtime_idle	= pcie_port_runtime_idle,
84*4882a593Smuzhiyun };
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun #define PCIE_PORTDRV_PM_OPS	(&pcie_portdrv_pm_ops)
87*4882a593Smuzhiyun 
88*4882a593Smuzhiyun #else /* !PM */
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun #define PCIE_PORTDRV_PM_OPS	NULL
91*4882a593Smuzhiyun #endif /* !PM */
92*4882a593Smuzhiyun 
93*4882a593Smuzhiyun /*
94*4882a593Smuzhiyun  * pcie_portdrv_probe - Probe PCI-Express port devices
95*4882a593Smuzhiyun  * @dev: PCI-Express port device being probed
96*4882a593Smuzhiyun  *
97*4882a593Smuzhiyun  * If detected invokes the pcie_port_device_register() method for
98*4882a593Smuzhiyun  * this port device.
99*4882a593Smuzhiyun  *
100*4882a593Smuzhiyun  */
pcie_portdrv_probe(struct pci_dev * dev,const struct pci_device_id * id)101*4882a593Smuzhiyun static int pcie_portdrv_probe(struct pci_dev *dev,
102*4882a593Smuzhiyun 					const struct pci_device_id *id)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun 	int type = pci_pcie_type(dev);
105*4882a593Smuzhiyun 	int status;
106*4882a593Smuzhiyun 
107*4882a593Smuzhiyun 	if (!pci_is_pcie(dev) ||
108*4882a593Smuzhiyun 	    ((type != PCI_EXP_TYPE_ROOT_PORT) &&
109*4882a593Smuzhiyun 	     (type != PCI_EXP_TYPE_UPSTREAM) &&
110*4882a593Smuzhiyun 	     (type != PCI_EXP_TYPE_DOWNSTREAM) &&
111*4882a593Smuzhiyun 	     (type != PCI_EXP_TYPE_RC_EC)))
112*4882a593Smuzhiyun 		return -ENODEV;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	status = pcie_port_device_register(dev);
115*4882a593Smuzhiyun 	if (status)
116*4882a593Smuzhiyun 		return status;
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun 	pci_save_state(dev);
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE |
121*4882a593Smuzhiyun 					   DPM_FLAG_SMART_SUSPEND);
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	if (pci_bridge_d3_possible(dev)) {
124*4882a593Smuzhiyun 		/*
125*4882a593Smuzhiyun 		 * Keep the port resumed 100ms to make sure things like
126*4882a593Smuzhiyun 		 * config space accesses from userspace (lspci) will not
127*4882a593Smuzhiyun 		 * cause the port to repeatedly suspend and resume.
128*4882a593Smuzhiyun 		 */
129*4882a593Smuzhiyun 		pm_runtime_set_autosuspend_delay(&dev->dev, 100);
130*4882a593Smuzhiyun 		pm_runtime_use_autosuspend(&dev->dev);
131*4882a593Smuzhiyun 		pm_runtime_mark_last_busy(&dev->dev);
132*4882a593Smuzhiyun 		pm_runtime_put_autosuspend(&dev->dev);
133*4882a593Smuzhiyun 		pm_runtime_allow(&dev->dev);
134*4882a593Smuzhiyun 	}
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	return 0;
137*4882a593Smuzhiyun }
138*4882a593Smuzhiyun 
pcie_portdrv_remove(struct pci_dev * dev)139*4882a593Smuzhiyun static void pcie_portdrv_remove(struct pci_dev *dev)
140*4882a593Smuzhiyun {
141*4882a593Smuzhiyun 	if (pci_bridge_d3_possible(dev)) {
142*4882a593Smuzhiyun 		pm_runtime_forbid(&dev->dev);
143*4882a593Smuzhiyun 		pm_runtime_get_noresume(&dev->dev);
144*4882a593Smuzhiyun 		pm_runtime_dont_use_autosuspend(&dev->dev);
145*4882a593Smuzhiyun 	}
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	pcie_port_device_remove(dev);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun 
pcie_portdrv_error_detected(struct pci_dev * dev,pci_channel_state_t error)150*4882a593Smuzhiyun static pci_ers_result_t pcie_portdrv_error_detected(struct pci_dev *dev,
151*4882a593Smuzhiyun 					pci_channel_state_t error)
152*4882a593Smuzhiyun {
153*4882a593Smuzhiyun 	/* Root Port has no impact. Always recovers. */
154*4882a593Smuzhiyun 	return PCI_ERS_RESULT_CAN_RECOVER;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun 
pcie_portdrv_slot_reset(struct pci_dev * dev)157*4882a593Smuzhiyun static pci_ers_result_t pcie_portdrv_slot_reset(struct pci_dev *dev)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun 	pci_restore_state(dev);
160*4882a593Smuzhiyun 	pci_save_state(dev);
161*4882a593Smuzhiyun 	return PCI_ERS_RESULT_RECOVERED;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun 
pcie_portdrv_mmio_enabled(struct pci_dev * dev)164*4882a593Smuzhiyun static pci_ers_result_t pcie_portdrv_mmio_enabled(struct pci_dev *dev)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun 	return PCI_ERS_RESULT_RECOVERED;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun 
resume_iter(struct device * device,void * data)169*4882a593Smuzhiyun static int resume_iter(struct device *device, void *data)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun 	struct pcie_device *pcie_device;
172*4882a593Smuzhiyun 	struct pcie_port_service_driver *driver;
173*4882a593Smuzhiyun 
174*4882a593Smuzhiyun 	if (device->bus == &pcie_port_bus_type && device->driver) {
175*4882a593Smuzhiyun 		driver = to_service_driver(device->driver);
176*4882a593Smuzhiyun 		if (driver && driver->error_resume) {
177*4882a593Smuzhiyun 			pcie_device = to_pcie_device(device);
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 			/* Forward error message to service drivers */
180*4882a593Smuzhiyun 			driver->error_resume(pcie_device->port);
181*4882a593Smuzhiyun 		}
182*4882a593Smuzhiyun 	}
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun 
pcie_portdrv_err_resume(struct pci_dev * dev)187*4882a593Smuzhiyun static void pcie_portdrv_err_resume(struct pci_dev *dev)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun 	device_for_each_child(&dev->dev, NULL, resume_iter);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun /*
193*4882a593Smuzhiyun  * LINUX Device Driver Model
194*4882a593Smuzhiyun  */
195*4882a593Smuzhiyun static const struct pci_device_id port_pci_ids[] = {
196*4882a593Smuzhiyun 	/* handle any PCI-Express port */
197*4882a593Smuzhiyun 	{ PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x00), ~0) },
198*4882a593Smuzhiyun 	/* subtractive decode PCI-to-PCI bridge, class type is 060401h */
199*4882a593Smuzhiyun 	{ PCI_DEVICE_CLASS(((PCI_CLASS_BRIDGE_PCI << 8) | 0x01), ~0) },
200*4882a593Smuzhiyun 	/* handle any Root Complex Event Collector */
201*4882a593Smuzhiyun 	{ PCI_DEVICE_CLASS(((PCI_CLASS_SYSTEM_RCEC << 8) | 0x00), ~0) },
202*4882a593Smuzhiyun 	{ },
203*4882a593Smuzhiyun };
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun static const struct pci_error_handlers pcie_portdrv_err_handler = {
206*4882a593Smuzhiyun 	.error_detected = pcie_portdrv_error_detected,
207*4882a593Smuzhiyun 	.slot_reset = pcie_portdrv_slot_reset,
208*4882a593Smuzhiyun 	.mmio_enabled = pcie_portdrv_mmio_enabled,
209*4882a593Smuzhiyun 	.resume = pcie_portdrv_err_resume,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun static struct pci_driver pcie_portdriver = {
213*4882a593Smuzhiyun 	.name		= "pcieport",
214*4882a593Smuzhiyun 	.id_table	= &port_pci_ids[0],
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun 	.probe		= pcie_portdrv_probe,
217*4882a593Smuzhiyun 	.remove		= pcie_portdrv_remove,
218*4882a593Smuzhiyun 	.shutdown	= pcie_portdrv_remove,
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun 	.err_handler	= &pcie_portdrv_err_handler,
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun 	.driver.pm	= PCIE_PORTDRV_PM_OPS,
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun 
dmi_pcie_pme_disable_msi(const struct dmi_system_id * d)225*4882a593Smuzhiyun static int __init dmi_pcie_pme_disable_msi(const struct dmi_system_id *d)
226*4882a593Smuzhiyun {
227*4882a593Smuzhiyun 	pr_notice("%s detected: will not use MSI for PCIe PME signaling\n",
228*4882a593Smuzhiyun 		  d->ident);
229*4882a593Smuzhiyun 	pcie_pme_disable_msi();
230*4882a593Smuzhiyun 	return 0;
231*4882a593Smuzhiyun }
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun static const struct dmi_system_id pcie_portdrv_dmi_table[] __initconst = {
234*4882a593Smuzhiyun 	/*
235*4882a593Smuzhiyun 	 * Boxes that should not use MSI for PCIe PME signaling.
236*4882a593Smuzhiyun 	 */
237*4882a593Smuzhiyun 	{
238*4882a593Smuzhiyun 	 .callback = dmi_pcie_pme_disable_msi,
239*4882a593Smuzhiyun 	 .ident = "MSI Wind U-100",
240*4882a593Smuzhiyun 	 .matches = {
241*4882a593Smuzhiyun 		     DMI_MATCH(DMI_SYS_VENDOR,
242*4882a593Smuzhiyun 				"MICRO-STAR INTERNATIONAL CO., LTD"),
243*4882a593Smuzhiyun 		     DMI_MATCH(DMI_PRODUCT_NAME, "U-100"),
244*4882a593Smuzhiyun 		     },
245*4882a593Smuzhiyun 	 },
246*4882a593Smuzhiyun 	 {}
247*4882a593Smuzhiyun };
248*4882a593Smuzhiyun 
pcie_init_services(void)249*4882a593Smuzhiyun static void __init pcie_init_services(void)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	pcie_aer_init();
252*4882a593Smuzhiyun 	pcie_pme_init();
253*4882a593Smuzhiyun 	pcie_dpc_init();
254*4882a593Smuzhiyun 	pcie_hp_init();
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
pcie_portdrv_init(void)257*4882a593Smuzhiyun static int __init pcie_portdrv_init(void)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	if (pcie_ports_disabled)
260*4882a593Smuzhiyun 		return -EACCES;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	pcie_init_services();
263*4882a593Smuzhiyun 	dmi_check_system(pcie_portdrv_dmi_table);
264*4882a593Smuzhiyun 
265*4882a593Smuzhiyun 	return pci_register_driver(&pcie_portdriver);
266*4882a593Smuzhiyun }
267*4882a593Smuzhiyun device_initcall(pcie_portdrv_init);
268