1*4882a593Smuzhiyun# SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun# 3*4882a593Smuzhiyun# PCI Express Port Bus Configuration 4*4882a593Smuzhiyun# 5*4882a593Smuzhiyunconfig PCIEPORTBUS 6*4882a593Smuzhiyun bool "PCI Express Port Bus support" 7*4882a593Smuzhiyun help 8*4882a593Smuzhiyun This enables PCI Express Port Bus support. Users can then enable 9*4882a593Smuzhiyun support for Native Hot-Plug, Advanced Error Reporting, Power 10*4882a593Smuzhiyun Management Events, and Downstream Port Containment. 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun# 13*4882a593Smuzhiyun# Include service Kconfig here 14*4882a593Smuzhiyun# 15*4882a593Smuzhiyunconfig HOTPLUG_PCI_PCIE 16*4882a593Smuzhiyun bool "PCI Express Hotplug driver" 17*4882a593Smuzhiyun depends on HOTPLUG_PCI && PCIEPORTBUS 18*4882a593Smuzhiyun help 19*4882a593Smuzhiyun Say Y here if you have a motherboard that supports PCI Express Native 20*4882a593Smuzhiyun Hotplug 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun When in doubt, say N. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyunconfig PCIEAER 25*4882a593Smuzhiyun bool "PCI Express Advanced Error Reporting support" 26*4882a593Smuzhiyun depends on PCIEPORTBUS 27*4882a593Smuzhiyun select RAS 28*4882a593Smuzhiyun help 29*4882a593Smuzhiyun This enables PCI Express Root Port Advanced Error Reporting 30*4882a593Smuzhiyun (AER) driver support. Error reporting messages sent to Root 31*4882a593Smuzhiyun Port will be handled by PCI Express AER driver. 32*4882a593Smuzhiyun 33*4882a593Smuzhiyunconfig PCIEAER_INJECT 34*4882a593Smuzhiyun tristate "PCI Express error injection support" 35*4882a593Smuzhiyun depends on PCIEAER 36*4882a593Smuzhiyun select GENERIC_IRQ_INJECTION 37*4882a593Smuzhiyun help 38*4882a593Smuzhiyun This enables PCI Express Root Port Advanced Error Reporting 39*4882a593Smuzhiyun (AER) software error injector. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun Debugging AER code is quite difficult because it is hard 42*4882a593Smuzhiyun to trigger various real hardware errors. Software-based 43*4882a593Smuzhiyun error injection can fake almost all kinds of errors with the 44*4882a593Smuzhiyun help of a user space helper tool aer-inject, which can be 45*4882a593Smuzhiyun gotten from: 46*4882a593Smuzhiyun https://www.kernel.org/pub/linux/utils/pci/aer-inject/ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun# 49*4882a593Smuzhiyun# PCI Express ECRC 50*4882a593Smuzhiyun# 51*4882a593Smuzhiyunconfig PCIE_ECRC 52*4882a593Smuzhiyun bool "PCI Express ECRC settings control" 53*4882a593Smuzhiyun depends on PCIEAER 54*4882a593Smuzhiyun help 55*4882a593Smuzhiyun Used to override firmware/bios settings for PCI Express ECRC 56*4882a593Smuzhiyun (transaction layer end-to-end CRC checking). 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun When in doubt, say N. 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun# 61*4882a593Smuzhiyun# PCI Express ASPM 62*4882a593Smuzhiyun# 63*4882a593Smuzhiyunconfig PCIEASPM 64*4882a593Smuzhiyun bool "PCI Express ASPM control" if EXPERT 65*4882a593Smuzhiyun default y 66*4882a593Smuzhiyun help 67*4882a593Smuzhiyun This enables OS control over PCI Express ASPM (Active State 68*4882a593Smuzhiyun Power Management) and Clock Power Management. ASPM supports 69*4882a593Smuzhiyun state L0/L0s/L1. 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun ASPM is initially set up by the firmware. With this option enabled, 72*4882a593Smuzhiyun Linux can modify this state in order to disable ASPM on known-bad 73*4882a593Smuzhiyun hardware or configurations and enable it when known-safe. 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun ASPM can be disabled or enabled at runtime via 76*4882a593Smuzhiyun /sys/module/pcie_aspm/parameters/policy 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun When in doubt, say Y. 79*4882a593Smuzhiyun 80*4882a593Smuzhiyunchoice 81*4882a593Smuzhiyun prompt "Default ASPM policy" 82*4882a593Smuzhiyun default PCIEASPM_DEFAULT 83*4882a593Smuzhiyun depends on PCIEASPM 84*4882a593Smuzhiyun 85*4882a593Smuzhiyunconfig PCIEASPM_DEFAULT 86*4882a593Smuzhiyun bool "BIOS default" 87*4882a593Smuzhiyun depends on PCIEASPM 88*4882a593Smuzhiyun help 89*4882a593Smuzhiyun Use the BIOS defaults for PCI Express ASPM. 90*4882a593Smuzhiyun 91*4882a593Smuzhiyunconfig PCIEASPM_POWERSAVE 92*4882a593Smuzhiyun bool "Powersave" 93*4882a593Smuzhiyun depends on PCIEASPM 94*4882a593Smuzhiyun help 95*4882a593Smuzhiyun Enable PCI Express ASPM L0s and L1 where possible, even if the 96*4882a593Smuzhiyun BIOS did not. 97*4882a593Smuzhiyun 98*4882a593Smuzhiyunconfig PCIEASPM_POWER_SUPERSAVE 99*4882a593Smuzhiyun bool "Power Supersave" 100*4882a593Smuzhiyun depends on PCIEASPM 101*4882a593Smuzhiyun help 102*4882a593Smuzhiyun Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where 103*4882a593Smuzhiyun possible. This would result in higher power savings while staying in L1 104*4882a593Smuzhiyun where the components support it. 105*4882a593Smuzhiyun 106*4882a593Smuzhiyunconfig PCIEASPM_PERFORMANCE 107*4882a593Smuzhiyun bool "Performance" 108*4882a593Smuzhiyun depends on PCIEASPM 109*4882a593Smuzhiyun help 110*4882a593Smuzhiyun Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them. 111*4882a593Smuzhiyunendchoice 112*4882a593Smuzhiyun 113*4882a593Smuzhiyunconfig PCIEASPM_EXT 114*4882a593Smuzhiyun tristate "Extend ASPM function" 115*4882a593Smuzhiyun depends on PCIEASPM 116*4882a593Smuzhiyun help 117*4882a593Smuzhiyun This enables the extensions APIs for ASPM control. 118*4882a593Smuzhiyun 119*4882a593Smuzhiyunconfig PCIE_PME 120*4882a593Smuzhiyun def_bool y 121*4882a593Smuzhiyun depends on PCIEPORTBUS && PM 122*4882a593Smuzhiyun 123*4882a593Smuzhiyunconfig PCIE_DPC 124*4882a593Smuzhiyun bool "PCI Express Downstream Port Containment support" 125*4882a593Smuzhiyun depends on PCIEPORTBUS && PCIEAER 126*4882a593Smuzhiyun help 127*4882a593Smuzhiyun This enables PCI Express Downstream Port Containment (DPC) 128*4882a593Smuzhiyun driver support. DPC events from Root and Downstream ports 129*4882a593Smuzhiyun will be handled by the DPC driver. If your system doesn't 130*4882a593Smuzhiyun have this capability or you do not want to use this feature, 131*4882a593Smuzhiyun it is safe to answer N. 132*4882a593Smuzhiyun 133*4882a593Smuzhiyunconfig PCIE_PTM 134*4882a593Smuzhiyun bool "PCI Express Precision Time Measurement support" 135*4882a593Smuzhiyun help 136*4882a593Smuzhiyun This enables PCI Express Precision Time Measurement (PTM) 137*4882a593Smuzhiyun support. 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun This is only useful if you have devices that support PTM, but it 140*4882a593Smuzhiyun is safe to enable even if you don't. 141*4882a593Smuzhiyun 142*4882a593Smuzhiyunconfig PCIE_EDR 143*4882a593Smuzhiyun bool "PCI Express Error Disconnect Recover support" 144*4882a593Smuzhiyun depends on PCIE_DPC && ACPI 145*4882a593Smuzhiyun help 146*4882a593Smuzhiyun This option adds Error Disconnect Recover support as specified 147*4882a593Smuzhiyun in the Downstream Port Containment Related Enhancements ECN to 148*4882a593Smuzhiyun the PCI Firmware Specification r3.2. Enable this if you want to 149*4882a593Smuzhiyun support hybrid DPC model which uses both firmware and OS to 150*4882a593Smuzhiyun implement DPC. 151