1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel MID platform PM support
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2016, Intel Corporation
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/init.h>
11*4882a593Smuzhiyun #include <linux/pci.h>
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <asm/cpu_device_id.h>
14*4882a593Smuzhiyun #include <asm/intel-family.h>
15*4882a593Smuzhiyun #include <asm/intel-mid.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include "pci.h"
18*4882a593Smuzhiyun
mid_pci_power_manageable(struct pci_dev * dev)19*4882a593Smuzhiyun static bool mid_pci_power_manageable(struct pci_dev *dev)
20*4882a593Smuzhiyun {
21*4882a593Smuzhiyun return true;
22*4882a593Smuzhiyun }
23*4882a593Smuzhiyun
mid_pci_set_power_state(struct pci_dev * pdev,pci_power_t state)24*4882a593Smuzhiyun static int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
25*4882a593Smuzhiyun {
26*4882a593Smuzhiyun return intel_mid_pci_set_power_state(pdev, state);
27*4882a593Smuzhiyun }
28*4882a593Smuzhiyun
mid_pci_get_power_state(struct pci_dev * pdev)29*4882a593Smuzhiyun static pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
30*4882a593Smuzhiyun {
31*4882a593Smuzhiyun return intel_mid_pci_get_power_state(pdev);
32*4882a593Smuzhiyun }
33*4882a593Smuzhiyun
mid_pci_choose_state(struct pci_dev * pdev)34*4882a593Smuzhiyun static pci_power_t mid_pci_choose_state(struct pci_dev *pdev)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun return PCI_D3hot;
37*4882a593Smuzhiyun }
38*4882a593Smuzhiyun
mid_pci_wakeup(struct pci_dev * dev,bool enable)39*4882a593Smuzhiyun static int mid_pci_wakeup(struct pci_dev *dev, bool enable)
40*4882a593Smuzhiyun {
41*4882a593Smuzhiyun return 0;
42*4882a593Smuzhiyun }
43*4882a593Smuzhiyun
mid_pci_need_resume(struct pci_dev * dev)44*4882a593Smuzhiyun static bool mid_pci_need_resume(struct pci_dev *dev)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun return false;
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun static const struct pci_platform_pm_ops mid_pci_platform_pm = {
50*4882a593Smuzhiyun .is_manageable = mid_pci_power_manageable,
51*4882a593Smuzhiyun .set_state = mid_pci_set_power_state,
52*4882a593Smuzhiyun .get_state = mid_pci_get_power_state,
53*4882a593Smuzhiyun .choose_state = mid_pci_choose_state,
54*4882a593Smuzhiyun .set_wakeup = mid_pci_wakeup,
55*4882a593Smuzhiyun .need_resume = mid_pci_need_resume,
56*4882a593Smuzhiyun };
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * This table should be in sync with the one in
60*4882a593Smuzhiyun * arch/x86/platform/intel-mid/pwr.c.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun static const struct x86_cpu_id lpss_cpu_ids[] = {
63*4882a593Smuzhiyun X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, NULL),
64*4882a593Smuzhiyun X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL),
65*4882a593Smuzhiyun {}
66*4882a593Smuzhiyun };
67*4882a593Smuzhiyun
mid_pci_init(void)68*4882a593Smuzhiyun static int __init mid_pci_init(void)
69*4882a593Smuzhiyun {
70*4882a593Smuzhiyun const struct x86_cpu_id *id;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun id = x86_match_cpu(lpss_cpu_ids);
73*4882a593Smuzhiyun if (id)
74*4882a593Smuzhiyun pci_set_platform_pm(&mid_pci_platform_pm);
75*4882a593Smuzhiyun return 0;
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun arch_initcall(mid_pci_init);
78