xref: /OK3568_Linux_fs/kernel/drivers/pci/hotplug/cpqphp.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Compaq Hot Plug Controller Driver
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 1995,2001 Compaq Computer Corporation
6*4882a593Smuzhiyun  * Copyright (C) 2001 Greg Kroah-Hartman (greg@kroah.com)
7*4882a593Smuzhiyun  * Copyright (C) 2001 IBM
8*4882a593Smuzhiyun  *
9*4882a593Smuzhiyun  * All rights reserved.
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * Send feedback to <greg@kroah.com>
12*4882a593Smuzhiyun  *
13*4882a593Smuzhiyun  */
14*4882a593Smuzhiyun #ifndef _CPQPHP_H
15*4882a593Smuzhiyun #define _CPQPHP_H
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #include <linux/interrupt.h>
18*4882a593Smuzhiyun #include <asm/io.h>		/* for read? and write? functions */
19*4882a593Smuzhiyun #include <linux/delay.h>	/* for delays */
20*4882a593Smuzhiyun #include <linux/mutex.h>
21*4882a593Smuzhiyun #include <linux/sched/signal.h>	/* for signal_pending() */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #define MY_NAME	"cpqphp"
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define dbg(fmt, arg...) do { if (cpqhp_debug) printk(KERN_DEBUG "%s: " fmt, MY_NAME, ## arg); } while (0)
26*4882a593Smuzhiyun #define err(format, arg...) printk(KERN_ERR "%s: " format, MY_NAME, ## arg)
27*4882a593Smuzhiyun #define info(format, arg...) printk(KERN_INFO "%s: " format, MY_NAME, ## arg)
28*4882a593Smuzhiyun #define warn(format, arg...) printk(KERN_WARNING "%s: " format, MY_NAME, ## arg)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun struct smbios_system_slot {
33*4882a593Smuzhiyun 	u8 type;
34*4882a593Smuzhiyun 	u8 length;
35*4882a593Smuzhiyun 	u16 handle;
36*4882a593Smuzhiyun 	u8 name_string_num;
37*4882a593Smuzhiyun 	u8 slot_type;
38*4882a593Smuzhiyun 	u8 slot_width;
39*4882a593Smuzhiyun 	u8 slot_current_usage;
40*4882a593Smuzhiyun 	u8 slot_length;
41*4882a593Smuzhiyun 	u16 slot_number;
42*4882a593Smuzhiyun 	u8 properties1;
43*4882a593Smuzhiyun 	u8 properties2;
44*4882a593Smuzhiyun } __attribute__ ((packed));
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun /* offsets to the smbios generic type based on the above structure layout */
47*4882a593Smuzhiyun enum smbios_system_slot_offsets {
48*4882a593Smuzhiyun 	SMBIOS_SLOT_GENERIC_TYPE =	offsetof(struct smbios_system_slot, type),
49*4882a593Smuzhiyun 	SMBIOS_SLOT_GENERIC_LENGTH =	offsetof(struct smbios_system_slot, length),
50*4882a593Smuzhiyun 	SMBIOS_SLOT_GENERIC_HANDLE =	offsetof(struct smbios_system_slot, handle),
51*4882a593Smuzhiyun 	SMBIOS_SLOT_NAME_STRING_NUM =	offsetof(struct smbios_system_slot, name_string_num),
52*4882a593Smuzhiyun 	SMBIOS_SLOT_TYPE =		offsetof(struct smbios_system_slot, slot_type),
53*4882a593Smuzhiyun 	SMBIOS_SLOT_WIDTH =		offsetof(struct smbios_system_slot, slot_width),
54*4882a593Smuzhiyun 	SMBIOS_SLOT_CURRENT_USAGE =	offsetof(struct smbios_system_slot, slot_current_usage),
55*4882a593Smuzhiyun 	SMBIOS_SLOT_LENGTH =		offsetof(struct smbios_system_slot, slot_length),
56*4882a593Smuzhiyun 	SMBIOS_SLOT_NUMBER =		offsetof(struct smbios_system_slot, slot_number),
57*4882a593Smuzhiyun 	SMBIOS_SLOT_PROPERTIES1 =	offsetof(struct smbios_system_slot, properties1),
58*4882a593Smuzhiyun 	SMBIOS_SLOT_PROPERTIES2 =	offsetof(struct smbios_system_slot, properties2),
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun struct smbios_generic {
62*4882a593Smuzhiyun 	u8 type;
63*4882a593Smuzhiyun 	u8 length;
64*4882a593Smuzhiyun 	u16 handle;
65*4882a593Smuzhiyun } __attribute__ ((packed));
66*4882a593Smuzhiyun 
67*4882a593Smuzhiyun /* offsets to the smbios generic type based on the above structure layout */
68*4882a593Smuzhiyun enum smbios_generic_offsets {
69*4882a593Smuzhiyun 	SMBIOS_GENERIC_TYPE =	offsetof(struct smbios_generic, type),
70*4882a593Smuzhiyun 	SMBIOS_GENERIC_LENGTH =	offsetof(struct smbios_generic, length),
71*4882a593Smuzhiyun 	SMBIOS_GENERIC_HANDLE =	offsetof(struct smbios_generic, handle),
72*4882a593Smuzhiyun };
73*4882a593Smuzhiyun 
74*4882a593Smuzhiyun struct smbios_entry_point {
75*4882a593Smuzhiyun 	char anchor[4];
76*4882a593Smuzhiyun 	u8 ep_checksum;
77*4882a593Smuzhiyun 	u8 ep_length;
78*4882a593Smuzhiyun 	u8 major_version;
79*4882a593Smuzhiyun 	u8 minor_version;
80*4882a593Smuzhiyun 	u16 max_size_entry;
81*4882a593Smuzhiyun 	u8 ep_rev;
82*4882a593Smuzhiyun 	u8 reserved[5];
83*4882a593Smuzhiyun 	char int_anchor[5];
84*4882a593Smuzhiyun 	u8 int_checksum;
85*4882a593Smuzhiyun 	u16 st_length;
86*4882a593Smuzhiyun 	u32 st_address;
87*4882a593Smuzhiyun 	u16 number_of_entrys;
88*4882a593Smuzhiyun 	u8 bcd_rev;
89*4882a593Smuzhiyun } __attribute__ ((packed));
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun /* offsets to the smbios entry point based on the above structure layout */
92*4882a593Smuzhiyun enum smbios_entry_point_offsets {
93*4882a593Smuzhiyun 	ANCHOR =		offsetof(struct smbios_entry_point, anchor[0]),
94*4882a593Smuzhiyun 	EP_CHECKSUM =		offsetof(struct smbios_entry_point, ep_checksum),
95*4882a593Smuzhiyun 	EP_LENGTH =		offsetof(struct smbios_entry_point, ep_length),
96*4882a593Smuzhiyun 	MAJOR_VERSION =		offsetof(struct smbios_entry_point, major_version),
97*4882a593Smuzhiyun 	MINOR_VERSION =		offsetof(struct smbios_entry_point, minor_version),
98*4882a593Smuzhiyun 	MAX_SIZE_ENTRY =	offsetof(struct smbios_entry_point, max_size_entry),
99*4882a593Smuzhiyun 	EP_REV =		offsetof(struct smbios_entry_point, ep_rev),
100*4882a593Smuzhiyun 	INT_ANCHOR =		offsetof(struct smbios_entry_point, int_anchor[0]),
101*4882a593Smuzhiyun 	INT_CHECKSUM =		offsetof(struct smbios_entry_point, int_checksum),
102*4882a593Smuzhiyun 	ST_LENGTH =		offsetof(struct smbios_entry_point, st_length),
103*4882a593Smuzhiyun 	ST_ADDRESS =		offsetof(struct smbios_entry_point, st_address),
104*4882a593Smuzhiyun 	NUMBER_OF_ENTRYS =	offsetof(struct smbios_entry_point, number_of_entrys),
105*4882a593Smuzhiyun 	BCD_REV =		offsetof(struct smbios_entry_point, bcd_rev),
106*4882a593Smuzhiyun };
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun struct ctrl_reg {			/* offset */
109*4882a593Smuzhiyun 	u8	slot_RST;		/* 0x00 */
110*4882a593Smuzhiyun 	u8	slot_enable;		/* 0x01 */
111*4882a593Smuzhiyun 	u16	misc;			/* 0x02 */
112*4882a593Smuzhiyun 	u32	led_control;		/* 0x04 */
113*4882a593Smuzhiyun 	u32	int_input_clear;	/* 0x08 */
114*4882a593Smuzhiyun 	u32	int_mask;		/* 0x0a */
115*4882a593Smuzhiyun 	u8	reserved0;		/* 0x10 */
116*4882a593Smuzhiyun 	u8	reserved1;		/* 0x11 */
117*4882a593Smuzhiyun 	u8	reserved2;		/* 0x12 */
118*4882a593Smuzhiyun 	u8	gen_output_AB;		/* 0x13 */
119*4882a593Smuzhiyun 	u32	non_int_input;		/* 0x14 */
120*4882a593Smuzhiyun 	u32	reserved3;		/* 0x18 */
121*4882a593Smuzhiyun 	u32	reserved4;		/* 0x1a */
122*4882a593Smuzhiyun 	u32	reserved5;		/* 0x20 */
123*4882a593Smuzhiyun 	u8	reserved6;		/* 0x24 */
124*4882a593Smuzhiyun 	u8	reserved7;		/* 0x25 */
125*4882a593Smuzhiyun 	u16	reserved8;		/* 0x26 */
126*4882a593Smuzhiyun 	u8	slot_mask;		/* 0x28 */
127*4882a593Smuzhiyun 	u8	reserved9;		/* 0x29 */
128*4882a593Smuzhiyun 	u8	reserved10;		/* 0x2a */
129*4882a593Smuzhiyun 	u8	reserved11;		/* 0x2b */
130*4882a593Smuzhiyun 	u8	slot_SERR;		/* 0x2c */
131*4882a593Smuzhiyun 	u8	slot_power;		/* 0x2d */
132*4882a593Smuzhiyun 	u8	reserved12;		/* 0x2e */
133*4882a593Smuzhiyun 	u8	reserved13;		/* 0x2f */
134*4882a593Smuzhiyun 	u8	next_curr_freq;		/* 0x30 */
135*4882a593Smuzhiyun 	u8	reset_freq_mode;	/* 0x31 */
136*4882a593Smuzhiyun } __attribute__ ((packed));
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun /* offsets to the controller registers based on the above structure layout */
139*4882a593Smuzhiyun enum ctrl_offsets {
140*4882a593Smuzhiyun 	SLOT_RST =		offsetof(struct ctrl_reg, slot_RST),
141*4882a593Smuzhiyun 	SLOT_ENABLE =		offsetof(struct ctrl_reg, slot_enable),
142*4882a593Smuzhiyun 	MISC =			offsetof(struct ctrl_reg, misc),
143*4882a593Smuzhiyun 	LED_CONTROL =		offsetof(struct ctrl_reg, led_control),
144*4882a593Smuzhiyun 	INT_INPUT_CLEAR =	offsetof(struct ctrl_reg, int_input_clear),
145*4882a593Smuzhiyun 	INT_MASK =		offsetof(struct ctrl_reg, int_mask),
146*4882a593Smuzhiyun 	CTRL_RESERVED0 =	offsetof(struct ctrl_reg, reserved0),
147*4882a593Smuzhiyun 	CTRL_RESERVED1 =	offsetof(struct ctrl_reg, reserved1),
148*4882a593Smuzhiyun 	CTRL_RESERVED2 =	offsetof(struct ctrl_reg, reserved1),
149*4882a593Smuzhiyun 	GEN_OUTPUT_AB =		offsetof(struct ctrl_reg, gen_output_AB),
150*4882a593Smuzhiyun 	NON_INT_INPUT =		offsetof(struct ctrl_reg, non_int_input),
151*4882a593Smuzhiyun 	CTRL_RESERVED3 =	offsetof(struct ctrl_reg, reserved3),
152*4882a593Smuzhiyun 	CTRL_RESERVED4 =	offsetof(struct ctrl_reg, reserved4),
153*4882a593Smuzhiyun 	CTRL_RESERVED5 =	offsetof(struct ctrl_reg, reserved5),
154*4882a593Smuzhiyun 	CTRL_RESERVED6 =	offsetof(struct ctrl_reg, reserved6),
155*4882a593Smuzhiyun 	CTRL_RESERVED7 =	offsetof(struct ctrl_reg, reserved7),
156*4882a593Smuzhiyun 	CTRL_RESERVED8 =	offsetof(struct ctrl_reg, reserved8),
157*4882a593Smuzhiyun 	SLOT_MASK =		offsetof(struct ctrl_reg, slot_mask),
158*4882a593Smuzhiyun 	CTRL_RESERVED9 =	offsetof(struct ctrl_reg, reserved9),
159*4882a593Smuzhiyun 	CTRL_RESERVED10 =	offsetof(struct ctrl_reg, reserved10),
160*4882a593Smuzhiyun 	CTRL_RESERVED11 =	offsetof(struct ctrl_reg, reserved11),
161*4882a593Smuzhiyun 	SLOT_SERR =		offsetof(struct ctrl_reg, slot_SERR),
162*4882a593Smuzhiyun 	SLOT_POWER =		offsetof(struct ctrl_reg, slot_power),
163*4882a593Smuzhiyun 	NEXT_CURR_FREQ =	offsetof(struct ctrl_reg, next_curr_freq),
164*4882a593Smuzhiyun 	RESET_FREQ_MODE =	offsetof(struct ctrl_reg, reset_freq_mode),
165*4882a593Smuzhiyun };
166*4882a593Smuzhiyun 
167*4882a593Smuzhiyun struct hrt {
168*4882a593Smuzhiyun 	char sig0;
169*4882a593Smuzhiyun 	char sig1;
170*4882a593Smuzhiyun 	char sig2;
171*4882a593Smuzhiyun 	char sig3;
172*4882a593Smuzhiyun 	u16 unused_IRQ;
173*4882a593Smuzhiyun 	u16 PCIIRQ;
174*4882a593Smuzhiyun 	u8 number_of_entries;
175*4882a593Smuzhiyun 	u8 revision;
176*4882a593Smuzhiyun 	u16 reserved1;
177*4882a593Smuzhiyun 	u32 reserved2;
178*4882a593Smuzhiyun } __attribute__ ((packed));
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /* offsets to the hotplug resource table registers based on the above
181*4882a593Smuzhiyun  * structure layout
182*4882a593Smuzhiyun  */
183*4882a593Smuzhiyun enum hrt_offsets {
184*4882a593Smuzhiyun 	SIG0 =			offsetof(struct hrt, sig0),
185*4882a593Smuzhiyun 	SIG1 =			offsetof(struct hrt, sig1),
186*4882a593Smuzhiyun 	SIG2 =			offsetof(struct hrt, sig2),
187*4882a593Smuzhiyun 	SIG3 =			offsetof(struct hrt, sig3),
188*4882a593Smuzhiyun 	UNUSED_IRQ =		offsetof(struct hrt, unused_IRQ),
189*4882a593Smuzhiyun 	PCIIRQ =		offsetof(struct hrt, PCIIRQ),
190*4882a593Smuzhiyun 	NUMBER_OF_ENTRIES =	offsetof(struct hrt, number_of_entries),
191*4882a593Smuzhiyun 	REVISION =		offsetof(struct hrt, revision),
192*4882a593Smuzhiyun 	HRT_RESERVED1 =		offsetof(struct hrt, reserved1),
193*4882a593Smuzhiyun 	HRT_RESERVED2 =		offsetof(struct hrt, reserved2),
194*4882a593Smuzhiyun };
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun struct slot_rt {
197*4882a593Smuzhiyun 	u8 dev_func;
198*4882a593Smuzhiyun 	u8 primary_bus;
199*4882a593Smuzhiyun 	u8 secondary_bus;
200*4882a593Smuzhiyun 	u8 max_bus;
201*4882a593Smuzhiyun 	u16 io_base;
202*4882a593Smuzhiyun 	u16 io_length;
203*4882a593Smuzhiyun 	u16 mem_base;
204*4882a593Smuzhiyun 	u16 mem_length;
205*4882a593Smuzhiyun 	u16 pre_mem_base;
206*4882a593Smuzhiyun 	u16 pre_mem_length;
207*4882a593Smuzhiyun } __attribute__ ((packed));
208*4882a593Smuzhiyun 
209*4882a593Smuzhiyun /* offsets to the hotplug slot resource table registers based on the above
210*4882a593Smuzhiyun  * structure layout
211*4882a593Smuzhiyun  */
212*4882a593Smuzhiyun enum slot_rt_offsets {
213*4882a593Smuzhiyun 	DEV_FUNC =		offsetof(struct slot_rt, dev_func),
214*4882a593Smuzhiyun 	PRIMARY_BUS =		offsetof(struct slot_rt, primary_bus),
215*4882a593Smuzhiyun 	SECONDARY_BUS =		offsetof(struct slot_rt, secondary_bus),
216*4882a593Smuzhiyun 	MAX_BUS =		offsetof(struct slot_rt, max_bus),
217*4882a593Smuzhiyun 	IO_BASE =		offsetof(struct slot_rt, io_base),
218*4882a593Smuzhiyun 	IO_LENGTH =		offsetof(struct slot_rt, io_length),
219*4882a593Smuzhiyun 	MEM_BASE =		offsetof(struct slot_rt, mem_base),
220*4882a593Smuzhiyun 	MEM_LENGTH =		offsetof(struct slot_rt, mem_length),
221*4882a593Smuzhiyun 	PRE_MEM_BASE =		offsetof(struct slot_rt, pre_mem_base),
222*4882a593Smuzhiyun 	PRE_MEM_LENGTH =	offsetof(struct slot_rt, pre_mem_length),
223*4882a593Smuzhiyun };
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun struct pci_func {
226*4882a593Smuzhiyun 	struct pci_func *next;
227*4882a593Smuzhiyun 	u8 bus;
228*4882a593Smuzhiyun 	u8 device;
229*4882a593Smuzhiyun 	u8 function;
230*4882a593Smuzhiyun 	u8 is_a_board;
231*4882a593Smuzhiyun 	u16 status;
232*4882a593Smuzhiyun 	u8 configured;
233*4882a593Smuzhiyun 	u8 switch_save;
234*4882a593Smuzhiyun 	u8 presence_save;
235*4882a593Smuzhiyun 	u32 base_length[0x06];
236*4882a593Smuzhiyun 	u8 base_type[0x06];
237*4882a593Smuzhiyun 	u16 reserved2;
238*4882a593Smuzhiyun 	u32 config_space[0x20];
239*4882a593Smuzhiyun 	struct pci_resource *mem_head;
240*4882a593Smuzhiyun 	struct pci_resource *p_mem_head;
241*4882a593Smuzhiyun 	struct pci_resource *io_head;
242*4882a593Smuzhiyun 	struct pci_resource *bus_head;
243*4882a593Smuzhiyun 	struct timer_list *p_task_event;
244*4882a593Smuzhiyun 	struct pci_dev *pci_dev;
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun 
247*4882a593Smuzhiyun struct slot {
248*4882a593Smuzhiyun 	struct slot *next;
249*4882a593Smuzhiyun 	u8 bus;
250*4882a593Smuzhiyun 	u8 device;
251*4882a593Smuzhiyun 	u8 number;
252*4882a593Smuzhiyun 	u8 is_a_board;
253*4882a593Smuzhiyun 	u8 configured;
254*4882a593Smuzhiyun 	u8 state;
255*4882a593Smuzhiyun 	u8 switch_save;
256*4882a593Smuzhiyun 	u8 presence_save;
257*4882a593Smuzhiyun 	u32 capabilities;
258*4882a593Smuzhiyun 	u16 reserved2;
259*4882a593Smuzhiyun 	struct timer_list task_event;
260*4882a593Smuzhiyun 	u8 hp_slot;
261*4882a593Smuzhiyun 	struct controller *ctrl;
262*4882a593Smuzhiyun 	void __iomem *p_sm_slot;
263*4882a593Smuzhiyun 	struct hotplug_slot hotplug_slot;
264*4882a593Smuzhiyun };
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun struct pci_resource {
267*4882a593Smuzhiyun 	struct pci_resource *next;
268*4882a593Smuzhiyun 	u32 base;
269*4882a593Smuzhiyun 	u32 length;
270*4882a593Smuzhiyun };
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun struct event_info {
273*4882a593Smuzhiyun 	u32 event_type;
274*4882a593Smuzhiyun 	u8 hp_slot;
275*4882a593Smuzhiyun };
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun struct controller {
278*4882a593Smuzhiyun 	struct controller *next;
279*4882a593Smuzhiyun 	u32 ctrl_int_comp;
280*4882a593Smuzhiyun 	struct mutex crit_sect;	/* critical section mutex */
281*4882a593Smuzhiyun 	void __iomem *hpc_reg;	/* cookie for our pci controller location */
282*4882a593Smuzhiyun 	struct pci_resource *mem_head;
283*4882a593Smuzhiyun 	struct pci_resource *p_mem_head;
284*4882a593Smuzhiyun 	struct pci_resource *io_head;
285*4882a593Smuzhiyun 	struct pci_resource *bus_head;
286*4882a593Smuzhiyun 	struct pci_dev *pci_dev;
287*4882a593Smuzhiyun 	struct pci_bus *pci_bus;
288*4882a593Smuzhiyun 	struct event_info event_queue[10];
289*4882a593Smuzhiyun 	struct slot *slot;
290*4882a593Smuzhiyun 	u8 next_event;
291*4882a593Smuzhiyun 	u8 interrupt;
292*4882a593Smuzhiyun 	u8 cfgspc_irq;
293*4882a593Smuzhiyun 	u8 bus;			/* bus number for the pci hotplug controller */
294*4882a593Smuzhiyun 	u8 rev;
295*4882a593Smuzhiyun 	u8 slot_device_offset;
296*4882a593Smuzhiyun 	u8 first_slot;
297*4882a593Smuzhiyun 	u8 add_support;
298*4882a593Smuzhiyun 	u8 push_flag;
299*4882a593Smuzhiyun 	u8 push_button;			/* 0 = no pushbutton, 1 = pushbutton present */
300*4882a593Smuzhiyun 	u8 slot_switch_type;		/* 0 = no switch, 1 = switch present */
301*4882a593Smuzhiyun 	u8 defeature_PHP;		/* 0 = PHP not supported, 1 = PHP supported */
302*4882a593Smuzhiyun 	u8 alternate_base_address;	/* 0 = not supported, 1 = supported */
303*4882a593Smuzhiyun 	u8 pci_config_space;		/* Index/data access to working registers 0 = not supported, 1 = supported */
304*4882a593Smuzhiyun 	u8 pcix_speed_capability;	/* PCI-X */
305*4882a593Smuzhiyun 	u8 pcix_support;		/* PCI-X */
306*4882a593Smuzhiyun 	u16 vendor_id;
307*4882a593Smuzhiyun 	struct work_struct int_task_event;
308*4882a593Smuzhiyun 	wait_queue_head_t queue;	/* sleep & wake process */
309*4882a593Smuzhiyun 	struct dentry *dentry;		/* debugfs dentry */
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun 
312*4882a593Smuzhiyun struct irq_mapping {
313*4882a593Smuzhiyun 	u8 barber_pole;
314*4882a593Smuzhiyun 	u8 valid_INT;
315*4882a593Smuzhiyun 	u8 interrupt[4];
316*4882a593Smuzhiyun };
317*4882a593Smuzhiyun 
318*4882a593Smuzhiyun struct resource_lists {
319*4882a593Smuzhiyun 	struct pci_resource *mem_head;
320*4882a593Smuzhiyun 	struct pci_resource *p_mem_head;
321*4882a593Smuzhiyun 	struct pci_resource *io_head;
322*4882a593Smuzhiyun 	struct pci_resource *bus_head;
323*4882a593Smuzhiyun 	struct irq_mapping *irqs;
324*4882a593Smuzhiyun };
325*4882a593Smuzhiyun 
326*4882a593Smuzhiyun #define ROM_PHY_ADDR			0x0F0000
327*4882a593Smuzhiyun #define ROM_PHY_LEN			0x00ffff
328*4882a593Smuzhiyun 
329*4882a593Smuzhiyun #define PCI_HPC_ID			0xA0F7
330*4882a593Smuzhiyun #define PCI_SUB_HPC_ID			0xA2F7
331*4882a593Smuzhiyun #define PCI_SUB_HPC_ID2			0xA2F8
332*4882a593Smuzhiyun #define PCI_SUB_HPC_ID3			0xA2F9
333*4882a593Smuzhiyun #define PCI_SUB_HPC_ID_INTC		0xA2FA
334*4882a593Smuzhiyun #define PCI_SUB_HPC_ID4			0xA2FD
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun #define INT_BUTTON_IGNORE		0
337*4882a593Smuzhiyun #define INT_PRESENCE_ON			1
338*4882a593Smuzhiyun #define INT_PRESENCE_OFF		2
339*4882a593Smuzhiyun #define INT_SWITCH_CLOSE		3
340*4882a593Smuzhiyun #define INT_SWITCH_OPEN			4
341*4882a593Smuzhiyun #define INT_POWER_FAULT			5
342*4882a593Smuzhiyun #define INT_POWER_FAULT_CLEAR		6
343*4882a593Smuzhiyun #define INT_BUTTON_PRESS		7
344*4882a593Smuzhiyun #define INT_BUTTON_RELEASE		8
345*4882a593Smuzhiyun #define INT_BUTTON_CANCEL		9
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun #define STATIC_STATE			0
348*4882a593Smuzhiyun #define BLINKINGON_STATE		1
349*4882a593Smuzhiyun #define BLINKINGOFF_STATE		2
350*4882a593Smuzhiyun #define POWERON_STATE			3
351*4882a593Smuzhiyun #define POWEROFF_STATE			4
352*4882a593Smuzhiyun 
353*4882a593Smuzhiyun #define PCISLOT_INTERLOCK_CLOSED	0x00000001
354*4882a593Smuzhiyun #define PCISLOT_ADAPTER_PRESENT		0x00000002
355*4882a593Smuzhiyun #define PCISLOT_POWERED			0x00000004
356*4882a593Smuzhiyun #define PCISLOT_66_MHZ_OPERATION	0x00000008
357*4882a593Smuzhiyun #define PCISLOT_64_BIT_OPERATION	0x00000010
358*4882a593Smuzhiyun #define PCISLOT_REPLACE_SUPPORTED	0x00000020
359*4882a593Smuzhiyun #define PCISLOT_ADD_SUPPORTED		0x00000040
360*4882a593Smuzhiyun #define PCISLOT_INTERLOCK_SUPPORTED	0x00000080
361*4882a593Smuzhiyun #define PCISLOT_66_MHZ_SUPPORTED	0x00000100
362*4882a593Smuzhiyun #define PCISLOT_64_BIT_SUPPORTED	0x00000200
363*4882a593Smuzhiyun 
364*4882a593Smuzhiyun #define PCI_TO_PCI_BRIDGE_CLASS		0x00060400
365*4882a593Smuzhiyun 
366*4882a593Smuzhiyun #define INTERLOCK_OPEN			0x00000002
367*4882a593Smuzhiyun #define ADD_NOT_SUPPORTED		0x00000003
368*4882a593Smuzhiyun #define CARD_FUNCTIONING		0x00000005
369*4882a593Smuzhiyun #define ADAPTER_NOT_SAME		0x00000006
370*4882a593Smuzhiyun #define NO_ADAPTER_PRESENT		0x00000009
371*4882a593Smuzhiyun #define NOT_ENOUGH_RESOURCES		0x0000000B
372*4882a593Smuzhiyun #define DEVICE_TYPE_NOT_SUPPORTED	0x0000000C
373*4882a593Smuzhiyun #define POWER_FAILURE			0x0000000E
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun #define REMOVE_NOT_SUPPORTED		0x00000003
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun /*
379*4882a593Smuzhiyun  * error Messages
380*4882a593Smuzhiyun  */
381*4882a593Smuzhiyun #define msg_initialization_err	"Initialization failure, error=%d\n"
382*4882a593Smuzhiyun #define msg_HPC_rev_error	"Unsupported revision of the PCI hot plug controller found.\n"
383*4882a593Smuzhiyun #define msg_HPC_non_compaq_or_intel	"The PCI hot plug controller is not supported by this driver.\n"
384*4882a593Smuzhiyun #define msg_HPC_not_supported	"this system is not supported by this version of cpqphpd. Upgrade to a newer version of cpqphpd\n"
385*4882a593Smuzhiyun #define msg_unable_to_save	"unable to store PCI hot plug add resource information. This system must be rebooted before adding any PCI devices.\n"
386*4882a593Smuzhiyun #define msg_button_on		"PCI slot #%d - powering on due to button press.\n"
387*4882a593Smuzhiyun #define msg_button_off		"PCI slot #%d - powering off due to button press.\n"
388*4882a593Smuzhiyun #define msg_button_cancel	"PCI slot #%d - action canceled due to button press.\n"
389*4882a593Smuzhiyun #define msg_button_ignore	"PCI slot #%d - button press ignored.  (action in progress...)\n"
390*4882a593Smuzhiyun 
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun /* debugfs functions for the hotplug controller info */
393*4882a593Smuzhiyun void cpqhp_initialize_debugfs(void);
394*4882a593Smuzhiyun void cpqhp_shutdown_debugfs(void);
395*4882a593Smuzhiyun void cpqhp_create_debugfs_files(struct controller *ctrl);
396*4882a593Smuzhiyun void cpqhp_remove_debugfs_files(struct controller *ctrl);
397*4882a593Smuzhiyun 
398*4882a593Smuzhiyun /* controller functions */
399*4882a593Smuzhiyun void cpqhp_pushbutton_thread(struct timer_list *t);
400*4882a593Smuzhiyun irqreturn_t cpqhp_ctrl_intr(int IRQ, void *data);
401*4882a593Smuzhiyun int cpqhp_find_available_resources(struct controller *ctrl,
402*4882a593Smuzhiyun 				   void __iomem *rom_start);
403*4882a593Smuzhiyun int cpqhp_event_start_thread(void);
404*4882a593Smuzhiyun void cpqhp_event_stop_thread(void);
405*4882a593Smuzhiyun struct pci_func *cpqhp_slot_create(unsigned char busnumber);
406*4882a593Smuzhiyun struct pci_func *cpqhp_slot_find(unsigned char bus, unsigned char device,
407*4882a593Smuzhiyun 				 unsigned char index);
408*4882a593Smuzhiyun int cpqhp_process_SI(struct controller *ctrl, struct pci_func *func);
409*4882a593Smuzhiyun int cpqhp_process_SS(struct controller *ctrl, struct pci_func *func);
410*4882a593Smuzhiyun int cpqhp_hardware_test(struct controller *ctrl, int test_num);
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun /* resource functions */
413*4882a593Smuzhiyun int	cpqhp_resource_sort_and_combine(struct pci_resource **head);
414*4882a593Smuzhiyun 
415*4882a593Smuzhiyun /* pci functions */
416*4882a593Smuzhiyun int cpqhp_set_irq(u8 bus_num, u8 dev_num, u8 int_pin, u8 irq_num);
417*4882a593Smuzhiyun int cpqhp_get_bus_dev(struct controller *ctrl, u8 *bus_num, u8 *dev_num,
418*4882a593Smuzhiyun 		      u8 slot);
419*4882a593Smuzhiyun int cpqhp_save_config(struct controller *ctrl, int busnumber, int is_hot_plug);
420*4882a593Smuzhiyun int cpqhp_save_base_addr_length(struct controller *ctrl, struct pci_func *func);
421*4882a593Smuzhiyun int cpqhp_save_used_resources(struct controller *ctrl, struct pci_func *func);
422*4882a593Smuzhiyun int cpqhp_configure_board(struct controller *ctrl, struct pci_func *func);
423*4882a593Smuzhiyun int cpqhp_save_slot_config(struct controller *ctrl, struct pci_func *new_slot);
424*4882a593Smuzhiyun int cpqhp_valid_replace(struct controller *ctrl, struct pci_func *func);
425*4882a593Smuzhiyun void cpqhp_destroy_board_resources(struct pci_func *func);
426*4882a593Smuzhiyun int cpqhp_return_board_resources(struct pci_func *func,
427*4882a593Smuzhiyun 				 struct resource_lists *resources);
428*4882a593Smuzhiyun void cpqhp_destroy_resource_list(struct resource_lists *resources);
429*4882a593Smuzhiyun int cpqhp_configure_device(struct controller *ctrl, struct pci_func *func);
430*4882a593Smuzhiyun int cpqhp_unconfigure_device(struct pci_func *func);
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun /* Global variables */
433*4882a593Smuzhiyun extern int cpqhp_debug;
434*4882a593Smuzhiyun extern int cpqhp_legacy_mode;
435*4882a593Smuzhiyun extern struct controller *cpqhp_ctrl_list;
436*4882a593Smuzhiyun extern struct pci_func *cpqhp_slot_list[256];
437*4882a593Smuzhiyun extern struct irq_routing_table *cpqhp_routing_table;
438*4882a593Smuzhiyun 
439*4882a593Smuzhiyun /* these can be gotten rid of, but for debugging they are purty */
440*4882a593Smuzhiyun extern u8 cpqhp_nic_irq;
441*4882a593Smuzhiyun extern u8 cpqhp_disk_irq;
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun /* inline functions */
445*4882a593Smuzhiyun 
slot_name(struct slot * slot)446*4882a593Smuzhiyun static inline const char *slot_name(struct slot *slot)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	return hotplug_slot_name(&slot->hotplug_slot);
449*4882a593Smuzhiyun }
450*4882a593Smuzhiyun 
to_slot(struct hotplug_slot * hotplug_slot)451*4882a593Smuzhiyun static inline struct slot *to_slot(struct hotplug_slot *hotplug_slot)
452*4882a593Smuzhiyun {
453*4882a593Smuzhiyun 	return container_of(hotplug_slot, struct slot, hotplug_slot);
454*4882a593Smuzhiyun }
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun /*
457*4882a593Smuzhiyun  * return_resource
458*4882a593Smuzhiyun  *
459*4882a593Smuzhiyun  * Puts node back in the resource list pointed to by head
460*4882a593Smuzhiyun  */
return_resource(struct pci_resource ** head,struct pci_resource * node)461*4882a593Smuzhiyun static inline void return_resource(struct pci_resource **head,
462*4882a593Smuzhiyun 				   struct pci_resource *node)
463*4882a593Smuzhiyun {
464*4882a593Smuzhiyun 	if (!node || !head)
465*4882a593Smuzhiyun 		return;
466*4882a593Smuzhiyun 	node->next = *head;
467*4882a593Smuzhiyun 	*head = node;
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun 
set_SOGO(struct controller * ctrl)470*4882a593Smuzhiyun static inline void set_SOGO(struct controller *ctrl)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun 	u16 misc;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	misc = readw(ctrl->hpc_reg + MISC);
475*4882a593Smuzhiyun 	misc = (misc | 0x0001) & 0xFFFB;
476*4882a593Smuzhiyun 	writew(misc, ctrl->hpc_reg + MISC);
477*4882a593Smuzhiyun }
478*4882a593Smuzhiyun 
479*4882a593Smuzhiyun 
amber_LED_on(struct controller * ctrl,u8 slot)480*4882a593Smuzhiyun static inline void amber_LED_on(struct controller *ctrl, u8 slot)
481*4882a593Smuzhiyun {
482*4882a593Smuzhiyun 	u32 led_control;
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	led_control = readl(ctrl->hpc_reg + LED_CONTROL);
485*4882a593Smuzhiyun 	led_control |= (0x01010000L << slot);
486*4882a593Smuzhiyun 	writel(led_control, ctrl->hpc_reg + LED_CONTROL);
487*4882a593Smuzhiyun }
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 
amber_LED_off(struct controller * ctrl,u8 slot)490*4882a593Smuzhiyun static inline void amber_LED_off(struct controller *ctrl, u8 slot)
491*4882a593Smuzhiyun {
492*4882a593Smuzhiyun 	u32 led_control;
493*4882a593Smuzhiyun 
494*4882a593Smuzhiyun 	led_control = readl(ctrl->hpc_reg + LED_CONTROL);
495*4882a593Smuzhiyun 	led_control &= ~(0x01010000L << slot);
496*4882a593Smuzhiyun 	writel(led_control, ctrl->hpc_reg + LED_CONTROL);
497*4882a593Smuzhiyun }
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun 
read_amber_LED(struct controller * ctrl,u8 slot)500*4882a593Smuzhiyun static inline int read_amber_LED(struct controller *ctrl, u8 slot)
501*4882a593Smuzhiyun {
502*4882a593Smuzhiyun 	u32 led_control;
503*4882a593Smuzhiyun 
504*4882a593Smuzhiyun 	led_control = readl(ctrl->hpc_reg + LED_CONTROL);
505*4882a593Smuzhiyun 	led_control &= (0x01010000L << slot);
506*4882a593Smuzhiyun 
507*4882a593Smuzhiyun 	return led_control ? 1 : 0;
508*4882a593Smuzhiyun }
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun 
green_LED_on(struct controller * ctrl,u8 slot)511*4882a593Smuzhiyun static inline void green_LED_on(struct controller *ctrl, u8 slot)
512*4882a593Smuzhiyun {
513*4882a593Smuzhiyun 	u32 led_control;
514*4882a593Smuzhiyun 
515*4882a593Smuzhiyun 	led_control = readl(ctrl->hpc_reg + LED_CONTROL);
516*4882a593Smuzhiyun 	led_control |= 0x0101L << slot;
517*4882a593Smuzhiyun 	writel(led_control, ctrl->hpc_reg + LED_CONTROL);
518*4882a593Smuzhiyun }
519*4882a593Smuzhiyun 
green_LED_off(struct controller * ctrl,u8 slot)520*4882a593Smuzhiyun static inline void green_LED_off(struct controller *ctrl, u8 slot)
521*4882a593Smuzhiyun {
522*4882a593Smuzhiyun 	u32 led_control;
523*4882a593Smuzhiyun 
524*4882a593Smuzhiyun 	led_control = readl(ctrl->hpc_reg + LED_CONTROL);
525*4882a593Smuzhiyun 	led_control &= ~(0x0101L << slot);
526*4882a593Smuzhiyun 	writel(led_control, ctrl->hpc_reg + LED_CONTROL);
527*4882a593Smuzhiyun }
528*4882a593Smuzhiyun 
529*4882a593Smuzhiyun 
green_LED_blink(struct controller * ctrl,u8 slot)530*4882a593Smuzhiyun static inline void green_LED_blink(struct controller *ctrl, u8 slot)
531*4882a593Smuzhiyun {
532*4882a593Smuzhiyun 	u32 led_control;
533*4882a593Smuzhiyun 
534*4882a593Smuzhiyun 	led_control = readl(ctrl->hpc_reg + LED_CONTROL);
535*4882a593Smuzhiyun 	led_control &= ~(0x0101L << slot);
536*4882a593Smuzhiyun 	led_control |= (0x0001L << slot);
537*4882a593Smuzhiyun 	writel(led_control, ctrl->hpc_reg + LED_CONTROL);
538*4882a593Smuzhiyun }
539*4882a593Smuzhiyun 
540*4882a593Smuzhiyun 
slot_disable(struct controller * ctrl,u8 slot)541*4882a593Smuzhiyun static inline void slot_disable(struct controller *ctrl, u8 slot)
542*4882a593Smuzhiyun {
543*4882a593Smuzhiyun 	u8 slot_enable;
544*4882a593Smuzhiyun 
545*4882a593Smuzhiyun 	slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE);
546*4882a593Smuzhiyun 	slot_enable &= ~(0x01 << slot);
547*4882a593Smuzhiyun 	writeb(slot_enable, ctrl->hpc_reg + SLOT_ENABLE);
548*4882a593Smuzhiyun }
549*4882a593Smuzhiyun 
550*4882a593Smuzhiyun 
slot_enable(struct controller * ctrl,u8 slot)551*4882a593Smuzhiyun static inline void slot_enable(struct controller *ctrl, u8 slot)
552*4882a593Smuzhiyun {
553*4882a593Smuzhiyun 	u8 slot_enable;
554*4882a593Smuzhiyun 
555*4882a593Smuzhiyun 	slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE);
556*4882a593Smuzhiyun 	slot_enable |= (0x01 << slot);
557*4882a593Smuzhiyun 	writeb(slot_enable, ctrl->hpc_reg + SLOT_ENABLE);
558*4882a593Smuzhiyun }
559*4882a593Smuzhiyun 
560*4882a593Smuzhiyun 
is_slot_enabled(struct controller * ctrl,u8 slot)561*4882a593Smuzhiyun static inline u8 is_slot_enabled(struct controller *ctrl, u8 slot)
562*4882a593Smuzhiyun {
563*4882a593Smuzhiyun 	u8 slot_enable;
564*4882a593Smuzhiyun 
565*4882a593Smuzhiyun 	slot_enable = readb(ctrl->hpc_reg + SLOT_ENABLE);
566*4882a593Smuzhiyun 	slot_enable &= (0x01 << slot);
567*4882a593Smuzhiyun 	return slot_enable ? 1 : 0;
568*4882a593Smuzhiyun }
569*4882a593Smuzhiyun 
570*4882a593Smuzhiyun 
read_slot_enable(struct controller * ctrl)571*4882a593Smuzhiyun static inline u8 read_slot_enable(struct controller *ctrl)
572*4882a593Smuzhiyun {
573*4882a593Smuzhiyun 	return readb(ctrl->hpc_reg + SLOT_ENABLE);
574*4882a593Smuzhiyun }
575*4882a593Smuzhiyun 
576*4882a593Smuzhiyun 
577*4882a593Smuzhiyun /**
578*4882a593Smuzhiyun  * get_controller_speed - find the current frequency/mode of controller.
579*4882a593Smuzhiyun  *
580*4882a593Smuzhiyun  * @ctrl: controller to get frequency/mode for.
581*4882a593Smuzhiyun  *
582*4882a593Smuzhiyun  * Returns controller speed.
583*4882a593Smuzhiyun  */
get_controller_speed(struct controller * ctrl)584*4882a593Smuzhiyun static inline u8 get_controller_speed(struct controller *ctrl)
585*4882a593Smuzhiyun {
586*4882a593Smuzhiyun 	u8 curr_freq;
587*4882a593Smuzhiyun 	u16 misc;
588*4882a593Smuzhiyun 
589*4882a593Smuzhiyun 	if (ctrl->pcix_support) {
590*4882a593Smuzhiyun 		curr_freq = readb(ctrl->hpc_reg + NEXT_CURR_FREQ);
591*4882a593Smuzhiyun 		if ((curr_freq & 0xB0) == 0xB0)
592*4882a593Smuzhiyun 			return PCI_SPEED_133MHz_PCIX;
593*4882a593Smuzhiyun 		if ((curr_freq & 0xA0) == 0xA0)
594*4882a593Smuzhiyun 			return PCI_SPEED_100MHz_PCIX;
595*4882a593Smuzhiyun 		if ((curr_freq & 0x90) == 0x90)
596*4882a593Smuzhiyun 			return PCI_SPEED_66MHz_PCIX;
597*4882a593Smuzhiyun 		if (curr_freq & 0x10)
598*4882a593Smuzhiyun 			return PCI_SPEED_66MHz;
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun 		return PCI_SPEED_33MHz;
601*4882a593Smuzhiyun 	}
602*4882a593Smuzhiyun 
603*4882a593Smuzhiyun 	misc = readw(ctrl->hpc_reg + MISC);
604*4882a593Smuzhiyun 	return (misc & 0x0800) ? PCI_SPEED_66MHz : PCI_SPEED_33MHz;
605*4882a593Smuzhiyun }
606*4882a593Smuzhiyun 
607*4882a593Smuzhiyun 
608*4882a593Smuzhiyun /**
609*4882a593Smuzhiyun  * get_adapter_speed - find the max supported frequency/mode of adapter.
610*4882a593Smuzhiyun  *
611*4882a593Smuzhiyun  * @ctrl: hotplug controller.
612*4882a593Smuzhiyun  * @hp_slot: hotplug slot where adapter is installed.
613*4882a593Smuzhiyun  *
614*4882a593Smuzhiyun  * Returns adapter speed.
615*4882a593Smuzhiyun  */
get_adapter_speed(struct controller * ctrl,u8 hp_slot)616*4882a593Smuzhiyun static inline u8 get_adapter_speed(struct controller *ctrl, u8 hp_slot)
617*4882a593Smuzhiyun {
618*4882a593Smuzhiyun 	u32 temp_dword = readl(ctrl->hpc_reg + NON_INT_INPUT);
619*4882a593Smuzhiyun 	dbg("slot: %d, PCIXCAP: %8x\n", hp_slot, temp_dword);
620*4882a593Smuzhiyun 	if (ctrl->pcix_support) {
621*4882a593Smuzhiyun 		if (temp_dword & (0x10000 << hp_slot))
622*4882a593Smuzhiyun 			return PCI_SPEED_133MHz_PCIX;
623*4882a593Smuzhiyun 		if (temp_dword & (0x100 << hp_slot))
624*4882a593Smuzhiyun 			return PCI_SPEED_66MHz_PCIX;
625*4882a593Smuzhiyun 	}
626*4882a593Smuzhiyun 
627*4882a593Smuzhiyun 	if (temp_dword & (0x01 << hp_slot))
628*4882a593Smuzhiyun 		return PCI_SPEED_66MHz;
629*4882a593Smuzhiyun 
630*4882a593Smuzhiyun 	return PCI_SPEED_33MHz;
631*4882a593Smuzhiyun }
632*4882a593Smuzhiyun 
enable_slot_power(struct controller * ctrl,u8 slot)633*4882a593Smuzhiyun static inline void enable_slot_power(struct controller *ctrl, u8 slot)
634*4882a593Smuzhiyun {
635*4882a593Smuzhiyun 	u8 slot_power;
636*4882a593Smuzhiyun 
637*4882a593Smuzhiyun 	slot_power = readb(ctrl->hpc_reg + SLOT_POWER);
638*4882a593Smuzhiyun 	slot_power |= (0x01 << slot);
639*4882a593Smuzhiyun 	writeb(slot_power, ctrl->hpc_reg + SLOT_POWER);
640*4882a593Smuzhiyun }
641*4882a593Smuzhiyun 
disable_slot_power(struct controller * ctrl,u8 slot)642*4882a593Smuzhiyun static inline void disable_slot_power(struct controller *ctrl, u8 slot)
643*4882a593Smuzhiyun {
644*4882a593Smuzhiyun 	u8 slot_power;
645*4882a593Smuzhiyun 
646*4882a593Smuzhiyun 	slot_power = readb(ctrl->hpc_reg + SLOT_POWER);
647*4882a593Smuzhiyun 	slot_power &= ~(0x01 << slot);
648*4882a593Smuzhiyun 	writeb(slot_power, ctrl->hpc_reg + SLOT_POWER);
649*4882a593Smuzhiyun }
650*4882a593Smuzhiyun 
651*4882a593Smuzhiyun 
cpq_get_attention_status(struct controller * ctrl,struct slot * slot)652*4882a593Smuzhiyun static inline int cpq_get_attention_status(struct controller *ctrl, struct slot *slot)
653*4882a593Smuzhiyun {
654*4882a593Smuzhiyun 	u8 hp_slot;
655*4882a593Smuzhiyun 
656*4882a593Smuzhiyun 	hp_slot = slot->device - ctrl->slot_device_offset;
657*4882a593Smuzhiyun 
658*4882a593Smuzhiyun 	return read_amber_LED(ctrl, hp_slot);
659*4882a593Smuzhiyun }
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 
get_slot_enabled(struct controller * ctrl,struct slot * slot)662*4882a593Smuzhiyun static inline int get_slot_enabled(struct controller *ctrl, struct slot *slot)
663*4882a593Smuzhiyun {
664*4882a593Smuzhiyun 	u8 hp_slot;
665*4882a593Smuzhiyun 
666*4882a593Smuzhiyun 	hp_slot = slot->device - ctrl->slot_device_offset;
667*4882a593Smuzhiyun 
668*4882a593Smuzhiyun 	return is_slot_enabled(ctrl, hp_slot);
669*4882a593Smuzhiyun }
670*4882a593Smuzhiyun 
671*4882a593Smuzhiyun 
cpq_get_latch_status(struct controller * ctrl,struct slot * slot)672*4882a593Smuzhiyun static inline int cpq_get_latch_status(struct controller *ctrl,
673*4882a593Smuzhiyun 				       struct slot *slot)
674*4882a593Smuzhiyun {
675*4882a593Smuzhiyun 	u32 status;
676*4882a593Smuzhiyun 	u8 hp_slot;
677*4882a593Smuzhiyun 
678*4882a593Smuzhiyun 	hp_slot = slot->device - ctrl->slot_device_offset;
679*4882a593Smuzhiyun 	dbg("%s: slot->device = %d, ctrl->slot_device_offset = %d\n",
680*4882a593Smuzhiyun 	    __func__, slot->device, ctrl->slot_device_offset);
681*4882a593Smuzhiyun 
682*4882a593Smuzhiyun 	status = (readl(ctrl->hpc_reg + INT_INPUT_CLEAR) & (0x01L << hp_slot));
683*4882a593Smuzhiyun 
684*4882a593Smuzhiyun 	return (status == 0) ? 1 : 0;
685*4882a593Smuzhiyun }
686*4882a593Smuzhiyun 
687*4882a593Smuzhiyun 
get_presence_status(struct controller * ctrl,struct slot * slot)688*4882a593Smuzhiyun static inline int get_presence_status(struct controller *ctrl,
689*4882a593Smuzhiyun 				      struct slot *slot)
690*4882a593Smuzhiyun {
691*4882a593Smuzhiyun 	int presence_save = 0;
692*4882a593Smuzhiyun 	u8 hp_slot;
693*4882a593Smuzhiyun 	u32 tempdword;
694*4882a593Smuzhiyun 
695*4882a593Smuzhiyun 	hp_slot = slot->device - ctrl->slot_device_offset;
696*4882a593Smuzhiyun 
697*4882a593Smuzhiyun 	tempdword = readl(ctrl->hpc_reg + INT_INPUT_CLEAR);
698*4882a593Smuzhiyun 	presence_save = (int) ((((~tempdword) >> 23) | ((~tempdword) >> 15))
699*4882a593Smuzhiyun 				>> hp_slot) & 0x02;
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun 	return presence_save;
702*4882a593Smuzhiyun }
703*4882a593Smuzhiyun 
wait_for_ctrl_irq(struct controller * ctrl)704*4882a593Smuzhiyun static inline int wait_for_ctrl_irq(struct controller *ctrl)
705*4882a593Smuzhiyun {
706*4882a593Smuzhiyun 	DECLARE_WAITQUEUE(wait, current);
707*4882a593Smuzhiyun 	int retval = 0;
708*4882a593Smuzhiyun 
709*4882a593Smuzhiyun 	dbg("%s - start\n", __func__);
710*4882a593Smuzhiyun 	add_wait_queue(&ctrl->queue, &wait);
711*4882a593Smuzhiyun 	/* Sleep for up to 1 second to wait for the LED to change. */
712*4882a593Smuzhiyun 	msleep_interruptible(1000);
713*4882a593Smuzhiyun 	remove_wait_queue(&ctrl->queue, &wait);
714*4882a593Smuzhiyun 	if (signal_pending(current))
715*4882a593Smuzhiyun 		retval =  -EINTR;
716*4882a593Smuzhiyun 
717*4882a593Smuzhiyun 	dbg("%s - end\n", __func__);
718*4882a593Smuzhiyun 	return retval;
719*4882a593Smuzhiyun }
720*4882a593Smuzhiyun 
721*4882a593Smuzhiyun #include <asm/pci_x86.h>
cpqhp_routing_table_length(void)722*4882a593Smuzhiyun static inline int cpqhp_routing_table_length(void)
723*4882a593Smuzhiyun {
724*4882a593Smuzhiyun 	BUG_ON(cpqhp_routing_table == NULL);
725*4882a593Smuzhiyun 	return ((cpqhp_routing_table->size - sizeof(struct irq_routing_table)) /
726*4882a593Smuzhiyun 		sizeof(struct irq_info));
727*4882a593Smuzhiyun }
728*4882a593Smuzhiyun 
729*4882a593Smuzhiyun #endif
730