1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * cpcihp_zt5550.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Intel/Ziatech ZT5550 CompactPCI Host Controller driver definitions 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright 2002 SOMA Networks, Inc. 8*4882a593Smuzhiyun * Copyright 2001 Intel San Luis Obispo 9*4882a593Smuzhiyun * Copyright 2000,2001 MontaVista Software Inc. 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Send feedback to <scottm@somanetworks.com> 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _CPCIHP_ZT5550_H 15*4882a593Smuzhiyun #define _CPCIHP_ZT5550_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Direct registers */ 18*4882a593Smuzhiyun #define CSR_HCINDEX 0x00 19*4882a593Smuzhiyun #define CSR_HCDATA 0x04 20*4882a593Smuzhiyun #define CSR_INTSTAT 0x08 21*4882a593Smuzhiyun #define CSR_INTMASK 0x09 22*4882a593Smuzhiyun #define CSR_CNT0CMD 0x0C 23*4882a593Smuzhiyun #define CSR_CNT1CMD 0x0E 24*4882a593Smuzhiyun #define CSR_CNT0 0x10 25*4882a593Smuzhiyun #define CSR_CNT1 0x14 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Masks for interrupt bits in CSR_INTMASK direct register */ 28*4882a593Smuzhiyun #define CNT0_INT_MASK 0x01 29*4882a593Smuzhiyun #define CNT1_INT_MASK 0x02 30*4882a593Smuzhiyun #define ENUM_INT_MASK 0x04 31*4882a593Smuzhiyun #define ALL_DIRECT_INTS_MASK 0x07 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* Indexed registers (through CSR_INDEX, CSR_DATA) */ 34*4882a593Smuzhiyun #define HC_INT_MASK_REG 0x04 35*4882a593Smuzhiyun #define HC_STATUS_REG 0x08 36*4882a593Smuzhiyun #define HC_CMD_REG 0x0C 37*4882a593Smuzhiyun #define ARB_CONFIG_GNT_REG 0x10 38*4882a593Smuzhiyun #define ARB_CONFIG_CFG_REG 0x12 39*4882a593Smuzhiyun #define ARB_CONFIG_REG 0x10 40*4882a593Smuzhiyun #define ISOL_CONFIG_REG 0x18 41*4882a593Smuzhiyun #define FAULT_STATUS_REG 0x20 42*4882a593Smuzhiyun #define FAULT_CONFIG_REG 0x24 43*4882a593Smuzhiyun #define WD_CONFIG_REG 0x2C 44*4882a593Smuzhiyun #define HC_DIAG_REG 0x30 45*4882a593Smuzhiyun #define SERIAL_COMM_REG 0x34 46*4882a593Smuzhiyun #define SERIAL_OUT_REG 0x38 47*4882a593Smuzhiyun #define SERIAL_IN_REG 0x3C 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Masks for interrupt bits in HC_INT_MASK_REG indexed register */ 50*4882a593Smuzhiyun #define SERIAL_INT_MASK 0x01 51*4882a593Smuzhiyun #define FAULT_INT_MASK 0x02 52*4882a593Smuzhiyun #define HCF_INT_MASK 0x04 53*4882a593Smuzhiyun #define ALL_INDEXED_INTS_MASK 0x07 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* Digital I/O port storing ENUM# */ 56*4882a593Smuzhiyun #define ENUM_PORT 0xE1 57*4882a593Smuzhiyun /* Mask to get to the ENUM# bit on the bus */ 58*4882a593Smuzhiyun #define ENUM_MASK 0x40 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif /* _CPCIHP_ZT5550_H */ 61